History | View | Annotate | Download (359.9 kB)
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,this can be implemented in TCG instead of using softfloat.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate cmpb instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate prtyw and prtyd instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix 32-bit host compile, simplify code]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate fcpsgn instruction
target-ppc: fix nego and subf*o instructions
The overflow computation of nego and subf*o instructions has been brokenin commit ffe30937. Contrary to other targets, the instruction is subtractfrom an not subtract on PowerPC.
This patch fixes the issue by using the correct argument in the xor...
target-ppc: Fix narrow-mode add/sub carry output
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself wasfixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need toproduce the full 64-bit addition.
Simplify the conditions at the top of the functions for when we need a...
target-ppc: Fix add and subf carry generation in narrow mode
The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9aare only valid if the current word size == target_long size. This failedto take ppc64 in 32-bit (narrow) mode into account....
target-ppc: Use NARROW_MODE macro for branches
Removing conditional compilation in the process.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for tlbie
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-ppc: Fix SUBFE carry
While ~T0+T1+CF = T1-T0+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Use mul*2 in mulh* insns
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Split out SO, OV, CA fields from XER
In preparation for more efficient setting of these fields.
target-ppc: Use setcond in gen_op_cmp
Which means that callers need not copy data into local tmps.
target-ppc: Compute addition overflow without branches
target-ppc: Compute addition carry with setcond
target-ppc: Use add2 for carry generation
target-ppc: Implement neg in terms of subf
target-ppc: Compute arithmetic shift carry without branches
target-ppc: Compute mullwo without branches
target-ppc: Fix build for PPC_DEBUG_DISAS
In r5949 / 76db3ba44ee8db671f804755f13b016eefd13288 (target-ppc: memoryload/store rework) variable little_endian was replaced with ctx.le_mode.Update the debug code.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared asreserved in ppc32 ISAs. However, hardware simply ignores the bit, makingcode valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.
Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
PPC: Fix missing TRACE exception
This patch fixes bug 1031698 :https://bugs.launchpad.net/qemu/+bug/1031698
If we look at the (truncated) translation of the conditional branchinstruction in the test submitted in the bug post, the call to theexception helper is missing in the "bne-false" chunk of translated...
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
target-ppc: Extend FPU state for newer POWER CPUs
This patch adds some extra FPU state to CPUPPCState. Specifically,fpscr is extended to a target_ulong bits, since some recent (64 bit)CPUs now have more status bits than fit inside 32 bits. Also, we add...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-ppc: fix altivec instructions
Altivec instructions are not working anymore in PowerPC emulation,following commit d15f74fb, which inverted two registers in the callto helper. Fix that.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Fix build with --enable-debug
The order of the arguments was wrong (copy+paste error).
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG tosupport running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Avoid AREG0 for timebase helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Avoid AREG0 for misc helpers
ppc: Move load and store helpers, switch to AREG0 free mode
Add an explicit CPUPPCState parameter instead of relying on AREG0and rename op_helper.c (which only contains load and store helpers)to mem_helper.c. Remove AREG0 swapping intlb_fill().
Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation...
ppc: Avoid AREG0 for MMU etc. helpers
ppc: Avoid AREG0 for FPU and SPE helpers
ppc: Avoid AREG0 for integer and vector helpers
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
ppc: Avoid AREG0 for exception helpers
target-ppc: QOM'ify CPU reset
Move code from cpu_state_reset() into ppc_cpu_reset().Reorder #include of helper_regs.h to use it in translate_init.c.
Adjust whitespace and add braces.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>
PPC: KVM: Synchronize regs on CPU dump
When we dump the CPU registers, there's a certain chance they haven't beensynchronized with KVM yet, so we have to manually trigger that.
This aligns the code with x86 and fixes a bug where the register state wasbogus on invalid/unknown kvm exit reasons....
PPC64: Add support for ldbrx and stdbrx instructions
These instructions for loading and storing byte-swapped 64-bit values havebeen introduced in PowerISA 2.06.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>Signed-off-by: David Gibson <david@gibson.dropbear.id.au>...
target-ppc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-ppc: Clean includes
Remove some include statements which are not needed.
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>
PPC: E500: Implement msgclr
This patch implements the msgclr instruction. It is part of theEmbedded.Processor Control specification and clears pending doorbellinterrupts on the current CPU.
PPC: E500: Implement msgsnd
This patch implements the msgsnd instruction. It is part of theEmbedded.Processor Control specification and allows one CPU toIPI another CPU without going through an interrupt controller.
PPC: booke206: Implement tlbilx
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is usedto flush TLB entries. It's the recommended way of flushing in virtualizedenvironments.
So far we got away without implementing it, but Linux for e500mc uses this...
PPC: booke206: Check for TLB overrun
Our internal helpers to fetch TLB entries were not able to tell usthat an entry doesn't even exist. Pass an error out if we hit sucha case to not accidently pass beyond the TLB array.
PPC: e500: msync is 440 only, e500 has real sync
The e500 CPUs don't use 440's msync which falls on the same opcode IDs,but instead use the real powerpc sync instruction. This is important,since the invalid mask differs between the two.
PPC: rename msync to msync_4xx
The msync instruction as defined today is only valid on 4xx cores, noton e500 which also supports msync, but treats it the same way as sync.
Rename it to reflect that it's 4xx only.
PPC: Fix for the gdb single step problem on an rfi instruction
When using gdb to single step a ppc interrupt routine, the executionflow passes the rfi instruction without actually returning from theinterrupt.
The patch fixes this by avoiding to update the nip when the debug...
Set an invalid-bits mask for each SPE instructions
SPE instructions are defined by pairs. Currently, the invalid-bits mask is setfor the first instruction, but the second one can have a different mask.
example:GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),...
Implement POWER7's CFAR in TCG
This patch implements support for the CFAR SPR on POWER7 (Come FromAddress Register), which snapshots the PC value at the time of a branch oran rfid. The latest powerpc-next kernel also catches it and can show it inxmon or in the signal frames....
PPC: E500: Inject SPE exception on invalid SPE access
When accessing an SPE instruction despite it being not available,throw an SPE exception instead of an APU exception. That way theguest knows what's going on and actually uses SPE.
Reported-by: Jason Wessel <jason.wessel@windriver.com>...
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Only set lower 32bits with mtmsr
As Nathan pointed out correctly, the mtmsr instruction does not modifythe high 32 bits of MSR. It also doesn't matter if SF is set or not,the instruction always behaves the same.
This patch moves it a bit closer to the spec....
target-ppc: remove old CONFIG_SOFTFLOAT #ifdef
target-ppc has been switched to softfloat only long ago, but afew #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.
Cc: Alexander Graf <agraf@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currentlyselected CPU emulation, we have a feature mask of what exactly the respectiveinstruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),and display them in "info registers".
Also get CR and PID from the existing KVM_GET_REGS.
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introducedin POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results...
target-ppc: ext32u instead of andi with constant
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: add support for 6 SPE instructions
Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}}
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: Correct BookE tlb reads
Call the tlb read helper (and not the write helper) for tlbreads.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Fix translation of unary PPC/SPE instructions (efdneg etc.).
Signed-off-by: Mike Pall <mike-lp10@luajit.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
PPC: Enable hint bits for lwarx/ldarx
The lwarx and ldarx instructions have a bit to give some hint to theCPU which is safe to ignore. We currently refuse to accept any instructionwith that bit set, as it used to be declared MBZ.
Let's remove the reserved bit and make the instruction work as expected....
target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix %lld or %llx printf format use
target-ppc: Remove duplicate cpu log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.
PPC: avoid function pointer type mismatch, spotted by clang
Fixes clang errors: CC ppc-softmmu/translate.o/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) {...
target-ppc: fix evsrwu and evsrws (second try)
target-ppc: fix evsrwu and evsrws
target-ppc: fix evslw instruction
Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if thiscode is never executed. Don't print an error message on the console,but keep the message in the log for debugging purposes....
target-ppc: stop translation after a trap instruction
target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,not extracted, and so used the wrong shift amounts to sign-extend or padwith zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-ppc: log instructions start in TCG code
static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Replace REGX with PRIx64