Archipelago » qemu

/*

 *  PowerPC emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

/* Include definitions for instructions classes and implementations flags */

//#define DO_SINGLE_STEP

//#define PPC_DEBUG_DISAS

//#define DEBUG_MEMORY_ACCESSES

//#define DO_PPC_STATISTICS

/*****************************************************************************/

/* Code translation helpers                                                  */

#if defined(USE_DIRECT_JUMP)

#define TBPARAM(x)

#else

#define TBPARAM(x) (long)(x)

#endif

enum {

#define DEF(s, n, copy_size) INDEX_op_ ## s,

#include "opc.h"

#undef DEF

    NB_OPS,

};

static uint16_t *gen_opc_ptr;

static uint32_t *gen_opparam_ptr;

#include "gen-op.h"

static always_inline void gen_set_T0 (target_ulong val)

{

#if defined(TARGET_PPC64)

    if (val >> 32)

        gen_op_set_T0_64(val >> 32, val);

    else

#endif

        gen_op_set_T0(val);

}

static always_inline void gen_set_T1 (target_ulong val)

{

#if defined(TARGET_PPC64)

    if (val >> 32)

        gen_op_set_T1_64(val >> 32, val);

    else

#endif

        gen_op_set_T1(val);

}

#define GEN8(func, NAME)                                                      \

static GenOpFunc *NAME ## _table [8] = {                                      \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

};                                                                            \

static always_inline void func (int n)                                        \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#define GEN16(func, NAME)                                                     \

static GenOpFunc *NAME ## _table [16] = {                                     \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

};                                                                            \

static always_inline void func (int n)                                        \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

#define GEN32(func, NAME)                                                     \

static GenOpFunc *NAME ## _table [32] = {                                     \

NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \

NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \

NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \

NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \

NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \

NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \

NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \

NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \

};                                                                            \

static always_inline void func (int n)                                        \

{                                                                             \

    NAME ## _table[n]();                                                      \

}

/* Condition register moves */

GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);

GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);

GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);

GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);

/* Floating point condition and status register moves */

GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);

GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);

GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);

static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)

{

    gen_op_set_T0(param);

    gen_op_store_T0_fpscr(n);

}

/* General purpose registers moves */

GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);

GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);

GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);

GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);

GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);

#if 0 // unused

GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);

#endif

/* floating point registers moves */

GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);

GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);

GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);

GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);

GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);

#if 0 // unused

GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);

#endif

/* internal defines */

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong nip;

    uint32_t opcode;

    uint32_t exception;

    /* Routine used to access memory */

    int mem_idx;

    /* Translation flags */

#if !defined(CONFIG_USER_ONLY)

    int supervisor;

#endif

#if defined(TARGET_PPC64)

    int sf_mode;

#endif

    int fpu_enabled;

    int altivec_enabled;

#if defined(TARGET_PPCEMB)

    int spe_enabled;

#endif

    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */

    int singlestep_enabled;

    int dcache_line_size;

} DisasContext;

struct opc_handler_t {

    /* invalid bits */

    uint32_t inval;

    /* instruction type */

    uint64_t type;

    /* handler */

    void (*handler)(DisasContext *ctx);

#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)

    const unsigned char *oname;

#endif

#if defined(DO_PPC_STATISTICS)

    uint64_t count;

#endif

};

static always_inline void gen_set_Rc0 (DisasContext *ctx)

{

#if defined(TARGET_PPC64)

    if (ctx->sf_mode)

        gen_op_cmpi_64(0);

    else

#endif

        gen_op_cmpi(0);

    gen_op_set_Rc0();

}

static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)

{

#if defined(TARGET_PPC64)

    if (ctx->sf_mode)

        gen_op_update_nip_64(nip >> 32, nip);

    else

#endif

        gen_op_update_nip(nip);

}

#define GEN_EXCP(ctx, excp, error)                                            \

do {                                                                          \

    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \

        gen_update_nip(ctx, (ctx)->nip);                                      \

    }                                                                         \

    gen_op_raise_exception_err((excp), (error));                              \

    ctx->exception = (excp);                                                  \

} while (0)

#define GEN_EXCP_INVAL(ctx)                                                   \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)

#define GEN_EXCP_PRIVOPC(ctx)                                                 \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)

#define GEN_EXCP_PRIVREG(ctx)                                                 \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)

#define GEN_EXCP_NO_FP(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)

#define GEN_EXCP_NO_AP(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)

#define GEN_EXCP_NO_VR(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)

/* Stop translation */

static always_inline void GEN_STOP (DisasContext *ctx)

{

    gen_update_nip(ctx, ctx->nip);

    ctx->exception = POWERPC_EXCP_STOP;

}

/* No need to update nip here, as execution flow will change */

static always_inline void GEN_SYNC (DisasContext *ctx)

{

    ctx->exception = POWERPC_EXCP_SYNC;

}

#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \

static void gen_##name (DisasContext *ctx);                                   \

GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \

static void gen_##name (DisasContext *ctx)

#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \

static void gen_##name (DisasContext *ctx);                                   \

GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \

static void gen_##name (DisasContext *ctx)

typedef struct opcode_t {

    unsigned char opc1, opc2, opc3;

#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */

    unsigned char pad[5];

#else

    unsigned char pad[1];

#endif

    opc_handler_t handler;

    const unsigned char *oname;

} opcode_t;

/*****************************************************************************/

/***                           Instruction decoding                        ***/

#define EXTRACT_HELPER(name, shift, nb)                                       \

static always_inline uint32_t name (uint32_t opcode)                          \

{                                                                             \

    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \

}

#define EXTRACT_SHELPER(name, shift, nb)                                      \

static always_inline int32_t name (uint32_t opcode)                           \

{                                                                             \

    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \

}

/* Opcode part 1 */

EXTRACT_HELPER(opc1, 26, 6);

/* Opcode part 2 */

EXTRACT_HELPER(opc2, 1, 5);

/* Opcode part 3 */

EXTRACT_HELPER(opc3, 6, 5);

/* Update Cr0 flags */

EXTRACT_HELPER(Rc, 0, 1);

/* Destination */

EXTRACT_HELPER(rD, 21, 5);

/* Source */

EXTRACT_HELPER(rS, 21, 5);

/* First operand */

EXTRACT_HELPER(rA, 16, 5);

/* Second operand */

EXTRACT_HELPER(rB, 11, 5);

/* Third operand */

EXTRACT_HELPER(rC, 6, 5);

/***                               Get CRn                                 ***/

EXTRACT_HELPER(crfD, 23, 3);

EXTRACT_HELPER(crfS, 18, 3);

EXTRACT_HELPER(crbD, 21, 5);

EXTRACT_HELPER(crbA, 16, 5);

EXTRACT_HELPER(crbB, 11, 5);

/* SPR / TBL */

EXTRACT_HELPER(_SPR, 11, 10);

static always_inline uint32_t SPR (uint32_t opcode)

{

    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);

}

/***                              Get constants                            ***/

EXTRACT_HELPER(IMM, 12, 8);

/* 16 bits signed immediate value */

EXTRACT_SHELPER(SIMM, 0, 16);

/* 16 bits unsigned immediate value */

EXTRACT_HELPER(UIMM, 0, 16);

/* Bit count */

EXTRACT_HELPER(NB, 11, 5);

/* Shift count */

EXTRACT_HELPER(SH, 11, 5);

/* Mask start */

EXTRACT_HELPER(MB, 6, 5);

/* Mask end */

EXTRACT_HELPER(ME, 1, 5);

/* Trap operand */

EXTRACT_HELPER(TO, 21, 5);

EXTRACT_HELPER(CRM, 12, 8);

EXTRACT_HELPER(FM, 17, 8);

EXTRACT_HELPER(SR, 16, 4);

EXTRACT_HELPER(FPIMM, 20, 4);

/***                            Jump target decoding                       ***/

/* Displacement */

EXTRACT_SHELPER(d, 0, 16);

/* Immediate address */

static always_inline target_ulong LI (uint32_t opcode)

{

    return (opcode >> 0) & 0x03FFFFFC;

}

static always_inline uint32_t BD (uint32_t opcode)

{

    return (opcode >> 0) & 0xFFFC;

}

EXTRACT_HELPER(BO, 21, 5);

EXTRACT_HELPER(BI, 16, 5);

/* Absolute/relative address */

EXTRACT_HELPER(AA, 1, 1);

/* Link */

EXTRACT_HELPER(LK, 0, 1);

/* Create a mask between <start> and <end> bits */

static always_inline target_ulong MASK (uint32_t start, uint32_t end)

{

    target_ulong ret;

#if defined(TARGET_PPC64)

    if (likely(start == 0)) {

        ret = (uint64_t)(-1ULL) << (63 - end);

    } else if (likely(end == 63)) {

        ret = (uint64_t)(-1ULL) >> start;

    }

#else

    if (likely(start == 0)) {

        ret = (uint32_t)(-1ULL) << (31  - end);

    } else if (likely(end == 31)) {

        ret = (uint32_t)(-1ULL) >> start;

    }

#endif

    else {

        ret = (((target_ulong)(-1ULL)) >> (start)) ^

            (((target_ulong)(-1ULL) >> (end)) >> 1);

        if (unlikely(start > end))

            return ~ret;

    }

    return ret;

}

/*****************************************************************************/

/* PowerPC Instructions types definitions                                    */

enum {

    PPC_NONE          = 0x0000000000000000ULL,

    /* PowerPC base instructions set                                         */

    PPC_INSNS_BASE    = 0x0000000000000001ULL,

    /* integer operations instructions                                       */

#define PPC_INTEGER PPC_INSNS_BASE

    /* flow control instructions                                             */

#define PPC_FLOW    PPC_INSNS_BASE

    /* virtual memory instructions                                           */

#define PPC_MEM     PPC_INSNS_BASE

    /* ld/st with reservation instructions                                   */

#define PPC_RES     PPC_INSNS_BASE

    /* cache control instructions                                            */

#define PPC_CACHE   PPC_INSNS_BASE

    /* spr/msr access instructions                                           */

#define PPC_MISC    PPC_INSNS_BASE

    /* Optional floating point instructions                                  */

    PPC_FLOAT         = 0x0000000000000002ULL,

    PPC_FLOAT_FSQRT   = 0x0000000000000004ULL,

    PPC_FLOAT_FRES    = 0x0000000000000008ULL,

    PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,

    PPC_FLOAT_FSEL    = 0x0000000000000020ULL,

    PPC_FLOAT_STFIWX  = 0x0000000000000040ULL,

    /* external control instructions                                         */

    PPC_EXTERN        = 0x0000000000000080ULL,

    /* segment register access instructions                                  */

    PPC_SEGMENT       = 0x0000000000000100ULL,

    /* Optional cache control instruction                                    */

    PPC_CACHE_DCBA    = 0x0000000000000200ULL,

    /* Optional memory control instructions                                  */

    PPC_MEM_TLBIA     = 0x0000000000000400ULL,

    PPC_MEM_TLBIE     = 0x0000000000000800ULL,

    PPC_MEM_TLBSYNC   = 0x0000000000001000ULL,

    /* eieio & sync                                                          */

    PPC_MEM_SYNC      = 0x0000000000002000ULL,

    /* PowerPC 6xx TLB management instructions                               */

    PPC_6xx_TLB       = 0x0000000000004000ULL,

    /* Altivec support                                                       */

    PPC_ALTIVEC       = 0x0000000000008000ULL,

    /* Time base mftb instruction                                            */

    PPC_MFTB          = 0x0000000000010000ULL,

    /* Embedded PowerPC dedicated instructions                               */

    PPC_EMB_COMMON    = 0x0000000000020000ULL,

    /* PowerPC 40x exception model                                           */

    PPC_40x_EXCP      = 0x0000000000040000ULL,

    /* PowerPC 40x TLB management instructions                               */

    PPC_40x_TLB       = 0x0000000000080000ULL,

    /* PowerPC 405 Mac instructions                                          */

    PPC_405_MAC       = 0x0000000000100000ULL,

    /* PowerPC 440 specific instructions                                     */

    PPC_440_SPEC      = 0x0000000000200000ULL,

    /* Power-to-PowerPC bridge (601)                                         */

    PPC_POWER_BR      = 0x0000000000400000ULL,

    /* PowerPC 602 specific                                                  */

    PPC_602_SPEC      = 0x0000000000800000ULL,

    /* Deprecated instructions                                               */

    /* Original POWER instruction set                                        */

    PPC_POWER         = 0x0000000001000000ULL,

    /* POWER2 instruction set extension                                      */

    PPC_POWER2        = 0x0000000002000000ULL,

    /* Power RTC support                                                     */

    PPC_POWER_RTC     = 0x0000000004000000ULL,

    /* 64 bits PowerPC instruction set                                       */

    PPC_64B           = 0x0000000008000000ULL,

    /* 64 bits hypervisor extensions                                         */

    PPC_64H           = 0x0000000010000000ULL,

    /* segment register access instructions for PowerPC 64 "bridge"          */

    PPC_SEGMENT_64B   = 0x0000000020000000ULL,

    /* BookE (embedded) PowerPC specification                                */

    PPC_BOOKE         = 0x0000000040000000ULL,

    /* eieio                                                                 */

    PPC_MEM_EIEIO     = 0x0000000080000000ULL,

    /* e500 vector instructions                                              */

    PPC_E500_VECTOR   = 0x0000000100000000ULL,

    /* PowerPC 4xx dedicated instructions                                    */

    PPC_4xx_COMMON    = 0x0000000200000000ULL,

    /* PowerPC 2.03 specification extensions                                 */

    PPC_203           = 0x0000000400000000ULL,

    /* PowerPC 2.03 SPE extension                                            */

    PPC_SPE           = 0x0000000800000000ULL,

    /* PowerPC 2.03 SPE floating-point extension                             */

    PPC_SPEFPU        = 0x0000001000000000ULL,

    /* SLB management                                                        */

    PPC_SLBI          = 0x0000002000000000ULL,

    /* PowerPC 40x ibct instructions                                         */

    PPC_40x_ICBT      = 0x0000004000000000ULL,

    /* PowerPC 74xx TLB management instructions                              */

    PPC_74xx_TLB      = 0x0000008000000000ULL,

    /* More BookE (embedded) instructions...                                 */

    PPC_BOOKE_EXT     = 0x0000010000000000ULL,

    /* rfmci is not implemented in all BookE PowerPC                         */

    PPC_RFMCI         = 0x0000020000000000ULL,

    /* user-mode DCR access, implemented in PowerPC 460                      */

    PPC_DCRUX         = 0x0000040000000000ULL,

    /* New floating-point extensions (PowerPC 2.0x)                          */

    PPC_FLOAT_EXT     = 0x0000080000000000ULL,

    /* New wait instruction (PowerPC 2.0x)                                   */

    PPC_WAIT          = 0x0000100000000000ULL,

    /* New 64 bits extensions (PowerPC 2.0x)                                 */

    PPC_64BX          = 0x0000200000000000ULL,

    /* dcbz instruction with fixed cache line size                           */

    PPC_CACHE_DCBZ    = 0x0000400000000000ULL,

    /* dcbz instruction with tunable cache line size                         */

    PPC_CACHE_DCBZT   = 0x0000800000000000ULL,

};

/*****************************************************************************/

/* PowerPC instructions table                                                */

#if HOST_LONG_BITS == 64

#define OPC_ALIGN 8

#else

#define OPC_ALIGN 4

#endif

#if defined(__APPLE__)

#define OPCODES_SECTION                                                       \

    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))

#else

#define OPCODES_SECTION                                                       \

    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))

#endif

#if defined(DO_PPC_STATISTICS)

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

        .oname = stringify(name),                                             \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

        .oname = onam,                                                        \

    },                                                                        \

    .oname = onam,                                                            \

}

#else

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = onam,                                                            \

}

#endif

#define GEN_OPCODE_MARK(name)                                                 \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = 0xFF,                                                             \

    .opc2 = 0xFF,                                                             \

    .opc3 = 0xFF,                                                             \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = 0x00000000,                                                \

        .type = 0x00,                                                         \

        .handler = NULL,                                                      \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

/* Start opcode list */

GEN_OPCODE_MARK(start);

/* Invalid instruction */

GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)

{

    GEN_EXCP_INVAL(ctx);

}

static opc_handler_t invalid_handler = {

    .inval   = 0xFFFFFFFF,

    .type    = PPC_NONE,

    .handler = gen_invalid,

};

/***                           Integer arithmetic                          ***/

#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \

GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \

GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_##name();                                                          \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

/* Two operands arithmetic functions */

#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \

__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \

__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)

/* Two operands arithmetic functions with no overflow allowed */

#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \

__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)

/* One operand arithmetic functions */

#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \

__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \

__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)

#if defined(TARGET_PPC64)

#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \

GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    if (ctx->sf_mode)                                                         \

        gen_op_##name##_64();                                                 \

    else                                                                      \

        gen_op_##name();                                                      \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \

GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \

    if (ctx->sf_mode)                                                         \

        gen_op_##name##_64();                                                 \

    else                                                                      \

        gen_op_##name();                                                      \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    if (ctx->sf_mode)                                                         \

        gen_op_##name##_64();                                                 \

    else                                                                      \

        gen_op_##name();                                                      \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \

GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \

{                                                                             \

    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \

    if (ctx->sf_mode)                                                         \

        gen_op_##name##_64();                                                 \

    else                                                                      \

        gen_op_##name();                                                      \

    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \

    if (unlikely(Rc(ctx->opcode) != 0))                                       \

        gen_set_Rc0(ctx);                                                     \

}

/* Two operands arithmetic functions */

#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \

__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \

__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)

/* Two operands arithmetic functions with no overflow allowed */

#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \

__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)

/* One operand arithmetic functions */

#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \

__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \

__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)

#else

#define GEN_INT_ARITH2_64 GEN_INT_ARITH2

#define GEN_INT_ARITHN_64 GEN_INT_ARITHN

#define GEN_INT_ARITH1_64 GEN_INT_ARITH1

#endif

/* add    add.    addo    addo.    */

static always_inline void gen_op_addo (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addo();

}

#if defined(TARGET_PPC64)

#define gen_op_add_64 gen_op_add

static always_inline void gen_op_addo_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addo_64();

}

#endif

GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);

/* addc   addc.   addco   addco.   */

static always_inline void gen_op_addc (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addc();

}

static always_inline void gen_op_addco (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addc();

    gen_op_check_addo();

}

#if defined(TARGET_PPC64)

static always_inline void gen_op_addc_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addc_64();

}

static always_inline void gen_op_addco_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_add();

    gen_op_check_addc_64();

    gen_op_check_addo_64();

}

#endif

GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);

/* adde   adde.   addeo   addeo.   */

static always_inline void gen_op_addeo (void)

{

    gen_op_move_T2_T0();

    gen_op_adde();

    gen_op_check_addo();

}

#if defined(TARGET_PPC64)

static always_inline void gen_op_addeo_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_adde_64();

    gen_op_check_addo_64();

}

#endif

GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);

/* addme  addme.  addmeo  addmeo.  */

static always_inline void gen_op_addme (void)

{

    gen_op_move_T1_T0();

    gen_op_add_me();

}

#if defined(TARGET_PPC64)

static always_inline void gen_op_addme_64 (void)

{

    gen_op_move_T1_T0();

    gen_op_add_me_64();

}

#endif

GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);

/* addze  addze.  addzeo  addzeo.  */

static always_inline void gen_op_addze (void)

{

    gen_op_move_T2_T0();

    gen_op_add_ze();

    gen_op_check_addc();

}

static always_inline void gen_op_addzeo (void)

{

    gen_op_move_T2_T0();

    gen_op_add_ze();

    gen_op_check_addc();

    gen_op_check_addo();

}

#if defined(TARGET_PPC64)

static always_inline void gen_op_addze_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_add_ze();

    gen_op_check_addc_64();

}

static always_inline void gen_op_addzeo_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_add_ze();

    gen_op_check_addc_64();

    gen_op_check_addo_64();

}

#endif

GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);

/* divw   divw.   divwo   divwo.   */

GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);

/* divwu  divwu.  divwuo  divwuo.  */

GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);

/* mulhw  mulhw.                   */

GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);

/* mulhwu mulhwu.                  */

GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);

/* mullw  mullw.  mullwo  mullwo.  */

GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);

/* neg    neg.    nego    nego.    */

GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);

/* subf   subf.   subfo   subfo.   */

static always_inline void gen_op_subfo (void)

{

    gen_op_move_T2_T0();

    gen_op_subf();

    gen_op_check_subfo();

}

#if defined(TARGET_PPC64)

#define gen_op_subf_64 gen_op_subf

static always_inline void gen_op_subfo_64 (void)

{

    gen_op_move_T2_T0();

    gen_op_subf();

    gen_op_check_subfo_64();

}

#endif

GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);

/* subfc  subfc.  subfco  subfco.  */

static always_inline void gen_op_subfc (void)

{

    gen_op_subf();

    gen_op_check_subfc();

}

static always_inline void gen_op_subfco (void)

{

    gen_op_move_T2_T0();

    gen_op_subf();

    gen_op_check_subfc();

    gen_op_check_subfo();

}

#if defined(TARGET_PPC64)