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/*
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 *  SH4 emulation
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 *
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 *  Copyright (c) 2005 Samuel Tardieu
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec.h"
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static inline void set_t(void)
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{
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    env->sr |= SR_T;
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}
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static inline void clr_t(void)
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{
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    env->sr &= ~SR_T;
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}
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static inline void cond_t(int cond)
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{
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    if (cond)
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        set_t();
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    else
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        clr_t();
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}
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void OPPROTO op_movl_imm_T0(void)
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{
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    T0 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_movl_imm_T1(void)
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{
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    T1 = (uint32_t) PARAM1;
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    RETURN();
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}
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void OPPROTO op_cmp_eq_imm_T0(void)
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{
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    cond_t((int32_t) T0 == (int32_t) PARAM1);
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    RETURN();
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}
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void OPPROTO op_not_T0(void)
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{
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    T0 = ~T0;
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    RETURN();
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}
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void OPPROTO op_bf_s(void)
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{
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    env->delayed_pc = PARAM1;
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    if (!(env->sr & SR_T)) {
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        env->flags |= DELAY_SLOT_TRUE;
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    }
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    RETURN();
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}
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void OPPROTO op_bt_s(void)
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{
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    env->delayed_pc = PARAM1;
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    if (env->sr & SR_T) {
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        env->flags |= DELAY_SLOT_TRUE;
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    }
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    RETURN();
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}
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void OPPROTO op_store_flags(void)
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{
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    env->flags &= DELAY_SLOT_TRUE;
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    env->flags |= PARAM1;
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    RETURN();
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}
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void OPPROTO op_bra(void)
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{
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    env->delayed_pc = PARAM1;
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    RETURN();
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}
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void OPPROTO op_braf_T0(void)
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{
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    env->delayed_pc = PARAM1 + T0;
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    RETURN();
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}
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void OPPROTO op_bsr(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM2;
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    RETURN();
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}
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void OPPROTO op_bsrf_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = PARAM1 + T0;
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    RETURN();
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}
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void OPPROTO op_jsr_T0(void)
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{
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    env->pr = PARAM1;
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    env->delayed_pc = T0;
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    RETURN();
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}
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void OPPROTO op_rts(void)
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{
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    env->delayed_pc = env->pr;
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    RETURN();
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}
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void OPPROTO op_addl_imm_T0(void)
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{
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    T0 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_addl_imm_T1(void)
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{
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    T1 += PARAM1;
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    RETURN();
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}
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void OPPROTO op_clrmac(void)
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{
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    env->mach = env->macl = 0;
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    RETURN();
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}
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void OPPROTO op_clrs(void)
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{
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    env->sr &= ~SR_S;
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    RETURN();
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}
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void OPPROTO op_clrt(void)
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{
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    env->sr &= ~SR_T;
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    RETURN();
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}
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void OPPROTO op_ldtlb(void)
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{
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    helper_ldtlb();
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    RETURN();
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}
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void OPPROTO op_sets(void)
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{
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    env->sr |= SR_S;
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    RETURN();
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}
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void OPPROTO op_sett(void)
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{
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    env->sr |= SR_T;
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    RETURN();
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}
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void OPPROTO op_frchg(void)
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{
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    env->fpscr ^= FPSCR_FR;
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    RETURN();
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}
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void OPPROTO op_fschg(void)
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{
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    env->fpscr ^= FPSCR_SZ;
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    RETURN();
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}
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void OPPROTO op_rte(void)
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{
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    env->sr = env->ssr;
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    env->delayed_pc = env->spc;
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    RETURN();
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}
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void OPPROTO op_swapb_T0(void)
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{
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    T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff);
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    RETURN();
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}
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void OPPROTO op_swapw_T0(void)
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{
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    T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_xtrct_T0_T1(void)
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{
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    T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff);
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    RETURN();
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}
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void OPPROTO op_add_T0_T1(void)
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{
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    T1 += T0;
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    RETURN();
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}
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void OPPROTO op_addc_T0_T1(void)
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{
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    helper_addc_T0_T1();
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    RETURN();
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}
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void OPPROTO op_addv_T0_T1(void)
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{
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    helper_addv_T0_T1();
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    RETURN();
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}
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void OPPROTO op_cmp_eq_T0_T1(void)
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{
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    cond_t(T1 == T0);
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    RETURN();
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}
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void OPPROTO op_cmp_ge_T0_T1(void)
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{
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    cond_t((int32_t) T1 >= (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_gt_T0_T1(void)
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{
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    cond_t((int32_t) T1 > (int32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hi_T0_T1(void)
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{
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    cond_t((uint32_t) T1 > (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_hs_T0_T1(void)
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{
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    cond_t((uint32_t) T1 >= (uint32_t) T0);
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    RETURN();
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}
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void OPPROTO op_cmp_str_T0_T1(void)
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{
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    cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) ||
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           (T0 & 0x0000ff00) == (T1 & 0x0000ff00) ||
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           (T0 & 0x00ff0000) == (T1 & 0x00ff0000) ||
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           (T0 & 0xff000000) == (T1 & 0xff000000));
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    RETURN();
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}
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void OPPROTO op_tst_T0_T1(void)
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{
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    cond_t((T1 & T0) == 0);
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    RETURN();
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}
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void OPPROTO op_div0s_T0_T1(void)
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{
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    if (T1 & 0x80000000)
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        env->sr |= SR_Q;
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    else
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        env->sr &= ~SR_Q;
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    if (T0 & 0x80000000)
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        env->sr |= SR_M;
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    else
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        env->sr &= ~SR_M;
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    cond_t((T1 ^ T0) & 0x80000000);
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    RETURN();
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}
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void OPPROTO op_div0u(void)
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{
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    env->sr &= ~(SR_M | SR_Q | SR_T);
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    RETURN();
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}
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void OPPROTO op_div1_T0_T1(void)
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{
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    helper_div1_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulsl_T0_T1(void)
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{
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    helper_dmulsl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_dmulul_T0_T1(void)
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{
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    helper_dmulul_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macl_T0_T1(void)
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{
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    helper_macl_T0_T1();
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    RETURN();
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}
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void OPPROTO op_macw_T0_T1(void)
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{
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    helper_macw_T0_T1();
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    RETURN();
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}
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void OPPROTO op_mull_T0_T1(void)
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{
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    env->macl = (T0 * T1) & 0xffffffff;
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    RETURN();
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}
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void OPPROTO op_mulsw_T0_T1(void)
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{
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    env->macl = (int32_t)(int16_t) T0 *(int32_t)(int16_t) T1;
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    RETURN();
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}
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void OPPROTO op_muluw_T0_T1(void)
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{
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    env->macl = (uint32_t)(uint16_t) T0 *(uint32_t)(uint16_t) T1;
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    RETURN();
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}
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void OPPROTO op_neg_T0(void)
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{
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    T0 = -T0;
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    RETURN();
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}
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void OPPROTO op_negc_T0(void)
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{
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    helper_negc_T0();
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    RETURN();
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}
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void OPPROTO op_shad_T0_T1(void)
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{
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    if ((T0 & 0x80000000) == 0)
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        T1 <<= (T0 & 0x1f);
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    else if ((T0 & 0x1f) == 0)
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        T1 = (T1 & 0x80000000)? 0xffffffff : 0;
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    else
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        T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1);
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    RETURN();
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}
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void OPPROTO op_shld_T0_T1(void)
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{
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    if ((T0 & 0x80000000) == 0)
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        T1 <<= (T0 & 0x1f);
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    else if ((T0 & 0x1f) == 0)
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        T1 = 0;
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    else
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        T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1);
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    RETURN();
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}
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void OPPROTO op_subc_T0_T1(void)
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{
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    helper_subc_T0_T1();
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    RETURN();
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}
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void OPPROTO op_subv_T0_T1(void)
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{
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    helper_subv_T0_T1();
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    RETURN();
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}
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void OPPROTO op_trapa(void)
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{
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    env->tra = PARAM1 << 2;
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    env->exception_index = 0x160;
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    do_raise_exception();
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    RETURN();
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}
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void OPPROTO op_cmp_pl_T0(void)
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{
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    cond_t((int32_t) T0 > 0);
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    RETURN();
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}
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void OPPROTO op_cmp_pz_T0(void)
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{
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    cond_t((int32_t) T0 >= 0);
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    RETURN();
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}
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void OPPROTO op_jmp_T0(void)
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{
412 fdf9b3e8 bellard
    env->delayed_pc = T0;
413 fdf9b3e8 bellard
    RETURN();
414 fdf9b3e8 bellard
}
415 fdf9b3e8 bellard
416 fdf9b3e8 bellard
void OPPROTO op_movl_rN_rN(void)
417 fdf9b3e8 bellard
{
418 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
419 fdf9b3e8 bellard
    RETURN();
420 fdf9b3e8 bellard
}
421 fdf9b3e8 bellard
422 fdf9b3e8 bellard
void OPPROTO op_ldcl_rMplus_rN_bank(void)
423 fdf9b3e8 bellard
{
424 fdf9b3e8 bellard
    env->gregs[PARAM2] = env->gregs[PARAM1];
425 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
426 fdf9b3e8 bellard
    RETURN();
427 fdf9b3e8 bellard
}
428 fdf9b3e8 bellard
429 eda9b09b bellard
void OPPROTO op_ldc_T0_sr(void)
430 eda9b09b bellard
{
431 eda9b09b bellard
    env->sr = T0 & 0x700083f3;
432 eda9b09b bellard
    RETURN();
433 eda9b09b bellard
}
434 eda9b09b bellard
435 eda9b09b bellard
void OPPROTO op_stc_sr_T0(void)
436 eda9b09b bellard
{
437 eda9b09b bellard
    T0 = env->sr;
438 eda9b09b bellard
    RETURN();
439 eda9b09b bellard
}
440 eda9b09b bellard
441 fdf9b3e8 bellard
#define LDSTOPS(target,load,store) \
442 fdf9b3e8 bellard
void OPPROTO op_##load##_T0_##target (void) \
443 fdf9b3e8 bellard
{ env ->target = T0;   RETURN(); \
444 fdf9b3e8 bellard
} \
445 fdf9b3e8 bellard
void OPPROTO op_##store##_##target##_T0 (void) \
446 fdf9b3e8 bellard
{ T0 = env->target;   RETURN(); \
447 fdf9b3e8 bellard
} \
448 fdf9b3e8 bellard
449 fdf9b3e8 bellard
    LDSTOPS(gbr, ldc, stc)
450 fdf9b3e8 bellard
    LDSTOPS(vbr, ldc, stc)
451 fdf9b3e8 bellard
    LDSTOPS(ssr, ldc, stc)
452 fdf9b3e8 bellard
    LDSTOPS(spc, ldc, stc)
453 fdf9b3e8 bellard
    LDSTOPS(sgr, ldc, stc)
454 fdf9b3e8 bellard
    LDSTOPS(dbr, ldc, stc)
455 fdf9b3e8 bellard
    LDSTOPS(mach, lds, sts)
456 fdf9b3e8 bellard
    LDSTOPS(macl, lds, sts)
457 fdf9b3e8 bellard
    LDSTOPS(pr, lds, sts)
458 eda9b09b bellard
    LDSTOPS(fpul, lds, sts)
459 eda9b09b bellard
460 eda9b09b bellard
void OPPROTO op_lds_T0_fpscr(void)
461 eda9b09b bellard
{
462 eda9b09b bellard
    env->fpscr = T0 & 0x003fffff;
463 ea6cf6be ths
    env->fp_status.float_rounding_mode = T0 & 0x01 ?
464 ea6cf6be ths
      float_round_to_zero : float_round_nearest_even;
465 ea6cf6be ths
466 eda9b09b bellard
    RETURN();
467 eda9b09b bellard
}
468 eda9b09b bellard
469 eda9b09b bellard
void OPPROTO op_sts_fpscr_T0(void)
470 eda9b09b bellard
{
471 eda9b09b bellard
    T0 = env->fpscr & 0x003fffff;
472 eda9b09b bellard
    RETURN();
473 eda9b09b bellard
}
474 fdf9b3e8 bellard
475 fdf9b3e8 bellard
void OPPROTO op_movt_rN(void)
476 fdf9b3e8 bellard
{
477 fdf9b3e8 bellard
    env->gregs[PARAM1] = env->sr & SR_T;
478 fdf9b3e8 bellard
    RETURN();
479 fdf9b3e8 bellard
}
480 fdf9b3e8 bellard
481 fdf9b3e8 bellard
void OPPROTO op_rotcl_Rn(void)
482 fdf9b3e8 bellard
{
483 fdf9b3e8 bellard
    helper_rotcl(&env->gregs[PARAM1]);
484 fdf9b3e8 bellard
    RETURN();
485 fdf9b3e8 bellard
}
486 fdf9b3e8 bellard
487 fdf9b3e8 bellard
void OPPROTO op_rotcr_Rn(void)
488 fdf9b3e8 bellard
{
489 fdf9b3e8 bellard
    helper_rotcr(&env->gregs[PARAM1]);
490 fdf9b3e8 bellard
    RETURN();
491 fdf9b3e8 bellard
}
492 fdf9b3e8 bellard
493 fdf9b3e8 bellard
void OPPROTO op_rotl_Rn(void)
494 fdf9b3e8 bellard
{
495 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
496 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
497 fdf9b3e8 bellard
    RETURN();
498 fdf9b3e8 bellard
}
499 fdf9b3e8 bellard
500 fdf9b3e8 bellard
void OPPROTO op_rotr_Rn(void)
501 fdf9b3e8 bellard
{
502 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
503 fdf9b3e8 bellard
    env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
504 fdf9b3e8 bellard
        ((env->sr & SR_T) ? 0x80000000 : 0);
505 fdf9b3e8 bellard
    RETURN();
506 fdf9b3e8 bellard
}
507 fdf9b3e8 bellard
508 fdf9b3e8 bellard
void OPPROTO op_shal_Rn(void)
509 fdf9b3e8 bellard
{
510 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 0x80000000);
511 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 1;
512 fdf9b3e8 bellard
    RETURN();
513 fdf9b3e8 bellard
}
514 fdf9b3e8 bellard
515 fdf9b3e8 bellard
void OPPROTO op_shar_Rn(void)
516 fdf9b3e8 bellard
{
517 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
518 24988dc2 aurel32
    *(int32_t *)&env->gregs[PARAM1] >>= 1;
519 fdf9b3e8 bellard
    RETURN();
520 fdf9b3e8 bellard
}
521 fdf9b3e8 bellard
522 fdf9b3e8 bellard
void OPPROTO op_shlr_Rn(void)
523 fdf9b3e8 bellard
{
524 fdf9b3e8 bellard
    cond_t(env->gregs[PARAM1] & 1);
525 a5d251bd ths
    env->gregs[PARAM1] >>= 1;
526 fdf9b3e8 bellard
    RETURN();
527 fdf9b3e8 bellard
}
528 fdf9b3e8 bellard
529 fdf9b3e8 bellard
void OPPROTO op_shll2_Rn(void)
530 fdf9b3e8 bellard
{
531 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 2;
532 fdf9b3e8 bellard
    RETURN();
533 fdf9b3e8 bellard
}
534 fdf9b3e8 bellard
535 fdf9b3e8 bellard
void OPPROTO op_shll8_Rn(void)
536 fdf9b3e8 bellard
{
537 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 8;
538 fdf9b3e8 bellard
    RETURN();
539 fdf9b3e8 bellard
}
540 fdf9b3e8 bellard
541 fdf9b3e8 bellard
void OPPROTO op_shll16_Rn(void)
542 fdf9b3e8 bellard
{
543 fdf9b3e8 bellard
    env->gregs[PARAM1] <<= 16;
544 fdf9b3e8 bellard
    RETURN();
545 fdf9b3e8 bellard
}
546 fdf9b3e8 bellard
547 fdf9b3e8 bellard
void OPPROTO op_shlr2_Rn(void)
548 fdf9b3e8 bellard
{
549 a5d251bd ths
    env->gregs[PARAM1] >>= 2;
550 fdf9b3e8 bellard
    RETURN();
551 fdf9b3e8 bellard
}
552 fdf9b3e8 bellard
553 fdf9b3e8 bellard
void OPPROTO op_shlr8_Rn(void)
554 fdf9b3e8 bellard
{
555 a5d251bd ths
    env->gregs[PARAM1] >>= 8;
556 fdf9b3e8 bellard
    RETURN();
557 fdf9b3e8 bellard
}
558 fdf9b3e8 bellard
559 fdf9b3e8 bellard
void OPPROTO op_shlr16_Rn(void)
560 fdf9b3e8 bellard
{
561 a5d251bd ths
    env->gregs[PARAM1] >>= 16;
562 fdf9b3e8 bellard
    RETURN();
563 fdf9b3e8 bellard
}
564 fdf9b3e8 bellard
565 fdf9b3e8 bellard
void OPPROTO op_movl_T0_rN(void)
566 fdf9b3e8 bellard
{
567 fdf9b3e8 bellard
    env->gregs[PARAM1] = T0;
568 fdf9b3e8 bellard
    RETURN();
569 fdf9b3e8 bellard
}
570 fdf9b3e8 bellard
571 fdf9b3e8 bellard
void OPPROTO op_movl_T1_rN(void)
572 fdf9b3e8 bellard
{
573 fdf9b3e8 bellard
    env->gregs[PARAM1] = T1;
574 fdf9b3e8 bellard
    RETURN();
575 fdf9b3e8 bellard
}
576 fdf9b3e8 bellard
577 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T0(void)
578 fdf9b3e8 bellard
{
579 fdf9b3e8 bellard
    T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
580 fdf9b3e8 bellard
    RETURN();
581 fdf9b3e8 bellard
}
582 fdf9b3e8 bellard
583 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T0(void)
584 fdf9b3e8 bellard
{
585 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xff;
586 fdf9b3e8 bellard
    RETURN();
587 fdf9b3e8 bellard
}
588 fdf9b3e8 bellard
589 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T0(void)
590 fdf9b3e8 bellard
{
591 fdf9b3e8 bellard
    T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
592 fdf9b3e8 bellard
    RETURN();
593 fdf9b3e8 bellard
}
594 fdf9b3e8 bellard
595 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T0(void)
596 fdf9b3e8 bellard
{
597 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1] & 0xffff;
598 fdf9b3e8 bellard
    RETURN();
599 fdf9b3e8 bellard
}
600 fdf9b3e8 bellard
601 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T0(void)
602 fdf9b3e8 bellard
{
603 fdf9b3e8 bellard
    T0 = env->gregs[PARAM1];
604 fdf9b3e8 bellard
    RETURN();
605 fdf9b3e8 bellard
}
606 fdf9b3e8 bellard
607 fdf9b3e8 bellard
void OPPROTO op_movb_rN_T1(void)
608 fdf9b3e8 bellard
{
609 fdf9b3e8 bellard
    T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
610 fdf9b3e8 bellard
    RETURN();
611 fdf9b3e8 bellard
}
612 fdf9b3e8 bellard
613 fdf9b3e8 bellard
void OPPROTO op_movub_rN_T1(void)
614 fdf9b3e8 bellard
{
615 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xff;
616 fdf9b3e8 bellard
    RETURN();
617 fdf9b3e8 bellard
}
618 fdf9b3e8 bellard
619 fdf9b3e8 bellard
void OPPROTO op_movw_rN_T1(void)
620 fdf9b3e8 bellard
{
621 fdf9b3e8 bellard
    T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
622 fdf9b3e8 bellard
    RETURN();
623 fdf9b3e8 bellard
}
624 fdf9b3e8 bellard
625 fdf9b3e8 bellard
void OPPROTO op_movuw_rN_T1(void)
626 fdf9b3e8 bellard
{
627 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1] & 0xffff;
628 fdf9b3e8 bellard
    RETURN();
629 fdf9b3e8 bellard
}
630 fdf9b3e8 bellard
631 fdf9b3e8 bellard
void OPPROTO op_movl_rN_T1(void)
632 fdf9b3e8 bellard
{
633 fdf9b3e8 bellard
    T1 = env->gregs[PARAM1];
634 fdf9b3e8 bellard
    RETURN();
635 fdf9b3e8 bellard
}
636 fdf9b3e8 bellard
637 fdf9b3e8 bellard
void OPPROTO op_movl_imm_rN(void)
638 fdf9b3e8 bellard
{
639 fdf9b3e8 bellard
    env->gregs[PARAM2] = PARAM1;
640 fdf9b3e8 bellard
    RETURN();
641 fdf9b3e8 bellard
}
642 fdf9b3e8 bellard
643 eda9b09b bellard
void OPPROTO op_fmov_frN_FT0(void)
644 eda9b09b bellard
{
645 e04ea3dc ths
    FT0 = env->fregs[PARAM1];
646 eda9b09b bellard
    RETURN();
647 eda9b09b bellard
}
648 eda9b09b bellard
649 eda9b09b bellard
void OPPROTO op_fmov_drN_DT0(void)
650 eda9b09b bellard
{
651 e04ea3dc ths
    CPU_DoubleU d;
652 e04ea3dc ths
653 e04ea3dc ths
    d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
654 e04ea3dc ths
    d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
655 e04ea3dc ths
    DT0 = d.d;
656 eda9b09b bellard
    RETURN();
657 eda9b09b bellard
}
658 eda9b09b bellard
659 ea6cf6be ths
void OPPROTO op_fmov_frN_FT1(void)
660 ea6cf6be ths
{
661 e04ea3dc ths
    FT1 = env->fregs[PARAM1];
662 ea6cf6be ths
    RETURN();
663 ea6cf6be ths
}
664 ea6cf6be ths
665 ea6cf6be ths
void OPPROTO op_fmov_drN_DT1(void)
666 ea6cf6be ths
{
667 e04ea3dc ths
    CPU_DoubleU d;
668 e04ea3dc ths
669 e04ea3dc ths
    d.l.upper = *(uint32_t *)&env->fregs[PARAM1];
670 e04ea3dc ths
    d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
671 e04ea3dc ths
    DT1 = d.d;
672 ea6cf6be ths
    RETURN();
673 ea6cf6be ths
}
674 ea6cf6be ths
675 eda9b09b bellard
void OPPROTO op_fmov_FT0_frN(void)
676 eda9b09b bellard
{
677 e04ea3dc ths
    env->fregs[PARAM1] = FT0;
678 eda9b09b bellard
    RETURN();
679 eda9b09b bellard
}
680 eda9b09b bellard
681 eda9b09b bellard
void OPPROTO op_fmov_DT0_drN(void)
682 eda9b09b bellard
{
683 e04ea3dc ths
    CPU_DoubleU d;
684 e04ea3dc ths
685 e04ea3dc ths
    d.d = DT0;
686 e04ea3dc ths
    *(uint32_t *)&env->fregs[PARAM1] = d.l.upper;
687 e04ea3dc ths
    *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
688 eda9b09b bellard
    RETURN();
689 eda9b09b bellard
}
690 eda9b09b bellard
691 ea6cf6be ths
void OPPROTO op_fadd_FT(void)
692 ea6cf6be ths
{
693 ea6cf6be ths
    FT0 = float32_add(FT0, FT1, &env->fp_status);
694 ea6cf6be ths
    RETURN();
695 ea6cf6be ths
}
696 ea6cf6be ths
697 ea6cf6be ths
void OPPROTO op_fadd_DT(void)
698 ea6cf6be ths
{
699 ea6cf6be ths
    DT0 = float64_add(DT0, DT1, &env->fp_status);
700 ea6cf6be ths
    RETURN();
701 ea6cf6be ths
}
702 ea6cf6be ths
703 ea6cf6be ths
void OPPROTO op_fsub_FT(void)
704 ea6cf6be ths
{
705 ea6cf6be ths
    FT0 = float32_sub(FT0, FT1, &env->fp_status);
706 ea6cf6be ths
    RETURN();
707 ea6cf6be ths
}
708 ea6cf6be ths
709 ea6cf6be ths
void OPPROTO op_fsub_DT(void)
710 ea6cf6be ths
{
711 ea6cf6be ths
    DT0 = float64_sub(DT0, DT1, &env->fp_status);
712 ea6cf6be ths
    RETURN();
713 ea6cf6be ths
}
714 ea6cf6be ths
715 ea6cf6be ths
void OPPROTO op_fmul_FT(void)
716 ea6cf6be ths
{
717 ea6cf6be ths
    FT0 = float32_mul(FT0, FT1, &env->fp_status);
718 ea6cf6be ths
    RETURN();
719 ea6cf6be ths
}
720 ea6cf6be ths
721 ea6cf6be ths
void OPPROTO op_fmul_DT(void)
722 ea6cf6be ths
{
723 ea6cf6be ths
    DT0 = float64_mul(DT0, DT1, &env->fp_status);
724 ea6cf6be ths
    RETURN();
725 ea6cf6be ths
}
726 ea6cf6be ths
727 ea6cf6be ths
void OPPROTO op_fdiv_FT(void)
728 ea6cf6be ths
{
729 ea6cf6be ths
    FT0 = float32_div(FT0, FT1, &env->fp_status);
730 ea6cf6be ths
    RETURN();
731 ea6cf6be ths
}
732 ea6cf6be ths
733 ea6cf6be ths
void OPPROTO op_fdiv_DT(void)
734 ea6cf6be ths
{
735 ea6cf6be ths
    DT0 = float64_div(DT0, DT1, &env->fp_status);
736 ea6cf6be ths
    RETURN();
737 ea6cf6be ths
}
738 ea6cf6be ths
739 24988dc2 aurel32
void OPPROTO op_fcmp_eq_FT(void)
740 24988dc2 aurel32
{
741 24988dc2 aurel32
    cond_t(float32_compare(FT0, FT1, &env->fp_status) == 0);
742 24988dc2 aurel32
    RETURN();
743 24988dc2 aurel32
}
744 24988dc2 aurel32
745 24988dc2 aurel32
void OPPROTO op_fcmp_eq_DT(void)
746 24988dc2 aurel32
{
747 24988dc2 aurel32
    cond_t(float64_compare(DT0, DT1, &env->fp_status) == 0);
748 24988dc2 aurel32
    RETURN();
749 24988dc2 aurel32
}
750 24988dc2 aurel32
751 24988dc2 aurel32
void OPPROTO op_fcmp_gt_FT(void)
752 24988dc2 aurel32
{
753 24988dc2 aurel32
    cond_t(float32_compare(FT0, FT1, &env->fp_status) == 1);
754 24988dc2 aurel32
    RETURN();
755 24988dc2 aurel32
}
756 24988dc2 aurel32
757 24988dc2 aurel32
void OPPROTO op_fcmp_gt_DT(void)
758 24988dc2 aurel32
{
759 24988dc2 aurel32
    cond_t(float64_compare(DT0, DT1, &env->fp_status) == 1);
760 24988dc2 aurel32
    RETURN();
761 24988dc2 aurel32
}
762 24988dc2 aurel32
763 ea6cf6be ths
void OPPROTO op_float_FT(void)
764 ea6cf6be ths
{
765 ea6cf6be ths
    FT0 = int32_to_float32(env->fpul, &env->fp_status);
766 ea6cf6be ths
    RETURN();
767 ea6cf6be ths
}
768 ea6cf6be ths
769 ea6cf6be ths
void OPPROTO op_float_DT(void)
770 ea6cf6be ths
{
771 ea6cf6be ths
    DT0 = int32_to_float64(env->fpul, &env->fp_status);
772 ea6cf6be ths
    RETURN();
773 ea6cf6be ths
}
774 ea6cf6be ths
775 ea6cf6be ths
void OPPROTO op_ftrc_FT(void)
776 ea6cf6be ths
{
777 ea6cf6be ths
    env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status);
778 ea6cf6be ths
    RETURN();
779 ea6cf6be ths
}
780 ea6cf6be ths
781 ea6cf6be ths
void OPPROTO op_ftrc_DT(void)
782 ea6cf6be ths
{
783 ea6cf6be ths
    env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status);
784 ea6cf6be ths
    RETURN();
785 ea6cf6be ths
}
786 ea6cf6be ths
787 24988dc2 aurel32
void OPPROTO op_fneg_frN(void)
788 24988dc2 aurel32
{
789 24988dc2 aurel32
    env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]);
790 24988dc2 aurel32
    RETURN();
791 24988dc2 aurel32
}
792 24988dc2 aurel32
793 24988dc2 aurel32
void OPPROTO op_fabs_FT(void)
794 24988dc2 aurel32
{
795 24988dc2 aurel32
    FT0 = float32_abs(FT0);
796 24988dc2 aurel32
    RETURN();
797 24988dc2 aurel32
}
798 24988dc2 aurel32
799 24988dc2 aurel32
void OPPROTO op_fabs_DT(void)
800 24988dc2 aurel32
{
801 24988dc2 aurel32
    DT0 = float64_abs(DT0);
802 24988dc2 aurel32
    RETURN();
803 24988dc2 aurel32
}
804 24988dc2 aurel32
805 24988dc2 aurel32
void OPPROTO op_fcnvsd_FT_DT(void)
806 24988dc2 aurel32
{
807 24988dc2 aurel32
    DT0 = float32_to_float64(FT0, &env->fp_status);
808 24988dc2 aurel32
    RETURN();
809 24988dc2 aurel32
}
810 24988dc2 aurel32
811 24988dc2 aurel32
void OPPROTO op_fcnvds_DT_FT(void)
812 24988dc2 aurel32
{
813 24988dc2 aurel32
    FT0 = float64_to_float32(DT0, &env->fp_status);
814 24988dc2 aurel32
    RETURN();
815 24988dc2 aurel32
}
816 24988dc2 aurel32
817 24988dc2 aurel32
void OPPROTO op_fsqrt_FT(void)
818 24988dc2 aurel32
{
819 24988dc2 aurel32
    FT0 = float32_sqrt(FT0, &env->fp_status);
820 24988dc2 aurel32
    RETURN();
821 24988dc2 aurel32
}
822 24988dc2 aurel32
823 24988dc2 aurel32
void OPPROTO op_fsqrt_DT(void)
824 24988dc2 aurel32
{
825 24988dc2 aurel32
    DT0 = float64_sqrt(DT0, &env->fp_status);
826 24988dc2 aurel32
    RETURN();
827 24988dc2 aurel32
}
828 24988dc2 aurel32
829 ea6cf6be ths
void OPPROTO op_fmov_T0_frN(void)
830 ea6cf6be ths
{
831 24988dc2 aurel32
    *(uint32_t *)&env->fregs[PARAM1] = T0;
832 ea6cf6be ths
    RETURN();
833 ea6cf6be ths
}
834 ea6cf6be ths
835 fdf9b3e8 bellard
void OPPROTO op_dec1_rN(void)
836 fdf9b3e8 bellard
{
837 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 1;
838 fdf9b3e8 bellard
    RETURN();
839 fdf9b3e8 bellard
}
840 fdf9b3e8 bellard
841 fdf9b3e8 bellard
void OPPROTO op_dec2_rN(void)
842 fdf9b3e8 bellard
{
843 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 2;
844 fdf9b3e8 bellard
    RETURN();
845 fdf9b3e8 bellard
}
846 fdf9b3e8 bellard
847 fdf9b3e8 bellard
void OPPROTO op_dec4_rN(void)
848 fdf9b3e8 bellard
{
849 fdf9b3e8 bellard
    env->gregs[PARAM1] -= 4;
850 fdf9b3e8 bellard
    RETURN();
851 fdf9b3e8 bellard
}
852 fdf9b3e8 bellard
853 eda9b09b bellard
void OPPROTO op_dec8_rN(void)
854 eda9b09b bellard
{
855 0a618140 ths
    env->gregs[PARAM1] -= 8;
856 eda9b09b bellard
    RETURN();
857 eda9b09b bellard
}
858 eda9b09b bellard
859 fdf9b3e8 bellard
void OPPROTO op_inc1_rN(void)
860 fdf9b3e8 bellard
{
861 fdf9b3e8 bellard
    env->gregs[PARAM1] += 1;
862 fdf9b3e8 bellard
    RETURN();
863 fdf9b3e8 bellard
}
864 fdf9b3e8 bellard
865 fdf9b3e8 bellard
void OPPROTO op_inc2_rN(void)
866 fdf9b3e8 bellard
{
867 fdf9b3e8 bellard
    env->gregs[PARAM1] += 2;
868 fdf9b3e8 bellard
    RETURN();
869 fdf9b3e8 bellard
}
870 fdf9b3e8 bellard
871 fdf9b3e8 bellard
void OPPROTO op_inc4_rN(void)
872 fdf9b3e8 bellard
{
873 fdf9b3e8 bellard
    env->gregs[PARAM1] += 4;
874 fdf9b3e8 bellard
    RETURN();
875 fdf9b3e8 bellard
}
876 fdf9b3e8 bellard
877 eda9b09b bellard
void OPPROTO op_inc8_rN(void)
878 eda9b09b bellard
{
879 0a618140 ths
    env->gregs[PARAM1] += 8;
880 eda9b09b bellard
    RETURN();
881 eda9b09b bellard
}
882 eda9b09b bellard
883 fdf9b3e8 bellard
void OPPROTO op_add_T0_rN(void)
884 fdf9b3e8 bellard
{
885 fdf9b3e8 bellard
    env->gregs[PARAM1] += T0;
886 fdf9b3e8 bellard
    RETURN();
887 fdf9b3e8 bellard
}
888 fdf9b3e8 bellard
889 fdf9b3e8 bellard
void OPPROTO op_sub_T0_rN(void)
890 fdf9b3e8 bellard
{
891 fdf9b3e8 bellard
    env->gregs[PARAM1] -= T0;
892 fdf9b3e8 bellard
    RETURN();
893 fdf9b3e8 bellard
}
894 fdf9b3e8 bellard
895 fdf9b3e8 bellard
void OPPROTO op_and_T0_rN(void)
896 fdf9b3e8 bellard
{
897 fdf9b3e8 bellard
    env->gregs[PARAM1] &= T0;
898 fdf9b3e8 bellard
    RETURN();
899 fdf9b3e8 bellard
}
900 fdf9b3e8 bellard
901 fdf9b3e8 bellard
void OPPROTO op_or_T0_rN(void)
902 fdf9b3e8 bellard
{
903 fdf9b3e8 bellard
    env->gregs[PARAM1] |= T0;
904 fdf9b3e8 bellard
    RETURN();
905 fdf9b3e8 bellard
}
906 fdf9b3e8 bellard
907 fdf9b3e8 bellard
void OPPROTO op_xor_T0_rN(void)
908 fdf9b3e8 bellard
{
909 fdf9b3e8 bellard
    env->gregs[PARAM1] ^= T0;
910 fdf9b3e8 bellard
    RETURN();
911 fdf9b3e8 bellard
}
912 fdf9b3e8 bellard
913 fdf9b3e8 bellard
void OPPROTO op_add_rN_T0(void)
914 fdf9b3e8 bellard
{
915 fdf9b3e8 bellard
    T0 += env->gregs[PARAM1];
916 fdf9b3e8 bellard
    RETURN();
917 fdf9b3e8 bellard
}
918 fdf9b3e8 bellard
919 fdf9b3e8 bellard
void OPPROTO op_add_rN_T1(void)
920 fdf9b3e8 bellard
{
921 fdf9b3e8 bellard
    T1 += env->gregs[PARAM1];
922 fdf9b3e8 bellard
    RETURN();
923 fdf9b3e8 bellard
}
924 fdf9b3e8 bellard
925 fdf9b3e8 bellard
void OPPROTO op_add_imm_rN(void)
926 fdf9b3e8 bellard
{
927 fdf9b3e8 bellard
    env->gregs[PARAM2] += PARAM1;
928 fdf9b3e8 bellard
    RETURN();
929 fdf9b3e8 bellard
}
930 fdf9b3e8 bellard
931 fdf9b3e8 bellard
void OPPROTO op_and_imm_rN(void)
932 fdf9b3e8 bellard
{
933 fdf9b3e8 bellard
    env->gregs[PARAM2] &= PARAM1;
934 fdf9b3e8 bellard
    RETURN();
935 fdf9b3e8 bellard
}
936 fdf9b3e8 bellard
937 fdf9b3e8 bellard
void OPPROTO op_or_imm_rN(void)
938 fdf9b3e8 bellard
{
939 fdf9b3e8 bellard
    env->gregs[PARAM2] |= PARAM1;
940 fdf9b3e8 bellard
    RETURN();
941 fdf9b3e8 bellard
}
942 fdf9b3e8 bellard
943 fdf9b3e8 bellard
void OPPROTO op_xor_imm_rN(void)
944 fdf9b3e8 bellard
{
945 fdf9b3e8 bellard
    env->gregs[PARAM2] ^= PARAM1;
946 fdf9b3e8 bellard
    RETURN();
947 fdf9b3e8 bellard
}
948 fdf9b3e8 bellard
949 fdf9b3e8 bellard
void OPPROTO op_dt_rN(void)
950 fdf9b3e8 bellard
{
951 fdf9b3e8 bellard
    cond_t((--env->gregs[PARAM1]) == 0);
952 fdf9b3e8 bellard
    RETURN();
953 fdf9b3e8 bellard
}
954 fdf9b3e8 bellard
955 fdf9b3e8 bellard
void OPPROTO op_tst_imm_rN(void)
956 fdf9b3e8 bellard
{
957 fdf9b3e8 bellard
    cond_t((env->gregs[PARAM2] & PARAM1) == 0);
958 fdf9b3e8 bellard
    RETURN();
959 fdf9b3e8 bellard
}
960 fdf9b3e8 bellard
961 fdf9b3e8 bellard
void OPPROTO op_movl_T0_T1(void)
962 fdf9b3e8 bellard
{
963 fdf9b3e8 bellard
    T1 = T0;
964 fdf9b3e8 bellard
    RETURN();
965 fdf9b3e8 bellard
}
966 fdf9b3e8 bellard
967 eda9b09b bellard
void OPPROTO op_movl_fpul_FT0(void)
968 eda9b09b bellard
{
969 eda9b09b bellard
    FT0 = *(float32 *)&env->fpul;
970 eda9b09b bellard
    RETURN();
971 eda9b09b bellard
}
972 eda9b09b bellard
973 eda9b09b bellard
void OPPROTO op_movl_FT0_fpul(void)
974 eda9b09b bellard
{
975 eda9b09b bellard
    *(float32 *)&env->fpul = FT0;
976 eda9b09b bellard
    RETURN();
977 eda9b09b bellard
}
978 eda9b09b bellard
979 fdf9b3e8 bellard
void OPPROTO op_movl_imm_PC(void)
980 fdf9b3e8 bellard
{
981 fdf9b3e8 bellard
    env->pc = PARAM1;
982 fdf9b3e8 bellard
    RETURN();
983 fdf9b3e8 bellard
}
984 fdf9b3e8 bellard
985 fdf9b3e8 bellard
void OPPROTO op_jT(void)
986 fdf9b3e8 bellard
{
987 fdf9b3e8 bellard
    if (env->sr & SR_T)
988 fdf9b3e8 bellard
        GOTO_LABEL_PARAM(1);
989 fdf9b3e8 bellard
    RETURN();
990 fdf9b3e8 bellard
}
991 fdf9b3e8 bellard
992 9c2a9ea1 pbrook
void OPPROTO op_jdelayed(void)
993 fdf9b3e8 bellard
{
994 823029f9 ths
    if (env->flags & DELAY_SLOT_TRUE) {
995 823029f9 ths
        env->flags &= ~DELAY_SLOT_TRUE;
996 823029f9 ths
        GOTO_LABEL_PARAM(1);
997 823029f9 ths
    }
998 fdf9b3e8 bellard
    RETURN();
999 fdf9b3e8 bellard
}
1000 fdf9b3e8 bellard
1001 fdf9b3e8 bellard
void OPPROTO op_movl_delayed_pc_PC(void)
1002 fdf9b3e8 bellard
{
1003 fdf9b3e8 bellard
    env->pc = env->delayed_pc;
1004 fdf9b3e8 bellard
    RETURN();
1005 fdf9b3e8 bellard
}
1006 fdf9b3e8 bellard
1007 fdf9b3e8 bellard
void OPPROTO op_addl_GBR_T0(void)
1008 fdf9b3e8 bellard
{
1009 fdf9b3e8 bellard
    T0 += env->gbr;
1010 fdf9b3e8 bellard
    RETURN();
1011 fdf9b3e8 bellard
}
1012 fdf9b3e8 bellard
1013 fdf9b3e8 bellard
void OPPROTO op_and_imm_T0(void)
1014 fdf9b3e8 bellard
{
1015 fdf9b3e8 bellard
    T0 &= PARAM1;
1016 fdf9b3e8 bellard
    RETURN();
1017 fdf9b3e8 bellard
}
1018 fdf9b3e8 bellard
1019 fdf9b3e8 bellard
void OPPROTO op_or_imm_T0(void)
1020 fdf9b3e8 bellard
{
1021 fdf9b3e8 bellard
    T0 |= PARAM1;
1022 fdf9b3e8 bellard
    RETURN();
1023 fdf9b3e8 bellard
}
1024 fdf9b3e8 bellard
1025 fdf9b3e8 bellard
void OPPROTO op_xor_imm_T0(void)
1026 fdf9b3e8 bellard
{
1027 fdf9b3e8 bellard
    T0 ^= PARAM1;
1028 fdf9b3e8 bellard
    RETURN();
1029 fdf9b3e8 bellard
}
1030 fdf9b3e8 bellard
1031 fdf9b3e8 bellard
void OPPROTO op_tst_imm_T0(void)
1032 fdf9b3e8 bellard
{
1033 fdf9b3e8 bellard
    cond_t((T0 & PARAM1) == 0);
1034 fdf9b3e8 bellard
    RETURN();
1035 fdf9b3e8 bellard
}
1036 fdf9b3e8 bellard
1037 fdf9b3e8 bellard
void OPPROTO op_raise_illegal_instruction(void)
1038 fdf9b3e8 bellard
{
1039 fdf9b3e8 bellard
    env->exception_index = 0x180;
1040 fdf9b3e8 bellard
    do_raise_exception();
1041 fdf9b3e8 bellard
    RETURN();
1042 fdf9b3e8 bellard
}
1043 fdf9b3e8 bellard
1044 fdf9b3e8 bellard
void OPPROTO op_raise_slot_illegal_instruction(void)
1045 fdf9b3e8 bellard
{
1046 fdf9b3e8 bellard
    env->exception_index = 0x1a0;
1047 fdf9b3e8 bellard
    do_raise_exception();
1048 fdf9b3e8 bellard
    RETURN();
1049 fdf9b3e8 bellard
}
1050 fdf9b3e8 bellard
1051 fdf9b3e8 bellard
void OPPROTO op_debug(void)
1052 fdf9b3e8 bellard
{
1053 fdf9b3e8 bellard
    env->exception_index = EXCP_DEBUG;
1054 fdf9b3e8 bellard
    cpu_loop_exit();
1055 fdf9b3e8 bellard
}
1056 fdf9b3e8 bellard
1057 833ed386 aurel32
void OPPROTO op_sleep(void)
1058 833ed386 aurel32
{
1059 833ed386 aurel32
    env->halted = 1;
1060 833ed386 aurel32
    env->exception_index = EXCP_HLT;
1061 833ed386 aurel32
    cpu_loop_exit();
1062 833ed386 aurel32
}
1063 833ed386 aurel32
1064 fdf9b3e8 bellard
/* Load and store */
1065 fdf9b3e8 bellard
#define MEMSUFFIX _raw
1066 fdf9b3e8 bellard
#include "op_mem.c"
1067 fdf9b3e8 bellard
#undef MEMSUFFIX
1068 fdf9b3e8 bellard
#if !defined(CONFIG_USER_ONLY)
1069 fdf9b3e8 bellard
#define MEMSUFFIX _user
1070 fdf9b3e8 bellard
#include "op_mem.c"
1071 fdf9b3e8 bellard
#undef MEMSUFFIX
1072 fdf9b3e8 bellard
1073 fdf9b3e8 bellard
#define MEMSUFFIX _kernel
1074 fdf9b3e8 bellard
#include "op_mem.c"
1075 fdf9b3e8 bellard
#undef MEMSUFFIX
1076 fdf9b3e8 bellard
#endif