History | View | Annotate | Download (23.3 kB)
hw/s*: pass owner to memory_region_init* functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
memory: add owner argument to initialization functions
xilinx_spips: lqspi: Push more data to tx-fifo
Do 16 words per fifo flush. Increases performance and decreasesdebug verbosity. This data depth has no real hardware analogue,so just go with something that has reasonable performance.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
xilinx_spips: lqspi: Fix byte/misaligned access
The LQSPI bus attachment supports byte/halfword and misalignedaccesses. Fixed. Refactored the LQSPI cache to be byte-wiseinstead of word wise accordingly.
xilinx_spips: lqspi: Dont touch config register
The LQSPI mode is supposed to work via the automatic CS mode featurerather than manipulate CS lines itself. Now that auto CS is implementedremove LQSPIs CS mode override logic. There is still a need tomanipulate the U_PAGE bit in LQSPI config register to implement...
xilinx_spips: Fix CTRL register RW bits
The CTRL register was RAZ/WI on some of the RW bits. Even though thefunction behind these bits is invalid in QEMU, they should still beguest accessible. Fix.
xilinx_spips: Fix striping behaviour
The QSPI controller was using byte-wide stripes when striping acrossthe two flashes in dual parallel mode. The real hardware however usesindividual bit striping. QEMU misbehaves in the (corner) case wheredata is written/read in dual-parallel mode and read/written back in...
xilinx_spips: Debug msgs for Snoop state
This is worth keeping track of when debugging the device model.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>...
xilinx_spips: Multiple debug verbosity levels
The debug printfs on every SPI operation is extremely verbose. Adda second level of debug for this.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
xilinx_spips: Fix QSPI FIFO size
QSPI has a bigger FIFO than the regular SPI controller. Differentiatebetween the two with correct FIFO sizes for each.
This is the first piece of class data for SPIPS, so this patch seesthe creation of the XilinxSPIPSClass definition and assoicated QOM...
xilinx_spips: Trash LQ page cache on mode change
Invalidate the LQSPI cached page when transitioning into LQSPI mode.Otherwise there is a possibility that the controller will return staledata to the guest when transitioning back to LQ_MODE after a page...
xilinx_spips: Add automatic start support
SPI has a mode where it automatically starts based on tx fifooccupancy. Implemented.
xilinx_spips: Implement automatic CS
Implement the automatic CS control feature. If the MANUAL_CS bit iscleared then the chip select stay de-asserted as long as the tx FIFOis empty.
xilinx_spips: seperate SPI and QSPI as two classes
Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS.Only QSPI has the LQSPI functionality, so move all that to the child class.
xilinx_spips: Make interrupts clear on read
By default these interrupts are clear on read.
xilinx_spips: Inhibit interrupts in LQSPI mode
The real hardware does not produce interrupts in LQSPI mode. Inhibitgeneration of interrupts when the LQ_MODE bit is set.
xilinx_spips: Add verbose LQSPI debug output
You really need this is you want to track a guest banging on LQSPI.
hw: move SSI controllers to hw/ssi/, configure via default-configs/