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root / hw / char @ f41152bd

Name Size
Makefile.objs 1.1 kB
cadence_uart.c 14.4 kB
debugcon.c 4.2 kB
digic-uart.c 4.7 kB
escc.c 25.9 kB
etraxfs_ser.c 6.5 kB
exynos4210_uart.c 19.3 kB
grlib_apbuart.c 7.8 kB
imx_serial.c 12.9 kB
ipack.c 2.9 kB
ipack.h 2.4 kB
ipoctal232.c 16.1 kB
lm32_juart.c 3.6 kB
lm32_uart.c 6.7 kB
mcf_uart.c 7.1 kB
milkymist-uart.c 5.9 kB
omap_uart.c 5.1 kB
parallel.c 18.2 kB
pl011.c 8.2 kB
sclpconsole-lm.c 10.5 kB
sclpconsole.c 8.1 kB
serial-isa.c 4.2 kB
serial-pci.c 8.5 kB
serial.c 23.5 kB
sh_serial.c 10.4 kB
spapr_vty.c 6.4 kB
tpci200.c 18.8 kB
virtio-console.c 5.5 kB
virtio-serial-bus.c 28.8 kB
xen_console.c 8.3 kB
xilinx_uartlite.c 5.9 kB

Latest revisions

# Date Author Comment
02d3bf7f 02/04/2014 08:34 pm Michael Walle

lm32_uart/lm32_juart: use qemu_chr_fe_write_all()

qemu_chr_fe_write() may return EAGAIN. Therefore, use
qemu_chr_fe_write_all().

Signed-off-by: Michael Walle <>
Reviewed-by: Peter Maydell <>
b2c623a3 02/04/2014 08:34 pm Antony Pavlov

milkymist-uart: use qemu_chr_fe_write_all() instead of qemu_chr_fe_write()

qemu_chr_fe_write() is capable of returning 0
to indicate EAGAIN (and friends) and we don't
handle this.

Just change it to qemu_chr_fe_write_all() to fix.

Reported-by: Peter Crosthwaite <>...
666eb032 01/09/2014 09:24 pm Anthony Liguori

Merge remote-tracking branch 'mjt/trivial-patches' into staging

  • mjt/trivial-patches:
    acpi unit-test: Remove temporary disk after test
    mainstone: Fix duplicate array values for key 'space'
    pxa27x: Add 'const' attribute to keyboard maps
    pxa27x: Reduce size of keyboard matrix mapping...
676f4c09 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Simplify status generation

The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state....
11a239a5 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Define Missing SR/ISR fields

Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.

Signed-off-by: Peter Crosthwaite <>...
2152e08a 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Remove TX timer & add TX FIFO state

This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting...
d0ac820f 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Fix can_receive logic

The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:...
86baecc3 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Use the TX fifo for transmission

Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.

Signed-off-by: Peter Crosthwaite <>
Message-id: ...
1e5d8cac 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Delete redundant rx rst logic

uart_rx_reset() called immediately above already does this. Remove.

Signed-off-by: Peter Crosthwaite <>
Message-id: ...
38acd64b 01/08/2014 09:07 pm Peter Crosthwaite

char/cadence_uart: Implement Tx flow control

If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).

Signed-off-by: Peter Crosthwaite <>...

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