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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 47103572 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "fdc.h" |
28 | 87ecb68b | pbrook | #include "net.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "pci.h" |
32 | 8ca8c7bc | Andreas Färber | #include "pci_host.h" |
33 | 87ecb68b | pbrook | #include "ppc.h" |
34 | 87ecb68b | pbrook | #include "boards.h" |
35 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
36 | ec82026c | Gerd Hoffmann | #include "ide.h" |
37 | ca20cf32 | Blue Swirl | #include "loader.h" |
38 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
41 | 9fddaa0c | bellard | |
42 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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43 | a541f297 | bellard | //#define DEBUG_PPC_IO
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44 | 9a64fbe4 | bellard | |
45 | fe33cc71 | j_mayer | /* SMP is not enabled, for now */
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46 | fe33cc71 | j_mayer | #define MAX_CPUS 1 |
47 | fe33cc71 | j_mayer | |
48 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
49 | e4bcb14c | ths | |
50 | bba831e8 | Paul Brook | #define BIOS_SIZE (1024 * 1024) |
51 | b6b8bd18 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
52 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
53 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
54 | 64201201 | bellard | |
55 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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56 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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57 | 9a64fbe4 | bellard | #endif
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58 | 9a64fbe4 | bellard | |
59 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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60 | 001faf32 | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) \
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61 | 9a64fbe4 | bellard | do { \
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62 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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63 | 001faf32 | Blue Swirl | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
64 | 9a64fbe4 | bellard | } else { \
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65 | 001faf32 | Blue Swirl | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
66 | 9a64fbe4 | bellard | } \ |
67 | 9a64fbe4 | bellard | } while (0) |
68 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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69 | 0bf9e31a | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) \
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70 | 0bf9e31a | Blue Swirl | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) |
71 | 9a64fbe4 | bellard | #else
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72 | 001faf32 | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
73 | 9a64fbe4 | bellard | #endif
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74 | 9a64fbe4 | bellard | |
75 | 64201201 | bellard | /* Constants for devices init */
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76 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
77 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
78 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
79 | a541f297 | bellard | |
80 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
81 | a541f297 | bellard | |
82 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
83 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
84 | 9a64fbe4 | bellard | |
85 | 64201201 | bellard | /* ISA IO ports bridge */
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86 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
87 | 9a64fbe4 | bellard | |
88 | 64201201 | bellard | /* PCI intack register */
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89 | 64201201 | bellard | /* Read-only register (?) */
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90 | 0c90c52f | Avi Kivity | static void PPC_intack_write (void *opaque, target_phys_addr_t addr, |
91 | 0c90c52f | Avi Kivity | uint64_t value, unsigned size)
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92 | 64201201 | bellard | { |
93 | 90e189ec | Blue Swirl | #if 0
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94 | 0c90c52f | Avi Kivity | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
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95 | 90e189ec | Blue Swirl | value);
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96 | 90e189ec | Blue Swirl | #endif
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97 | 64201201 | bellard | } |
98 | 64201201 | bellard | |
99 | 0c90c52f | Avi Kivity | static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr, |
100 | 0c90c52f | Avi Kivity | unsigned size)
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101 | 64201201 | bellard | { |
102 | 64201201 | bellard | uint32_t retval = 0;
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103 | 64201201 | bellard | |
104 | 4dd8c138 | aurel32 | if ((addr & 0xf) == 0) |
105 | 6e5580ca | Jan Kiszka | retval = pic_read_irq(isa_pic); |
106 | 90e189ec | Blue Swirl | #if 0
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107 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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108 | 90e189ec | Blue Swirl | retval);
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109 | 90e189ec | Blue Swirl | #endif
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110 | 64201201 | bellard | |
111 | 64201201 | bellard | return retval;
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112 | 64201201 | bellard | } |
113 | 64201201 | bellard | |
114 | 0c90c52f | Avi Kivity | static const MemoryRegionOps PPC_intack_ops = { |
115 | 0c90c52f | Avi Kivity | .read = PPC_intack_read, |
116 | 0c90c52f | Avi Kivity | .write = PPC_intack_write, |
117 | 0c90c52f | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
118 | 64201201 | bellard | }; |
119 | 64201201 | bellard | |
120 | 64201201 | bellard | /* PowerPC control and status registers */
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121 | 64201201 | bellard | #if 0 // Not used
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122 | 64201201 | bellard | static struct {
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123 | 64201201 | bellard | /* IDs */
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124 | 64201201 | bellard | uint32_t veni_devi;
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125 | 64201201 | bellard | uint32_t revi;
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126 | 64201201 | bellard | /* Control and status */
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127 | 64201201 | bellard | uint32_t gcsr;
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128 | 64201201 | bellard | uint32_t xcfr;
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129 | 64201201 | bellard | uint32_t ct32;
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130 | 64201201 | bellard | uint32_t mcsr;
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131 | 64201201 | bellard | /* General purpose registers */
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132 | 64201201 | bellard | uint32_t gprg[6];
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133 | 64201201 | bellard | /* Exceptions */
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134 | 64201201 | bellard | uint32_t feen;
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135 | 64201201 | bellard | uint32_t fest;
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136 | 64201201 | bellard | uint32_t fema;
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137 | 64201201 | bellard | uint32_t fecl;
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138 | 64201201 | bellard | uint32_t eeen;
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139 | 64201201 | bellard | uint32_t eest;
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140 | 64201201 | bellard | uint32_t eecl;
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141 | 64201201 | bellard | uint32_t eeint;
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142 | 64201201 | bellard | uint32_t eemck0;
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143 | 64201201 | bellard | uint32_t eemck1;
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144 | 64201201 | bellard | /* Error diagnostic */
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145 | 64201201 | bellard | } XCSR;
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146 | 64201201 | bellard | |
147 | 36081602 | j_mayer | static void PPC_XCSR_writeb (void *opaque,
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148 | c227f099 | Anthony Liguori | target_phys_addr_t addr, uint32_t value)
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149 | 64201201 | bellard | {
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150 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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151 | 90e189ec | Blue Swirl | value);
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152 | 64201201 | bellard | }
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153 | 64201201 | bellard | |
154 | 36081602 | j_mayer | static void PPC_XCSR_writew (void *opaque,
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155 | c227f099 | Anthony Liguori | target_phys_addr_t addr, uint32_t value)
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156 | 9a64fbe4 | bellard | {
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157 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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158 | 90e189ec | Blue Swirl | value);
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159 | 9a64fbe4 | bellard | }
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160 | 9a64fbe4 | bellard | |
161 | 36081602 | j_mayer | static void PPC_XCSR_writel (void *opaque,
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162 | c227f099 | Anthony Liguori | target_phys_addr_t addr, uint32_t value)
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163 | 9a64fbe4 | bellard | {
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164 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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165 | 90e189ec | Blue Swirl | value);
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166 | 9a64fbe4 | bellard | }
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167 | 9a64fbe4 | bellard | |
168 | c227f099 | Anthony Liguori | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
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169 | 64201201 | bellard | {
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170 | 64201201 | bellard | uint32_t retval = 0;
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171 | 9a64fbe4 | bellard | |
172 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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173 | 90e189ec | Blue Swirl | retval);
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174 | 9a64fbe4 | bellard | |
175 | 64201201 | bellard | return retval;
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176 | 64201201 | bellard | }
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177 | 64201201 | bellard | |
178 | c227f099 | Anthony Liguori | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
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179 | 9a64fbe4 | bellard | {
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180 | 64201201 | bellard | uint32_t retval = 0;
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181 | 64201201 | bellard | |
182 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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183 | 90e189ec | Blue Swirl | retval);
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184 | 64201201 | bellard | |
185 | 64201201 | bellard | return retval;
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186 | 9a64fbe4 | bellard | }
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187 | 9a64fbe4 | bellard | |
188 | c227f099 | Anthony Liguori | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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189 | 9a64fbe4 | bellard | {
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190 | 9a64fbe4 | bellard | uint32_t retval = 0;
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191 | 9a64fbe4 | bellard | |
192 | 90e189ec | Blue Swirl | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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193 | 90e189ec | Blue Swirl | retval);
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194 | 9a64fbe4 | bellard | |
195 | 9a64fbe4 | bellard | return retval;
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196 | 9a64fbe4 | bellard | }
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197 | 9a64fbe4 | bellard | |
198 | 0c90c52f | Avi Kivity | static const MemoryRegionOps PPC_XCSR_ops = {
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199 | 0c90c52f | Avi Kivity | .old_mmio = {
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200 | 0c90c52f | Avi Kivity | .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
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201 | 0c90c52f | Avi Kivity | .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
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202 | 0c90c52f | Avi Kivity | },
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203 | 0c90c52f | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN,
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204 | 9a64fbe4 | bellard | };
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205 | 9a64fbe4 | bellard | |
206 | b6b8bd18 | bellard | #endif
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207 | 9a64fbe4 | bellard | |
208 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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209 | c227f099 | Anthony Liguori | typedef struct sysctrl_t { |
210 | c4781a51 | j_mayer | qemu_irq reset_irq; |
211 | 43a34704 | Blue Swirl | M48t59State *nvram; |
212 | 64201201 | bellard | uint8_t state; |
213 | 64201201 | bellard | uint8_t syscontrol; |
214 | 64201201 | bellard | uint8_t fake_io[2];
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215 | da9b266b | bellard | int contiguous_map;
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216 | fb3444b8 | bellard | int endian;
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217 | c227f099 | Anthony Liguori | } sysctrl_t; |
218 | 9a64fbe4 | bellard | |
219 | 64201201 | bellard | enum {
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220 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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221 | 9a64fbe4 | bellard | }; |
222 | 9a64fbe4 | bellard | |
223 | c227f099 | Anthony Liguori | static sysctrl_t *sysctrl;
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224 | 9a64fbe4 | bellard | |
225 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
226 | 9a64fbe4 | bellard | { |
227 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
228 | 64201201 | bellard | |
229 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
230 | aae9366a | j_mayer | val); |
231 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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232 | 9a64fbe4 | bellard | } |
233 | 9a64fbe4 | bellard | |
234 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
235 | 9a64fbe4 | bellard | { |
236 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
237 | 9a64fbe4 | bellard | |
238 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
239 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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240 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
241 | 64201201 | bellard | } |
242 | 9a64fbe4 | bellard | |
243 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
244 | 9a64fbe4 | bellard | { |
245 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
246 | 64201201 | bellard | |
247 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
248 | aae9366a | j_mayer | addr - PPC_IO_BASE, val); |
249 | 9a64fbe4 | bellard | switch (addr) {
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250 | 9a64fbe4 | bellard | case 0x0092: |
251 | 9a64fbe4 | bellard | /* Special port 92 */
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252 | 9a64fbe4 | bellard | /* Check soft reset asked */
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253 | 64201201 | bellard | if (val & 0x01) { |
254 | c4781a51 | j_mayer | qemu_irq_raise(sysctrl->reset_irq); |
255 | c4781a51 | j_mayer | } else {
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256 | c4781a51 | j_mayer | qemu_irq_lower(sysctrl->reset_irq); |
257 | 9a64fbe4 | bellard | } |
258 | 9a64fbe4 | bellard | /* Check LE mode */
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259 | 64201201 | bellard | if (val & 0x02) { |
260 | fb3444b8 | bellard | sysctrl->endian = 1;
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261 | fb3444b8 | bellard | } else {
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262 | fb3444b8 | bellard | sysctrl->endian = 0;
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263 | 9a64fbe4 | bellard | } |
264 | 9a64fbe4 | bellard | break;
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265 | 64201201 | bellard | case 0x0800: |
266 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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267 | 64201201 | bellard | break;
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268 | 64201201 | bellard | case 0x0802: |
269 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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270 | 64201201 | bellard | break;
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271 | 64201201 | bellard | case 0x0803: |
272 | 64201201 | bellard | /* Motorola base module status register : read-only */
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273 | 64201201 | bellard | break;
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274 | 9a64fbe4 | bellard | case 0x0808: |
275 | 64201201 | bellard | /* Hardfile light register */
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276 | 64201201 | bellard | if (val & 1) |
277 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
278 | 64201201 | bellard | else
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279 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
280 | 9a64fbe4 | bellard | break;
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281 | 9a64fbe4 | bellard | case 0x0810: |
282 | 9a64fbe4 | bellard | /* Password protect 1 register */
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283 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
284 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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285 | 9a64fbe4 | bellard | break;
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286 | 9a64fbe4 | bellard | case 0x0812: |
287 | 9a64fbe4 | bellard | /* Password protect 2 register */
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288 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
289 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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290 | 9a64fbe4 | bellard | break;
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291 | 9a64fbe4 | bellard | case 0x0814: |
292 | 64201201 | bellard | /* L2 invalidate register */
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293 | c68ea704 | bellard | // tlb_flush(first_cpu, 1);
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294 | 9a64fbe4 | bellard | break;
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295 | 9a64fbe4 | bellard | case 0x081C: |
296 | 9a64fbe4 | bellard | /* system control register */
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297 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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298 | 9a64fbe4 | bellard | break;
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299 | 9a64fbe4 | bellard | case 0x0850: |
300 | 9a64fbe4 | bellard | /* I/O map type register */
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301 | da9b266b | bellard | sysctrl->contiguous_map = val & 0x01;
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302 | 9a64fbe4 | bellard | break;
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303 | 9a64fbe4 | bellard | default:
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304 | aae9366a | j_mayer | printf("ERROR: unaffected IO port write: %04" PRIx32
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305 | aae9366a | j_mayer | " => %02" PRIx32"\n", addr, val); |
306 | 9a64fbe4 | bellard | break;
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307 | 9a64fbe4 | bellard | } |
308 | 9a64fbe4 | bellard | } |
309 | 9a64fbe4 | bellard | |
310 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
311 | 9a64fbe4 | bellard | { |
312 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
313 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
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314 | 9a64fbe4 | bellard | |
315 | 9a64fbe4 | bellard | switch (addr) {
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316 | 9a64fbe4 | bellard | case 0x0092: |
317 | 9a64fbe4 | bellard | /* Special port 92 */
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318 | 64201201 | bellard | retval = 0x00;
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319 | 64201201 | bellard | break;
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320 | 64201201 | bellard | case 0x0800: |
321 | 64201201 | bellard | /* Motorola CPU configuration register */
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322 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
323 | 64201201 | bellard | break;
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324 | 64201201 | bellard | case 0x0802: |
325 | 64201201 | bellard | /* Motorola Base module feature register */
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326 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
327 | 64201201 | bellard | break;
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328 | 64201201 | bellard | case 0x0803: |
329 | 64201201 | bellard | /* Motorola base module status register */
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330 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
331 | 9a64fbe4 | bellard | break;
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332 | 9a64fbe4 | bellard | case 0x080C: |
333 | 9a64fbe4 | bellard | /* Equipment present register:
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334 | 9a64fbe4 | bellard | * no L2 cache
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335 | 9a64fbe4 | bellard | * no upgrade processor
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336 | 9a64fbe4 | bellard | * no cards in PCI slots
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337 | 9a64fbe4 | bellard | * SCSI fuse is bad
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338 | 9a64fbe4 | bellard | */
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339 | 64201201 | bellard | retval = 0x3C;
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340 | 64201201 | bellard | break;
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341 | 64201201 | bellard | case 0x0810: |
342 | 64201201 | bellard | /* Motorola base module extended feature register */
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343 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
344 | 9a64fbe4 | bellard | break;
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345 | da9b266b | bellard | case 0x0814: |
346 | da9b266b | bellard | /* L2 invalidate: don't care */
|
347 | da9b266b | bellard | break;
|
348 | 9a64fbe4 | bellard | case 0x0818: |
349 | 9a64fbe4 | bellard | /* Keylock */
|
350 | 9a64fbe4 | bellard | retval = 0x00;
|
351 | 9a64fbe4 | bellard | break;
|
352 | 9a64fbe4 | bellard | case 0x081C: |
353 | 9a64fbe4 | bellard | /* system control register
|
354 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
355 | 9a64fbe4 | bellard | */
|
356 | 64201201 | bellard | retval = sysctrl->syscontrol; |
357 | 9a64fbe4 | bellard | break;
|
358 | 9a64fbe4 | bellard | case 0x0823: |
359 | 9a64fbe4 | bellard | /* */
|
360 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
361 | 9a64fbe4 | bellard | break;
|
362 | 9a64fbe4 | bellard | case 0x0850: |
363 | 9a64fbe4 | bellard | /* I/O map type register */
|
364 | da9b266b | bellard | retval = sysctrl->contiguous_map; |
365 | 9a64fbe4 | bellard | break;
|
366 | 9a64fbe4 | bellard | default:
|
367 | aae9366a | j_mayer | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
368 | 9a64fbe4 | bellard | break;
|
369 | 9a64fbe4 | bellard | } |
370 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
371 | aae9366a | j_mayer | addr - PPC_IO_BASE, retval); |
372 | 9a64fbe4 | bellard | |
373 | 9a64fbe4 | bellard | return retval;
|
374 | 9a64fbe4 | bellard | } |
375 | 9a64fbe4 | bellard | |
376 | c227f099 | Anthony Liguori | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
377 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
378 | da9b266b | bellard | { |
379 | da9b266b | bellard | if (sysctrl->contiguous_map == 0) { |
380 | da9b266b | bellard | /* 64 KB contiguous space for IOs */
|
381 | da9b266b | bellard | addr &= 0xFFFF;
|
382 | da9b266b | bellard | } else {
|
383 | da9b266b | bellard | /* 8 MB non-contiguous space for IOs */
|
384 | da9b266b | bellard | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
385 | da9b266b | bellard | } |
386 | da9b266b | bellard | |
387 | da9b266b | bellard | return addr;
|
388 | da9b266b | bellard | } |
389 | da9b266b | bellard | |
390 | c227f099 | Anthony Liguori | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
391 | da9b266b | bellard | uint32_t value) |
392 | da9b266b | bellard | { |
393 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
394 | da9b266b | bellard | |
395 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
396 | afcea8cb | Blue Swirl | cpu_outb(addr, value); |
397 | da9b266b | bellard | } |
398 | da9b266b | bellard | |
399 | c227f099 | Anthony Liguori | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
400 | da9b266b | bellard | { |
401 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
402 | da9b266b | bellard | uint32_t ret; |
403 | da9b266b | bellard | |
404 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
405 | afcea8cb | Blue Swirl | ret = cpu_inb(addr); |
406 | da9b266b | bellard | |
407 | da9b266b | bellard | return ret;
|
408 | da9b266b | bellard | } |
409 | da9b266b | bellard | |
410 | c227f099 | Anthony Liguori | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
411 | da9b266b | bellard | uint32_t value) |
412 | da9b266b | bellard | { |
413 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
414 | da9b266b | bellard | |
415 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
416 | 90e189ec | Blue Swirl | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
417 | afcea8cb | Blue Swirl | cpu_outw(addr, value); |
418 | da9b266b | bellard | } |
419 | da9b266b | bellard | |
420 | c227f099 | Anthony Liguori | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
421 | da9b266b | bellard | { |
422 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
423 | da9b266b | bellard | uint32_t ret; |
424 | da9b266b | bellard | |
425 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
426 | afcea8cb | Blue Swirl | ret = cpu_inw(addr); |
427 | 90e189ec | Blue Swirl | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
428 | da9b266b | bellard | |
429 | da9b266b | bellard | return ret;
|
430 | da9b266b | bellard | } |
431 | da9b266b | bellard | |
432 | c227f099 | Anthony Liguori | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
433 | da9b266b | bellard | uint32_t value) |
434 | da9b266b | bellard | { |
435 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
436 | da9b266b | bellard | |
437 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
438 | 90e189ec | Blue Swirl | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
439 | afcea8cb | Blue Swirl | cpu_outl(addr, value); |
440 | da9b266b | bellard | } |
441 | da9b266b | bellard | |
442 | c227f099 | Anthony Liguori | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
443 | da9b266b | bellard | { |
444 | c227f099 | Anthony Liguori | sysctrl_t *sysctrl = opaque; |
445 | da9b266b | bellard | uint32_t ret; |
446 | da9b266b | bellard | |
447 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
448 | afcea8cb | Blue Swirl | ret = cpu_inl(addr); |
449 | 90e189ec | Blue Swirl | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
450 | da9b266b | bellard | |
451 | da9b266b | bellard | return ret;
|
452 | da9b266b | bellard | } |
453 | da9b266b | bellard | |
454 | 0c90c52f | Avi Kivity | static const MemoryRegionOps PPC_prep_io_ops = { |
455 | 0c90c52f | Avi Kivity | .old_mmio = { |
456 | 0c90c52f | Avi Kivity | .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, |
457 | 0c90c52f | Avi Kivity | .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, |
458 | 0c90c52f | Avi Kivity | }, |
459 | 0c90c52f | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
460 | da9b266b | bellard | }; |
461 | da9b266b | bellard | |
462 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
463 | a541f297 | bellard | |
464 | 4556bd8b | Blue Swirl | static void cpu_request_exit(void *opaque, int irq, int level) |
465 | 4556bd8b | Blue Swirl | { |
466 | e2684c0b | Andreas Färber | CPUPPCState *env = cpu_single_env; |
467 | 4556bd8b | Blue Swirl | |
468 | 4556bd8b | Blue Swirl | if (env && level) {
|
469 | 4556bd8b | Blue Swirl | cpu_exit(env); |
470 | 4556bd8b | Blue Swirl | } |
471 | 4556bd8b | Blue Swirl | } |
472 | 4556bd8b | Blue Swirl | |
473 | 1bba0dc9 | Andreas Färber | static void ppc_prep_reset(void *opaque) |
474 | 1bba0dc9 | Andreas Färber | { |
475 | e2684c0b | Andreas Färber | CPUPPCState *env = opaque; |
476 | 1bba0dc9 | Andreas Färber | |
477 | 1bba0dc9 | Andreas Färber | cpu_state_reset(env); |
478 | 1bba0dc9 | Andreas Färber | } |
479 | 1bba0dc9 | Andreas Färber | |
480 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
481 | c227f099 | Anthony Liguori | static void ppc_prep_init (ram_addr_t ram_size, |
482 | 3023f332 | aliguori | const char *boot_device, |
483 | b881c2c6 | blueswir1 | const char *kernel_filename, |
484 | 94fc95cd | j_mayer | const char *kernel_cmdline, |
485 | 94fc95cd | j_mayer | const char *initrd_filename, |
486 | 94fc95cd | j_mayer | const char *cpu_model) |
487 | a541f297 | bellard | { |
488 | 0c90c52f | Avi Kivity | MemoryRegion *sysmem = get_system_memory(); |
489 | e2684c0b | Andreas Färber | CPUPPCState *env = NULL;
|
490 | 5cea8590 | Paul Brook | char *filename;
|
491 | c227f099 | Anthony Liguori | nvram_t nvram; |
492 | 43a34704 | Blue Swirl | M48t59State *m48t59; |
493 | 0c90c52f | Avi Kivity | MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
|
494 | 0c90c52f | Avi Kivity | MemoryRegion *intack = g_new(MemoryRegion, 1);
|
495 | 0c90c52f | Avi Kivity | #if 0
|
496 | 0c90c52f | Avi Kivity | MemoryRegion *xcsr = g_new(MemoryRegion, 1);
|
497 | 0c90c52f | Avi Kivity | #endif
|
498 | 4157a662 | bellard | int linux_boot, i, nb_nics1, bios_size;
|
499 | 0c90c52f | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
|
500 | 0c90c52f | Avi Kivity | MemoryRegion *bios = g_new(MemoryRegion, 1);
|
501 | 093209cd | Blue Swirl | uint32_t kernel_base, initrd_base; |
502 | 093209cd | Blue Swirl | long kernel_size, initrd_size;
|
503 | 8ca8c7bc | Andreas Färber | DeviceState *dev; |
504 | 8ca8c7bc | Andreas Färber | SysBusDevice *sys; |
505 | 8ca8c7bc | Andreas Färber | PCIHostState *pcihost; |
506 | 46e50e9d | bellard | PCIBus *pci_bus; |
507 | 506b7ddf | Andreas Färber | PCIDevice *pci; |
508 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
509 | 4556bd8b | Blue Swirl | qemu_irq *cpu_exit_irq; |
510 | 28c5af54 | j_mayer | int ppc_boot_device;
|
511 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
512 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
513 | 64201201 | bellard | |
514 | 7267c094 | Anthony Liguori | sysctrl = g_malloc0(sizeof(sysctrl_t));
|
515 | a541f297 | bellard | |
516 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
517 | 0a032cbe | j_mayer | |
518 | c68ea704 | bellard | /* init CPUs */
|
519 | 94fc95cd | j_mayer | if (cpu_model == NULL) |
520 | b37fc148 | Gerd Hoffmann | cpu_model = "602";
|
521 | fe33cc71 | j_mayer | for (i = 0; i < smp_cpus; i++) { |
522 | aaed909a | bellard | env = cpu_init(cpu_model); |
523 | aaed909a | bellard | if (!env) {
|
524 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
525 | aaed909a | bellard | exit(1);
|
526 | aaed909a | bellard | } |
527 | 4018bae9 | j_mayer | if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
528 | 4018bae9 | j_mayer | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
529 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 7812500UL);
|
530 | 4018bae9 | j_mayer | } else {
|
531 | 4018bae9 | j_mayer | /* Set time-base frequency to 100 Mhz */
|
532 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
533 | 4018bae9 | j_mayer | } |
534 | 1bba0dc9 | Andreas Färber | qemu_register_reset(ppc_prep_reset, env); |
535 | fe33cc71 | j_mayer | } |
536 | a541f297 | bellard | |
537 | a541f297 | bellard | /* allocate RAM */
|
538 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
|
539 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
540 | 0c90c52f | Avi Kivity | memory_region_add_subregion(sysmem, 0, ram);
|
541 | cf9c147c | blueswir1 | |
542 | 64201201 | bellard | /* allocate and load BIOS */
|
543 | c5705a77 | Avi Kivity | memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
|
544 | 809680c0 | Andreas Färber | memory_region_set_readonly(bios, true);
|
545 | 809680c0 | Andreas Färber | memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); |
546 | c5705a77 | Avi Kivity | vmstate_register_ram_global(bios); |
547 | 1192dad8 | j_mayer | if (bios_name == NULL) |
548 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
549 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
550 | 5cea8590 | Paul Brook | if (filename) {
|
551 | 5cea8590 | Paul Brook | bios_size = get_image_size(filename); |
552 | 5cea8590 | Paul Brook | } else {
|
553 | 5cea8590 | Paul Brook | bios_size = -1;
|
554 | 5cea8590 | Paul Brook | } |
555 | dcac9679 | pbrook | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
556 | c227f099 | Anthony Liguori | target_phys_addr_t bios_addr; |
557 | dcac9679 | pbrook | bios_size = (bios_size + 0xfff) & ~0xfff; |
558 | dcac9679 | pbrook | bios_addr = (uint32_t)(-bios_size); |
559 | 5cea8590 | Paul Brook | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
560 | dcac9679 | pbrook | } |
561 | 4157a662 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
562 | 5cea8590 | Paul Brook | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
|
563 | 5cea8590 | Paul Brook | } |
564 | 5cea8590 | Paul Brook | if (filename) {
|
565 | 7267c094 | Anthony Liguori | g_free(filename); |
566 | 64201201 | bellard | } |
567 | 26aa7d72 | bellard | |
568 | a541f297 | bellard | if (linux_boot) {
|
569 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
570 | a541f297 | bellard | /* now we can load the kernel */
|
571 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
572 | dcac9679 | pbrook | ram_size - kernel_base); |
573 | 64201201 | bellard | if (kernel_size < 0) { |
574 | 2ac71179 | Paul Brook | hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
|
575 | a541f297 | bellard | exit(1);
|
576 | a541f297 | bellard | } |
577 | a541f297 | bellard | /* load initrd */
|
578 | a541f297 | bellard | if (initrd_filename) {
|
579 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
580 | dcac9679 | pbrook | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
581 | dcac9679 | pbrook | ram_size - initrd_base); |
582 | a541f297 | bellard | if (initrd_size < 0) { |
583 | 2ac71179 | Paul Brook | hw_error("qemu: could not load initial ram disk '%s'\n",
|
584 | 4a057712 | j_mayer | initrd_filename); |
585 | a541f297 | bellard | } |
586 | 64201201 | bellard | } else {
|
587 | 64201201 | bellard | initrd_base = 0;
|
588 | 64201201 | bellard | initrd_size = 0;
|
589 | a541f297 | bellard | } |
590 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
591 | a541f297 | bellard | } else {
|
592 | 64201201 | bellard | kernel_base = 0;
|
593 | 64201201 | bellard | kernel_size = 0;
|
594 | 64201201 | bellard | initrd_base = 0;
|
595 | 64201201 | bellard | initrd_size = 0;
|
596 | 28c5af54 | j_mayer | ppc_boot_device = '\0';
|
597 | 28c5af54 | j_mayer | /* For now, OHW cannot boot from the network. */
|
598 | 0d913fdb | j_mayer | for (i = 0; boot_device[i] != '\0'; i++) { |
599 | 0d913fdb | j_mayer | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
600 | 0d913fdb | j_mayer | ppc_boot_device = boot_device[i]; |
601 | 28c5af54 | j_mayer | break;
|
602 | 0d913fdb | j_mayer | } |
603 | 28c5af54 | j_mayer | } |
604 | 28c5af54 | j_mayer | if (ppc_boot_device == '\0') { |
605 | 28c5af54 | j_mayer | fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
606 | 28c5af54 | j_mayer | exit(1);
|
607 | 28c5af54 | j_mayer | } |
608 | a541f297 | bellard | } |
609 | a541f297 | bellard | |
610 | dd37a5e4 | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
611 | 2ac71179 | Paul Brook | hw_error("Only 6xx bus is supported on PREP machine\n");
|
612 | dd37a5e4 | j_mayer | } |
613 | 8ca8c7bc | Andreas Färber | |
614 | 8ca8c7bc | Andreas Färber | dev = qdev_create(NULL, "raven-pcihost"); |
615 | 8ca8c7bc | Andreas Färber | sys = sysbus_from_qdev(dev); |
616 | 8ca8c7bc | Andreas Färber | pcihost = DO_UPCAST(PCIHostState, busdev, sys); |
617 | 8ca8c7bc | Andreas Färber | pcihost->address_space = get_system_memory(); |
618 | 57c9fafe | Anthony Liguori | object_property_add_child(object_get_root(), "raven", OBJECT(dev), NULL); |
619 | f424d5c4 | Paolo Bonzini | qdev_init_nofail(dev); |
620 | 8ca8c7bc | Andreas Färber | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
621 | 8ca8c7bc | Andreas Färber | if (pci_bus == NULL) { |
622 | 8ca8c7bc | Andreas Färber | fprintf(stderr, "Couldn't create PCI host controller.\n");
|
623 | 8ca8c7bc | Andreas Färber | exit(1);
|
624 | 8ca8c7bc | Andreas Färber | } |
625 | 8ca8c7bc | Andreas Färber | |
626 | 506b7ddf | Andreas Färber | /* PCI -> ISA bridge */
|
627 | 506b7ddf | Andreas Färber | pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); |
628 | 506b7ddf | Andreas Färber | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
629 | 506b7ddf | Andreas Färber | qdev_connect_gpio_out(&pci->qdev, 0,
|
630 | 506b7ddf | Andreas Färber | first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
631 | 506b7ddf | Andreas Färber | qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
|
632 | 506b7ddf | Andreas Färber | sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); |
633 | 506b7ddf | Andreas Färber | sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); |
634 | 506b7ddf | Andreas Färber | sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); |
635 | 506b7ddf | Andreas Färber | sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); |
636 | 506b7ddf | Andreas Färber | isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
|
637 | 506b7ddf | Andreas Färber | |
638 | da9b266b | bellard | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
639 | 0c90c52f | Avi Kivity | memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, |
640 | 0c90c52f | Avi Kivity | "ppc-io", 0x00800000); |
641 | 0c90c52f | Avi Kivity | memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
|
642 | 64201201 | bellard | |
643 | a541f297 | bellard | /* init basic PC hardware */
|
644 | 78895427 | Gerd Hoffmann | pci_vga_init(pci_bus); |
645 | a541f297 | bellard | |
646 | ac0be998 | Gerd Hoffmann | if (serial_hds[0]) |
647 | 48a18b3c | Hervé Poussineau | serial_isa_init(isa_bus, 0, serial_hds[0]); |
648 | a541f297 | bellard | nb_nics1 = nb_nics; |
649 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
650 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
651 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
652 | 5652ef78 | aurel32 | if (nd_table[i].model == NULL) { |
653 | 7267c094 | Anthony Liguori | nd_table[i].model = g_strdup("ne2k_isa");
|
654 | 5652ef78 | aurel32 | } |
655 | 5652ef78 | aurel32 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
656 | 48a18b3c | Hervé Poussineau | isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], |
657 | 48a18b3c | Hervé Poussineau | &nd_table[i]); |
658 | a41b2ff2 | pbrook | } else {
|
659 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
660 | a41b2ff2 | pbrook | } |
661 | a541f297 | bellard | } |
662 | a541f297 | bellard | |
663 | 75717903 | Isaku Yamahata | ide_drive_get(hd, MAX_IDE_BUS); |
664 | 81aa0647 | Aurelien Jarno | for(i = 0; i < MAX_IDE_BUS; i++) { |
665 | 48a18b3c | Hervé Poussineau | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
666 | e4bcb14c | ths | hd[2 * i],
|
667 | e4bcb14c | ths | hd[2 * i + 1]); |
668 | a541f297 | bellard | } |
669 | 48a18b3c | Hervé Poussineau | isa_create_simple(isa_bus, "i8042");
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670 | 4556bd8b | Blue Swirl | |
671 | a541f297 | bellard | // SB16_init();
|
672 | a541f297 | bellard | |
673 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
674 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
675 | e4bcb14c | ths | } |
676 | 48a18b3c | Hervé Poussineau | fdctrl_init_isa(isa_bus, fd); |
677 | a541f297 | bellard | |
678 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
679 | c4781a51 | j_mayer | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
680 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
681 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
682 | a541f297 | bellard | /* System control ports */
|
683 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
684 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
685 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
686 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
687 | 64201201 | bellard | /* PCI intack location */
|
688 | 0c90c52f | Avi Kivity | memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4); |
689 | 0c90c52f | Avi Kivity | memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack);
|
690 | 64201201 | bellard | /* PowerPC control and status register group */
|
691 | b6b8bd18 | bellard | #if 0
|
692 | 0c90c52f | Avi Kivity | memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
|
693 | 0c90c52f | Avi Kivity | memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
|
694 | b6b8bd18 | bellard | #endif
|
695 | a541f297 | bellard | |
696 | 0d92ed30 | pbrook | if (usb_enabled) {
|
697 | afb9a60e | Gerd Hoffmann | pci_create_simple(pci_bus, -1, "pci-ohci"); |
698 | 0d92ed30 | pbrook | } |
699 | 0d92ed30 | pbrook | |
700 | 48e93728 | Andreas Färber | m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
701 | 3cbee15b | j_mayer | if (m48t59 == NULL) |
702 | 64201201 | bellard | return;
|
703 | 3cbee15b | j_mayer | sysctrl->nvram = m48t59; |
704 | 64201201 | bellard | |
705 | 64201201 | bellard | /* Initialise NVRAM */
|
706 | 3cbee15b | j_mayer | nvram.opaque = m48t59; |
707 | 3cbee15b | j_mayer | nvram.read_fn = &m48t59_read; |
708 | 3cbee15b | j_mayer | nvram.write_fn = &m48t59_write; |
709 | 6ac0e82d | balrog | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
710 | 64201201 | bellard | kernel_base, kernel_size, |
711 | b6b8bd18 | bellard | kernel_cmdline, |
712 | 64201201 | bellard | initrd_base, initrd_size, |
713 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
714 | b6b8bd18 | bellard | 0,
|
715 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
716 | c0e564d5 | bellard | |
717 | c0e564d5 | bellard | /* Special port to get debug messages from Open-Firmware */
|
718 | c0e564d5 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
719 | a541f297 | bellard | } |
720 | c0e564d5 | bellard | |
721 | f80f9ec9 | Anthony Liguori | static QEMUMachine prep_machine = {
|
722 | 4b32e168 | aliguori | .name = "prep",
|
723 | 4b32e168 | aliguori | .desc = "PowerPC PREP platform",
|
724 | 4b32e168 | aliguori | .init = ppc_prep_init, |
725 | 3d878caa | balrog | .max_cpus = MAX_CPUS, |
726 | c0e564d5 | bellard | }; |
727 | f80f9ec9 | Anthony Liguori | |
728 | f80f9ec9 | Anthony Liguori | static void prep_machine_init(void) |
729 | f80f9ec9 | Anthony Liguori | { |
730 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&prep_machine); |
731 | f80f9ec9 | Anthony Liguori | } |
732 | f80f9ec9 | Anthony Liguori | |
733 | f80f9ec9 | Anthony Liguori | machine_init(prep_machine_init); |