root / target-i386 / ops_sse.h @ f45748f1
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1 | 664e0f19 | bellard | /*
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2 | 222a3336 | balrog | * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
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3 | 5fafdf24 | ths | *
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4 | 664e0f19 | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 222a3336 | balrog | * Copyright (c) 2008 Intel Corporation <andrew.zaborowski@intel.com>
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6 | 664e0f19 | bellard | *
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7 | 664e0f19 | bellard | * This library is free software; you can redistribute it and/or
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8 | 664e0f19 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 664e0f19 | bellard | * License as published by the Free Software Foundation; either
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10 | 664e0f19 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 664e0f19 | bellard | *
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12 | 664e0f19 | bellard | * This library is distributed in the hope that it will be useful,
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13 | 664e0f19 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 664e0f19 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 664e0f19 | bellard | * Lesser General Public License for more details.
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16 | 664e0f19 | bellard | *
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17 | 664e0f19 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 664e0f19 | bellard | */
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20 | 664e0f19 | bellard | #if SHIFT == 0 |
21 | 664e0f19 | bellard | #define Reg MMXReg
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22 | 001faf32 | Blue Swirl | #define XMM_ONLY(...)
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23 | 664e0f19 | bellard | #define B(n) MMX_B(n)
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24 | 664e0f19 | bellard | #define W(n) MMX_W(n)
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25 | 664e0f19 | bellard | #define L(n) MMX_L(n)
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26 | 664e0f19 | bellard | #define Q(n) q
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27 | 664e0f19 | bellard | #define SUFFIX _mmx
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28 | 664e0f19 | bellard | #else
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29 | 664e0f19 | bellard | #define Reg XMMReg
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30 | 001faf32 | Blue Swirl | #define XMM_ONLY(...) __VA_ARGS__
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31 | 664e0f19 | bellard | #define B(n) XMM_B(n)
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32 | 664e0f19 | bellard | #define W(n) XMM_W(n)
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33 | 664e0f19 | bellard | #define L(n) XMM_L(n)
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34 | 664e0f19 | bellard | #define Q(n) XMM_Q(n)
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35 | 664e0f19 | bellard | #define SUFFIX _xmm
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36 | 664e0f19 | bellard | #endif
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37 | 664e0f19 | bellard | |
38 | d3eb5eae | Blue Swirl | void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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39 | 664e0f19 | bellard | { |
40 | 664e0f19 | bellard | int shift;
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41 | 664e0f19 | bellard | |
42 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
43 | 664e0f19 | bellard | d->Q(0) = 0; |
44 | 664e0f19 | bellard | #if SHIFT == 1 |
45 | 664e0f19 | bellard | d->Q(1) = 0; |
46 | 664e0f19 | bellard | #endif
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47 | 664e0f19 | bellard | } else {
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48 | 664e0f19 | bellard | shift = s->B(0);
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49 | 664e0f19 | bellard | d->W(0) >>= shift;
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50 | 664e0f19 | bellard | d->W(1) >>= shift;
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51 | 664e0f19 | bellard | d->W(2) >>= shift;
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52 | 664e0f19 | bellard | d->W(3) >>= shift;
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53 | 664e0f19 | bellard | #if SHIFT == 1 |
54 | 664e0f19 | bellard | d->W(4) >>= shift;
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55 | 664e0f19 | bellard | d->W(5) >>= shift;
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56 | 664e0f19 | bellard | d->W(6) >>= shift;
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57 | 664e0f19 | bellard | d->W(7) >>= shift;
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58 | 664e0f19 | bellard | #endif
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59 | 664e0f19 | bellard | } |
60 | 664e0f19 | bellard | } |
61 | 664e0f19 | bellard | |
62 | d3eb5eae | Blue Swirl | void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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63 | 664e0f19 | bellard | { |
64 | 664e0f19 | bellard | int shift;
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65 | 664e0f19 | bellard | |
66 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
67 | 664e0f19 | bellard | shift = 15;
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68 | 664e0f19 | bellard | } else {
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69 | 664e0f19 | bellard | shift = s->B(0);
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70 | 664e0f19 | bellard | } |
71 | 664e0f19 | bellard | d->W(0) = (int16_t)d->W(0) >> shift; |
72 | 664e0f19 | bellard | d->W(1) = (int16_t)d->W(1) >> shift; |
73 | 664e0f19 | bellard | d->W(2) = (int16_t)d->W(2) >> shift; |
74 | 664e0f19 | bellard | d->W(3) = (int16_t)d->W(3) >> shift; |
75 | 664e0f19 | bellard | #if SHIFT == 1 |
76 | 664e0f19 | bellard | d->W(4) = (int16_t)d->W(4) >> shift; |
77 | 664e0f19 | bellard | d->W(5) = (int16_t)d->W(5) >> shift; |
78 | 664e0f19 | bellard | d->W(6) = (int16_t)d->W(6) >> shift; |
79 | 664e0f19 | bellard | d->W(7) = (int16_t)d->W(7) >> shift; |
80 | 664e0f19 | bellard | #endif
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81 | 664e0f19 | bellard | } |
82 | 664e0f19 | bellard | |
83 | d3eb5eae | Blue Swirl | void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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84 | 664e0f19 | bellard | { |
85 | 664e0f19 | bellard | int shift;
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86 | 664e0f19 | bellard | |
87 | 664e0f19 | bellard | if (s->Q(0) > 15) { |
88 | 664e0f19 | bellard | d->Q(0) = 0; |
89 | 664e0f19 | bellard | #if SHIFT == 1 |
90 | 664e0f19 | bellard | d->Q(1) = 0; |
91 | 664e0f19 | bellard | #endif
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92 | 664e0f19 | bellard | } else {
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93 | 664e0f19 | bellard | shift = s->B(0);
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94 | 664e0f19 | bellard | d->W(0) <<= shift;
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95 | 664e0f19 | bellard | d->W(1) <<= shift;
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96 | 664e0f19 | bellard | d->W(2) <<= shift;
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97 | 664e0f19 | bellard | d->W(3) <<= shift;
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98 | 664e0f19 | bellard | #if SHIFT == 1 |
99 | 664e0f19 | bellard | d->W(4) <<= shift;
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100 | 664e0f19 | bellard | d->W(5) <<= shift;
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101 | 664e0f19 | bellard | d->W(6) <<= shift;
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102 | 664e0f19 | bellard | d->W(7) <<= shift;
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103 | 664e0f19 | bellard | #endif
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104 | 664e0f19 | bellard | } |
105 | 664e0f19 | bellard | } |
106 | 664e0f19 | bellard | |
107 | d3eb5eae | Blue Swirl | void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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108 | 664e0f19 | bellard | { |
109 | 664e0f19 | bellard | int shift;
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110 | 664e0f19 | bellard | |
111 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
112 | 664e0f19 | bellard | d->Q(0) = 0; |
113 | 664e0f19 | bellard | #if SHIFT == 1 |
114 | 664e0f19 | bellard | d->Q(1) = 0; |
115 | 664e0f19 | bellard | #endif
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116 | 664e0f19 | bellard | } else {
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117 | 664e0f19 | bellard | shift = s->B(0);
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118 | 664e0f19 | bellard | d->L(0) >>= shift;
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119 | 664e0f19 | bellard | d->L(1) >>= shift;
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120 | 664e0f19 | bellard | #if SHIFT == 1 |
121 | 664e0f19 | bellard | d->L(2) >>= shift;
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122 | 664e0f19 | bellard | d->L(3) >>= shift;
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123 | 664e0f19 | bellard | #endif
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124 | 664e0f19 | bellard | } |
125 | 664e0f19 | bellard | } |
126 | 664e0f19 | bellard | |
127 | d3eb5eae | Blue Swirl | void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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128 | 664e0f19 | bellard | { |
129 | 664e0f19 | bellard | int shift;
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130 | 664e0f19 | bellard | |
131 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
132 | 664e0f19 | bellard | shift = 31;
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133 | 664e0f19 | bellard | } else {
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134 | 664e0f19 | bellard | shift = s->B(0);
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135 | 664e0f19 | bellard | } |
136 | 664e0f19 | bellard | d->L(0) = (int32_t)d->L(0) >> shift; |
137 | 664e0f19 | bellard | d->L(1) = (int32_t)d->L(1) >> shift; |
138 | 664e0f19 | bellard | #if SHIFT == 1 |
139 | 664e0f19 | bellard | d->L(2) = (int32_t)d->L(2) >> shift; |
140 | 664e0f19 | bellard | d->L(3) = (int32_t)d->L(3) >> shift; |
141 | 664e0f19 | bellard | #endif
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142 | 664e0f19 | bellard | } |
143 | 664e0f19 | bellard | |
144 | d3eb5eae | Blue Swirl | void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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145 | 664e0f19 | bellard | { |
146 | 664e0f19 | bellard | int shift;
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147 | 664e0f19 | bellard | |
148 | 664e0f19 | bellard | if (s->Q(0) > 31) { |
149 | 664e0f19 | bellard | d->Q(0) = 0; |
150 | 664e0f19 | bellard | #if SHIFT == 1 |
151 | 664e0f19 | bellard | d->Q(1) = 0; |
152 | 664e0f19 | bellard | #endif
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153 | 664e0f19 | bellard | } else {
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154 | 664e0f19 | bellard | shift = s->B(0);
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155 | 664e0f19 | bellard | d->L(0) <<= shift;
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156 | 664e0f19 | bellard | d->L(1) <<= shift;
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157 | 664e0f19 | bellard | #if SHIFT == 1 |
158 | 664e0f19 | bellard | d->L(2) <<= shift;
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159 | 664e0f19 | bellard | d->L(3) <<= shift;
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160 | 664e0f19 | bellard | #endif
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161 | 664e0f19 | bellard | } |
162 | 664e0f19 | bellard | } |
163 | 664e0f19 | bellard | |
164 | d3eb5eae | Blue Swirl | void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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165 | 664e0f19 | bellard | { |
166 | 664e0f19 | bellard | int shift;
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167 | 664e0f19 | bellard | |
168 | 664e0f19 | bellard | if (s->Q(0) > 63) { |
169 | 664e0f19 | bellard | d->Q(0) = 0; |
170 | 664e0f19 | bellard | #if SHIFT == 1 |
171 | 664e0f19 | bellard | d->Q(1) = 0; |
172 | 664e0f19 | bellard | #endif
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173 | 664e0f19 | bellard | } else {
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174 | 664e0f19 | bellard | shift = s->B(0);
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175 | 664e0f19 | bellard | d->Q(0) >>= shift;
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176 | 664e0f19 | bellard | #if SHIFT == 1 |
177 | 664e0f19 | bellard | d->Q(1) >>= shift;
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178 | 664e0f19 | bellard | #endif
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179 | 664e0f19 | bellard | } |
180 | 664e0f19 | bellard | } |
181 | 664e0f19 | bellard | |
182 | d3eb5eae | Blue Swirl | void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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183 | 664e0f19 | bellard | { |
184 | 664e0f19 | bellard | int shift;
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185 | 664e0f19 | bellard | |
186 | 664e0f19 | bellard | if (s->Q(0) > 63) { |
187 | 664e0f19 | bellard | d->Q(0) = 0; |
188 | 664e0f19 | bellard | #if SHIFT == 1 |
189 | 664e0f19 | bellard | d->Q(1) = 0; |
190 | 664e0f19 | bellard | #endif
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191 | 664e0f19 | bellard | } else {
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192 | 664e0f19 | bellard | shift = s->B(0);
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193 | 664e0f19 | bellard | d->Q(0) <<= shift;
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194 | 664e0f19 | bellard | #if SHIFT == 1 |
195 | 664e0f19 | bellard | d->Q(1) <<= shift;
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196 | 664e0f19 | bellard | #endif
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197 | 664e0f19 | bellard | } |
198 | 664e0f19 | bellard | } |
199 | 664e0f19 | bellard | |
200 | 664e0f19 | bellard | #if SHIFT == 1 |
201 | d3eb5eae | Blue Swirl | void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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202 | 664e0f19 | bellard | { |
203 | 664e0f19 | bellard | int shift, i;
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204 | 664e0f19 | bellard | |
205 | 664e0f19 | bellard | shift = s->L(0);
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206 | e01d9d31 | Blue Swirl | if (shift > 16) { |
207 | 664e0f19 | bellard | shift = 16;
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208 | e01d9d31 | Blue Swirl | } |
209 | e01d9d31 | Blue Swirl | for (i = 0; i < 16 - shift; i++) { |
210 | 664e0f19 | bellard | d->B(i) = d->B(i + shift); |
211 | e01d9d31 | Blue Swirl | } |
212 | e01d9d31 | Blue Swirl | for (i = 16 - shift; i < 16; i++) { |
213 | 664e0f19 | bellard | d->B(i) = 0;
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214 | e01d9d31 | Blue Swirl | } |
215 | 664e0f19 | bellard | } |
216 | 664e0f19 | bellard | |
217 | d3eb5eae | Blue Swirl | void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
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218 | 664e0f19 | bellard | { |
219 | 664e0f19 | bellard | int shift, i;
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220 | 664e0f19 | bellard | |
221 | 664e0f19 | bellard | shift = s->L(0);
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222 | e01d9d31 | Blue Swirl | if (shift > 16) { |
223 | 664e0f19 | bellard | shift = 16;
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224 | e01d9d31 | Blue Swirl | } |
225 | e01d9d31 | Blue Swirl | for (i = 15; i >= shift; i--) { |
226 | 664e0f19 | bellard | d->B(i) = d->B(i - shift); |
227 | e01d9d31 | Blue Swirl | } |
228 | e01d9d31 | Blue Swirl | for (i = 0; i < shift; i++) { |
229 | 664e0f19 | bellard | d->B(i) = 0;
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230 | e01d9d31 | Blue Swirl | } |
231 | 664e0f19 | bellard | } |
232 | 664e0f19 | bellard | #endif
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233 | 664e0f19 | bellard | |
234 | e01d9d31 | Blue Swirl | #define SSE_HELPER_B(name, F) \
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235 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
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236 | e01d9d31 | Blue Swirl | { \ |
237 | e01d9d31 | Blue Swirl | d->B(0) = F(d->B(0), s->B(0)); \ |
238 | e01d9d31 | Blue Swirl | d->B(1) = F(d->B(1), s->B(1)); \ |
239 | e01d9d31 | Blue Swirl | d->B(2) = F(d->B(2), s->B(2)); \ |
240 | e01d9d31 | Blue Swirl | d->B(3) = F(d->B(3), s->B(3)); \ |
241 | e01d9d31 | Blue Swirl | d->B(4) = F(d->B(4), s->B(4)); \ |
242 | e01d9d31 | Blue Swirl | d->B(5) = F(d->B(5), s->B(5)); \ |
243 | e01d9d31 | Blue Swirl | d->B(6) = F(d->B(6), s->B(6)); \ |
244 | e01d9d31 | Blue Swirl | d->B(7) = F(d->B(7), s->B(7)); \ |
245 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
246 | e01d9d31 | Blue Swirl | d->B(8) = F(d->B(8), s->B(8)); \ |
247 | e01d9d31 | Blue Swirl | d->B(9) = F(d->B(9), s->B(9)); \ |
248 | e01d9d31 | Blue Swirl | d->B(10) = F(d->B(10), s->B(10)); \ |
249 | e01d9d31 | Blue Swirl | d->B(11) = F(d->B(11), s->B(11)); \ |
250 | e01d9d31 | Blue Swirl | d->B(12) = F(d->B(12), s->B(12)); \ |
251 | e01d9d31 | Blue Swirl | d->B(13) = F(d->B(13), s->B(13)); \ |
252 | e01d9d31 | Blue Swirl | d->B(14) = F(d->B(14), s->B(14)); \ |
253 | e01d9d31 | Blue Swirl | d->B(15) = F(d->B(15), s->B(15)); \ |
254 | e01d9d31 | Blue Swirl | ) \ |
255 | e01d9d31 | Blue Swirl | } |
256 | e01d9d31 | Blue Swirl | |
257 | e01d9d31 | Blue Swirl | #define SSE_HELPER_W(name, F) \
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258 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
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259 | e01d9d31 | Blue Swirl | { \ |
260 | e01d9d31 | Blue Swirl | d->W(0) = F(d->W(0), s->W(0)); \ |
261 | e01d9d31 | Blue Swirl | d->W(1) = F(d->W(1), s->W(1)); \ |
262 | e01d9d31 | Blue Swirl | d->W(2) = F(d->W(2), s->W(2)); \ |
263 | e01d9d31 | Blue Swirl | d->W(3) = F(d->W(3), s->W(3)); \ |
264 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
265 | e01d9d31 | Blue Swirl | d->W(4) = F(d->W(4), s->W(4)); \ |
266 | e01d9d31 | Blue Swirl | d->W(5) = F(d->W(5), s->W(5)); \ |
267 | e01d9d31 | Blue Swirl | d->W(6) = F(d->W(6), s->W(6)); \ |
268 | e01d9d31 | Blue Swirl | d->W(7) = F(d->W(7), s->W(7)); \ |
269 | e01d9d31 | Blue Swirl | ) \ |
270 | e01d9d31 | Blue Swirl | } |
271 | e01d9d31 | Blue Swirl | |
272 | e01d9d31 | Blue Swirl | #define SSE_HELPER_L(name, F) \
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273 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
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274 | e01d9d31 | Blue Swirl | { \ |
275 | e01d9d31 | Blue Swirl | d->L(0) = F(d->L(0), s->L(0)); \ |
276 | e01d9d31 | Blue Swirl | d->L(1) = F(d->L(1), s->L(1)); \ |
277 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
278 | e01d9d31 | Blue Swirl | d->L(2) = F(d->L(2), s->L(2)); \ |
279 | e01d9d31 | Blue Swirl | d->L(3) = F(d->L(3), s->L(3)); \ |
280 | e01d9d31 | Blue Swirl | ) \ |
281 | e01d9d31 | Blue Swirl | } |
282 | e01d9d31 | Blue Swirl | |
283 | e01d9d31 | Blue Swirl | #define SSE_HELPER_Q(name, F) \
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284 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
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285 | e01d9d31 | Blue Swirl | { \ |
286 | e01d9d31 | Blue Swirl | d->Q(0) = F(d->Q(0), s->Q(0)); \ |
287 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
288 | e01d9d31 | Blue Swirl | d->Q(1) = F(d->Q(1), s->Q(1)); \ |
289 | e01d9d31 | Blue Swirl | ) \ |
290 | e01d9d31 | Blue Swirl | } |
291 | 664e0f19 | bellard | |
292 | 664e0f19 | bellard | #if SHIFT == 0 |
293 | 664e0f19 | bellard | static inline int satub(int x) |
294 | 664e0f19 | bellard | { |
295 | e01d9d31 | Blue Swirl | if (x < 0) { |
296 | 664e0f19 | bellard | return 0; |
297 | e01d9d31 | Blue Swirl | } else if (x > 255) { |
298 | 664e0f19 | bellard | return 255; |
299 | e01d9d31 | Blue Swirl | } else {
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300 | 664e0f19 | bellard | return x;
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301 | e01d9d31 | Blue Swirl | } |
302 | 664e0f19 | bellard | } |
303 | 664e0f19 | bellard | |
304 | 664e0f19 | bellard | static inline int satuw(int x) |
305 | 664e0f19 | bellard | { |
306 | e01d9d31 | Blue Swirl | if (x < 0) { |
307 | 664e0f19 | bellard | return 0; |
308 | e01d9d31 | Blue Swirl | } else if (x > 65535) { |
309 | 664e0f19 | bellard | return 65535; |
310 | e01d9d31 | Blue Swirl | } else {
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311 | 664e0f19 | bellard | return x;
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312 | e01d9d31 | Blue Swirl | } |
313 | 664e0f19 | bellard | } |
314 | 664e0f19 | bellard | |
315 | 664e0f19 | bellard | static inline int satsb(int x) |
316 | 664e0f19 | bellard | { |
317 | e01d9d31 | Blue Swirl | if (x < -128) { |
318 | 664e0f19 | bellard | return -128; |
319 | e01d9d31 | Blue Swirl | } else if (x > 127) { |
320 | 664e0f19 | bellard | return 127; |
321 | e01d9d31 | Blue Swirl | } else {
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322 | 664e0f19 | bellard | return x;
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323 | e01d9d31 | Blue Swirl | } |
324 | 664e0f19 | bellard | } |
325 | 664e0f19 | bellard | |
326 | 664e0f19 | bellard | static inline int satsw(int x) |
327 | 664e0f19 | bellard | { |
328 | e01d9d31 | Blue Swirl | if (x < -32768) { |
329 | 664e0f19 | bellard | return -32768; |
330 | e01d9d31 | Blue Swirl | } else if (x > 32767) { |
331 | 664e0f19 | bellard | return 32767; |
332 | e01d9d31 | Blue Swirl | } else {
|
333 | 664e0f19 | bellard | return x;
|
334 | e01d9d31 | Blue Swirl | } |
335 | 664e0f19 | bellard | } |
336 | 664e0f19 | bellard | |
337 | 664e0f19 | bellard | #define FADD(a, b) ((a) + (b))
|
338 | 664e0f19 | bellard | #define FADDUB(a, b) satub((a) + (b))
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339 | 664e0f19 | bellard | #define FADDUW(a, b) satuw((a) + (b))
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340 | 664e0f19 | bellard | #define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
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341 | 664e0f19 | bellard | #define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
|
342 | 664e0f19 | bellard | |
343 | 664e0f19 | bellard | #define FSUB(a, b) ((a) - (b))
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344 | 664e0f19 | bellard | #define FSUBUB(a, b) satub((a) - (b))
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345 | 664e0f19 | bellard | #define FSUBUW(a, b) satuw((a) - (b))
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346 | 664e0f19 | bellard | #define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
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347 | 664e0f19 | bellard | #define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
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348 | 664e0f19 | bellard | #define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
|
349 | 664e0f19 | bellard | #define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
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350 | 664e0f19 | bellard | #define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
|
351 | 664e0f19 | bellard | #define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
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352 | 664e0f19 | bellard | |
353 | e01d9d31 | Blue Swirl | #define FAND(a, b) ((a) & (b))
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354 | 664e0f19 | bellard | #define FANDN(a, b) ((~(a)) & (b))
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355 | e01d9d31 | Blue Swirl | #define FOR(a, b) ((a) | (b))
|
356 | e01d9d31 | Blue Swirl | #define FXOR(a, b) ((a) ^ (b))
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357 | 664e0f19 | bellard | |
358 | e01d9d31 | Blue Swirl | #define FCMPGTB(a, b) ((int8_t)(a) > (int8_t)(b) ? -1 : 0) |
359 | e01d9d31 | Blue Swirl | #define FCMPGTW(a, b) ((int16_t)(a) > (int16_t)(b) ? -1 : 0) |
360 | e01d9d31 | Blue Swirl | #define FCMPGTL(a, b) ((int32_t)(a) > (int32_t)(b) ? -1 : 0) |
361 | e01d9d31 | Blue Swirl | #define FCMPEQ(a, b) ((a) == (b) ? -1 : 0) |
362 | 664e0f19 | bellard | |
363 | e01d9d31 | Blue Swirl | #define FMULLW(a, b) ((a) * (b))
|
364 | e01d9d31 | Blue Swirl | #define FMULHRW(a, b) (((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16) |
365 | e01d9d31 | Blue Swirl | #define FMULHUW(a, b) ((a) * (b) >> 16) |
366 | e01d9d31 | Blue Swirl | #define FMULHW(a, b) ((int16_t)(a) * (int16_t)(b) >> 16) |
367 | 664e0f19 | bellard | |
368 | e01d9d31 | Blue Swirl | #define FAVG(a, b) (((a) + (b) + 1) >> 1) |
369 | 664e0f19 | bellard | #endif
|
370 | 664e0f19 | bellard | |
371 | 5af45186 | bellard | SSE_HELPER_B(helper_paddb, FADD) |
372 | 5af45186 | bellard | SSE_HELPER_W(helper_paddw, FADD) |
373 | 5af45186 | bellard | SSE_HELPER_L(helper_paddl, FADD) |
374 | 5af45186 | bellard | SSE_HELPER_Q(helper_paddq, FADD) |
375 | 664e0f19 | bellard | |
376 | 5af45186 | bellard | SSE_HELPER_B(helper_psubb, FSUB) |
377 | 5af45186 | bellard | SSE_HELPER_W(helper_psubw, FSUB) |
378 | 5af45186 | bellard | SSE_HELPER_L(helper_psubl, FSUB) |
379 | 5af45186 | bellard | SSE_HELPER_Q(helper_psubq, FSUB) |
380 | 664e0f19 | bellard | |
381 | 5af45186 | bellard | SSE_HELPER_B(helper_paddusb, FADDUB) |
382 | 5af45186 | bellard | SSE_HELPER_B(helper_paddsb, FADDSB) |
383 | 5af45186 | bellard | SSE_HELPER_B(helper_psubusb, FSUBUB) |
384 | 5af45186 | bellard | SSE_HELPER_B(helper_psubsb, FSUBSB) |
385 | 664e0f19 | bellard | |
386 | 5af45186 | bellard | SSE_HELPER_W(helper_paddusw, FADDUW) |
387 | 5af45186 | bellard | SSE_HELPER_W(helper_paddsw, FADDSW) |
388 | 5af45186 | bellard | SSE_HELPER_W(helper_psubusw, FSUBUW) |
389 | 5af45186 | bellard | SSE_HELPER_W(helper_psubsw, FSUBSW) |
390 | 664e0f19 | bellard | |
391 | 5af45186 | bellard | SSE_HELPER_B(helper_pminub, FMINUB) |
392 | 5af45186 | bellard | SSE_HELPER_B(helper_pmaxub, FMAXUB) |
393 | 664e0f19 | bellard | |
394 | 5af45186 | bellard | SSE_HELPER_W(helper_pminsw, FMINSW) |
395 | 5af45186 | bellard | SSE_HELPER_W(helper_pmaxsw, FMAXSW) |
396 | 664e0f19 | bellard | |
397 | 5af45186 | bellard | SSE_HELPER_Q(helper_pand, FAND) |
398 | 5af45186 | bellard | SSE_HELPER_Q(helper_pandn, FANDN) |
399 | 5af45186 | bellard | SSE_HELPER_Q(helper_por, FOR) |
400 | 5af45186 | bellard | SSE_HELPER_Q(helper_pxor, FXOR) |
401 | 664e0f19 | bellard | |
402 | 5af45186 | bellard | SSE_HELPER_B(helper_pcmpgtb, FCMPGTB) |
403 | 5af45186 | bellard | SSE_HELPER_W(helper_pcmpgtw, FCMPGTW) |
404 | 5af45186 | bellard | SSE_HELPER_L(helper_pcmpgtl, FCMPGTL) |
405 | 664e0f19 | bellard | |
406 | 5af45186 | bellard | SSE_HELPER_B(helper_pcmpeqb, FCMPEQ) |
407 | 5af45186 | bellard | SSE_HELPER_W(helper_pcmpeqw, FCMPEQ) |
408 | 5af45186 | bellard | SSE_HELPER_L(helper_pcmpeql, FCMPEQ) |
409 | 664e0f19 | bellard | |
410 | 5af45186 | bellard | SSE_HELPER_W(helper_pmullw, FMULLW) |
411 | a35f3ec7 | aurel32 | #if SHIFT == 0 |
412 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhrw, FMULHRW) |
413 | a35f3ec7 | aurel32 | #endif
|
414 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhuw, FMULHUW) |
415 | 5af45186 | bellard | SSE_HELPER_W(helper_pmulhw, FMULHW) |
416 | 664e0f19 | bellard | |
417 | 5af45186 | bellard | SSE_HELPER_B(helper_pavgb, FAVG) |
418 | 5af45186 | bellard | SSE_HELPER_W(helper_pavgw, FAVG) |
419 | 664e0f19 | bellard | |
420 | d3eb5eae | Blue Swirl | void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
421 | 664e0f19 | bellard | { |
422 | 664e0f19 | bellard | d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0); |
423 | 664e0f19 | bellard | #if SHIFT == 1 |
424 | 664e0f19 | bellard | d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2); |
425 | 664e0f19 | bellard | #endif
|
426 | 664e0f19 | bellard | } |
427 | 664e0f19 | bellard | |
428 | d3eb5eae | Blue Swirl | void glue(helper_pmaddwd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
429 | 664e0f19 | bellard | { |
430 | 664e0f19 | bellard | int i;
|
431 | 664e0f19 | bellard | |
432 | e01d9d31 | Blue Swirl | for (i = 0; i < (2 << SHIFT); i++) { |
433 | e01d9d31 | Blue Swirl | d->L(i) = (int16_t)s->W(2 * i) * (int16_t)d->W(2 * i) + |
434 | e01d9d31 | Blue Swirl | (int16_t)s->W(2 * i + 1) * (int16_t)d->W(2 * i + 1); |
435 | 664e0f19 | bellard | } |
436 | 664e0f19 | bellard | } |
437 | 664e0f19 | bellard | |
438 | 664e0f19 | bellard | #if SHIFT == 0 |
439 | 664e0f19 | bellard | static inline int abs1(int a) |
440 | 664e0f19 | bellard | { |
441 | e01d9d31 | Blue Swirl | if (a < 0) { |
442 | 664e0f19 | bellard | return -a;
|
443 | e01d9d31 | Blue Swirl | } else {
|
444 | 664e0f19 | bellard | return a;
|
445 | e01d9d31 | Blue Swirl | } |
446 | 664e0f19 | bellard | } |
447 | 664e0f19 | bellard | #endif
|
448 | d3eb5eae | Blue Swirl | void glue(helper_psadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
449 | 664e0f19 | bellard | { |
450 | 664e0f19 | bellard | unsigned int val; |
451 | 664e0f19 | bellard | |
452 | 664e0f19 | bellard | val = 0;
|
453 | 664e0f19 | bellard | val += abs1(d->B(0) - s->B(0)); |
454 | 664e0f19 | bellard | val += abs1(d->B(1) - s->B(1)); |
455 | 664e0f19 | bellard | val += abs1(d->B(2) - s->B(2)); |
456 | 664e0f19 | bellard | val += abs1(d->B(3) - s->B(3)); |
457 | 664e0f19 | bellard | val += abs1(d->B(4) - s->B(4)); |
458 | 664e0f19 | bellard | val += abs1(d->B(5) - s->B(5)); |
459 | 664e0f19 | bellard | val += abs1(d->B(6) - s->B(6)); |
460 | 664e0f19 | bellard | val += abs1(d->B(7) - s->B(7)); |
461 | 664e0f19 | bellard | d->Q(0) = val;
|
462 | 664e0f19 | bellard | #if SHIFT == 1 |
463 | 664e0f19 | bellard | val = 0;
|
464 | 664e0f19 | bellard | val += abs1(d->B(8) - s->B(8)); |
465 | 664e0f19 | bellard | val += abs1(d->B(9) - s->B(9)); |
466 | 664e0f19 | bellard | val += abs1(d->B(10) - s->B(10)); |
467 | 664e0f19 | bellard | val += abs1(d->B(11) - s->B(11)); |
468 | 664e0f19 | bellard | val += abs1(d->B(12) - s->B(12)); |
469 | 664e0f19 | bellard | val += abs1(d->B(13) - s->B(13)); |
470 | 664e0f19 | bellard | val += abs1(d->B(14) - s->B(14)); |
471 | 664e0f19 | bellard | val += abs1(d->B(15) - s->B(15)); |
472 | 664e0f19 | bellard | d->Q(1) = val;
|
473 | 664e0f19 | bellard | #endif
|
474 | 664e0f19 | bellard | } |
475 | 664e0f19 | bellard | |
476 | d3eb5eae | Blue Swirl | void glue(helper_maskmov, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
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477 | d3eb5eae | Blue Swirl | target_ulong a0) |
478 | 664e0f19 | bellard | { |
479 | 664e0f19 | bellard | int i;
|
480 | e01d9d31 | Blue Swirl | |
481 | e01d9d31 | Blue Swirl | for (i = 0; i < (8 << SHIFT); i++) { |
482 | e01d9d31 | Blue Swirl | if (s->B(i) & 0x80) { |
483 | d3eb5eae | Blue Swirl | cpu_stb_data(env, a0 + i, d->B(i)); |
484 | e01d9d31 | Blue Swirl | } |
485 | 664e0f19 | bellard | } |
486 | 664e0f19 | bellard | } |
487 | 664e0f19 | bellard | |
488 | e01d9d31 | Blue Swirl | void glue(helper_movl_mm_T0, SUFFIX)(Reg *d, uint32_t val)
|
489 | 664e0f19 | bellard | { |
490 | 5af45186 | bellard | d->L(0) = val;
|
491 | 664e0f19 | bellard | d->L(1) = 0; |
492 | 664e0f19 | bellard | #if SHIFT == 1 |
493 | 664e0f19 | bellard | d->Q(1) = 0; |
494 | 664e0f19 | bellard | #endif
|
495 | 664e0f19 | bellard | } |
496 | 664e0f19 | bellard | |
497 | dabd98dd | bellard | #ifdef TARGET_X86_64
|
498 | e01d9d31 | Blue Swirl | void glue(helper_movq_mm_T0, SUFFIX)(Reg *d, uint64_t val)
|
499 | dabd98dd | bellard | { |
500 | 5af45186 | bellard | d->Q(0) = val;
|
501 | dabd98dd | bellard | #if SHIFT == 1 |
502 | dabd98dd | bellard | d->Q(1) = 0; |
503 | dabd98dd | bellard | #endif
|
504 | dabd98dd | bellard | } |
505 | dabd98dd | bellard | #endif
|
506 | dabd98dd | bellard | |
507 | 664e0f19 | bellard | #if SHIFT == 0 |
508 | e01d9d31 | Blue Swirl | void glue(helper_pshufw, SUFFIX)(Reg *d, Reg *s, int order) |
509 | 664e0f19 | bellard | { |
510 | 5af45186 | bellard | Reg r; |
511 | e01d9d31 | Blue Swirl | |
512 | 664e0f19 | bellard | r.W(0) = s->W(order & 3); |
513 | 664e0f19 | bellard | r.W(1) = s->W((order >> 2) & 3); |
514 | 664e0f19 | bellard | r.W(2) = s->W((order >> 4) & 3); |
515 | 664e0f19 | bellard | r.W(3) = s->W((order >> 6) & 3); |
516 | 664e0f19 | bellard | *d = r; |
517 | 664e0f19 | bellard | } |
518 | 664e0f19 | bellard | #else
|
519 | 5af45186 | bellard | void helper_shufps(Reg *d, Reg *s, int order) |
520 | d52cf7a6 | bellard | { |
521 | 5af45186 | bellard | Reg r; |
522 | e01d9d31 | Blue Swirl | |
523 | d52cf7a6 | bellard | r.L(0) = d->L(order & 3); |
524 | d52cf7a6 | bellard | r.L(1) = d->L((order >> 2) & 3); |
525 | d52cf7a6 | bellard | r.L(2) = s->L((order >> 4) & 3); |
526 | d52cf7a6 | bellard | r.L(3) = s->L((order >> 6) & 3); |
527 | d52cf7a6 | bellard | *d = r; |
528 | d52cf7a6 | bellard | } |
529 | d52cf7a6 | bellard | |
530 | 5af45186 | bellard | void helper_shufpd(Reg *d, Reg *s, int order) |
531 | 664e0f19 | bellard | { |
532 | 5af45186 | bellard | Reg r; |
533 | e01d9d31 | Blue Swirl | |
534 | d52cf7a6 | bellard | r.Q(0) = d->Q(order & 1); |
535 | 664e0f19 | bellard | r.Q(1) = s->Q((order >> 1) & 1); |
536 | 664e0f19 | bellard | *d = r; |
537 | 664e0f19 | bellard | } |
538 | 664e0f19 | bellard | |
539 | e01d9d31 | Blue Swirl | void glue(helper_pshufd, SUFFIX)(Reg *d, Reg *s, int order) |
540 | 664e0f19 | bellard | { |
541 | 5af45186 | bellard | Reg r; |
542 | e01d9d31 | Blue Swirl | |
543 | 664e0f19 | bellard | r.L(0) = s->L(order & 3); |
544 | 664e0f19 | bellard | r.L(1) = s->L((order >> 2) & 3); |
545 | 664e0f19 | bellard | r.L(2) = s->L((order >> 4) & 3); |
546 | 664e0f19 | bellard | r.L(3) = s->L((order >> 6) & 3); |
547 | 664e0f19 | bellard | *d = r; |
548 | 664e0f19 | bellard | } |
549 | 664e0f19 | bellard | |
550 | e01d9d31 | Blue Swirl | void glue(helper_pshuflw, SUFFIX)(Reg *d, Reg *s, int order) |
551 | 664e0f19 | bellard | { |
552 | 5af45186 | bellard | Reg r; |
553 | e01d9d31 | Blue Swirl | |
554 | 664e0f19 | bellard | r.W(0) = s->W(order & 3); |
555 | 664e0f19 | bellard | r.W(1) = s->W((order >> 2) & 3); |
556 | 664e0f19 | bellard | r.W(2) = s->W((order >> 4) & 3); |
557 | 664e0f19 | bellard | r.W(3) = s->W((order >> 6) & 3); |
558 | 664e0f19 | bellard | r.Q(1) = s->Q(1); |
559 | 664e0f19 | bellard | *d = r; |
560 | 664e0f19 | bellard | } |
561 | 664e0f19 | bellard | |
562 | e01d9d31 | Blue Swirl | void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order) |
563 | 664e0f19 | bellard | { |
564 | 5af45186 | bellard | Reg r; |
565 | e01d9d31 | Blue Swirl | |
566 | 664e0f19 | bellard | r.Q(0) = s->Q(0); |
567 | 664e0f19 | bellard | r.W(4) = s->W(4 + (order & 3)); |
568 | 664e0f19 | bellard | r.W(5) = s->W(4 + ((order >> 2) & 3)); |
569 | 664e0f19 | bellard | r.W(6) = s->W(4 + ((order >> 4) & 3)); |
570 | 664e0f19 | bellard | r.W(7) = s->W(4 + ((order >> 6) & 3)); |
571 | 664e0f19 | bellard | *d = r; |
572 | 664e0f19 | bellard | } |
573 | 664e0f19 | bellard | #endif
|
574 | 664e0f19 | bellard | |
575 | 664e0f19 | bellard | #if SHIFT == 1 |
576 | 664e0f19 | bellard | /* FPU ops */
|
577 | 664e0f19 | bellard | /* XXX: not accurate */
|
578 | 664e0f19 | bellard | |
579 | d3eb5eae | Blue Swirl | #define SSE_HELPER_S(name, F) \
|
580 | d3eb5eae | Blue Swirl | void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ |
581 | d3eb5eae | Blue Swirl | { \ |
582 | d3eb5eae | Blue Swirl | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
583 | d3eb5eae | Blue Swirl | d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ |
584 | d3eb5eae | Blue Swirl | d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ |
585 | d3eb5eae | Blue Swirl | d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ |
586 | d3eb5eae | Blue Swirl | } \ |
587 | d3eb5eae | Blue Swirl | \ |
588 | d3eb5eae | Blue Swirl | void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ |
589 | d3eb5eae | Blue Swirl | { \ |
590 | d3eb5eae | Blue Swirl | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
591 | d3eb5eae | Blue Swirl | } \ |
592 | d3eb5eae | Blue Swirl | \ |
593 | d3eb5eae | Blue Swirl | void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ |
594 | d3eb5eae | Blue Swirl | { \ |
595 | d3eb5eae | Blue Swirl | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
596 | d3eb5eae | Blue Swirl | d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ |
597 | d3eb5eae | Blue Swirl | } \ |
598 | d3eb5eae | Blue Swirl | \ |
599 | d3eb5eae | Blue Swirl | void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ |
600 | d3eb5eae | Blue Swirl | { \ |
601 | d3eb5eae | Blue Swirl | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
602 | e01d9d31 | Blue Swirl | } |
603 | 664e0f19 | bellard | |
604 | 7a0e1f41 | bellard | #define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status) |
605 | 7a0e1f41 | bellard | #define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status) |
606 | 7a0e1f41 | bellard | #define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status) |
607 | 7a0e1f41 | bellard | #define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status) |
608 | 7a0e1f41 | bellard | #define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status) |
609 | 664e0f19 | bellard | |
610 | a4d1f142 | Aurelien Jarno | /* Note that the choice of comparison op here is important to get the
|
611 | a4d1f142 | Aurelien Jarno | * special cases right: for min and max Intel specifies that (-0,0),
|
612 | a4d1f142 | Aurelien Jarno | * (NaN, anything) and (anything, NaN) return the second argument.
|
613 | a4d1f142 | Aurelien Jarno | */
|
614 | e01d9d31 | Blue Swirl | #define FPU_MIN(size, a, b) \
|
615 | e01d9d31 | Blue Swirl | (float ## size ## _lt(a, b, &env->sse_status) ? (a) : (b)) |
616 | e01d9d31 | Blue Swirl | #define FPU_MAX(size, a, b) \
|
617 | e01d9d31 | Blue Swirl | (float ## size ## _lt(b, a, &env->sse_status) ? (a) : (b)) |
618 | a4d1f142 | Aurelien Jarno | |
619 | 5af45186 | bellard | SSE_HELPER_S(add, FPU_ADD) |
620 | 5af45186 | bellard | SSE_HELPER_S(sub, FPU_SUB) |
621 | 5af45186 | bellard | SSE_HELPER_S(mul, FPU_MUL) |
622 | 5af45186 | bellard | SSE_HELPER_S(div, FPU_DIV) |
623 | 5af45186 | bellard | SSE_HELPER_S(min, FPU_MIN) |
624 | 5af45186 | bellard | SSE_HELPER_S(max, FPU_MAX) |
625 | 5af45186 | bellard | SSE_HELPER_S(sqrt, FPU_SQRT) |
626 | 664e0f19 | bellard | |
627 | 664e0f19 | bellard | |
628 | 664e0f19 | bellard | /* float to float conversions */
|
629 | d3eb5eae | Blue Swirl | void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s)
|
630 | 664e0f19 | bellard | { |
631 | 8422b113 | bellard | float32 s0, s1; |
632 | e01d9d31 | Blue Swirl | |
633 | 664e0f19 | bellard | s0 = s->XMM_S(0);
|
634 | 664e0f19 | bellard | s1 = s->XMM_S(1);
|
635 | 7a0e1f41 | bellard | d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
|
636 | 7a0e1f41 | bellard | d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
|
637 | 664e0f19 | bellard | } |
638 | 664e0f19 | bellard | |
639 | d3eb5eae | Blue Swirl | void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s)
|
640 | 664e0f19 | bellard | { |
641 | 7a0e1f41 | bellard | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
642 | 7a0e1f41 | bellard | d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status); |
643 | 664e0f19 | bellard | d->Q(1) = 0; |
644 | 664e0f19 | bellard | } |
645 | 664e0f19 | bellard | |
646 | d3eb5eae | Blue Swirl | void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
|
647 | 664e0f19 | bellard | { |
648 | 7a0e1f41 | bellard | d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status); |
649 | 664e0f19 | bellard | } |
650 | 664e0f19 | bellard | |
651 | d3eb5eae | Blue Swirl | void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
|
652 | 664e0f19 | bellard | { |
653 | 7a0e1f41 | bellard | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
654 | 664e0f19 | bellard | } |
655 | 664e0f19 | bellard | |
656 | 664e0f19 | bellard | /* integer to float */
|
657 | d3eb5eae | Blue Swirl | void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s)
|
658 | 664e0f19 | bellard | { |
659 | 7a0e1f41 | bellard | d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status); |
660 | 7a0e1f41 | bellard | d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status); |
661 | 7a0e1f41 | bellard | d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status); |
662 | 7a0e1f41 | bellard | d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status); |
663 | 664e0f19 | bellard | } |
664 | 664e0f19 | bellard | |
665 | d3eb5eae | Blue Swirl | void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s)
|
666 | 664e0f19 | bellard | { |
667 | 664e0f19 | bellard | int32_t l0, l1; |
668 | e01d9d31 | Blue Swirl | |
669 | 664e0f19 | bellard | l0 = (int32_t)s->XMM_L(0);
|
670 | 664e0f19 | bellard | l1 = (int32_t)s->XMM_L(1);
|
671 | 7a0e1f41 | bellard | d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
|
672 | 7a0e1f41 | bellard | d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
|
673 | 664e0f19 | bellard | } |
674 | 664e0f19 | bellard | |
675 | d3eb5eae | Blue Swirl | void helper_cvtpi2ps(CPUX86State *env, XMMReg *d, MMXReg *s)
|
676 | 664e0f19 | bellard | { |
677 | 7a0e1f41 | bellard | d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); |
678 | 7a0e1f41 | bellard | d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); |
679 | 664e0f19 | bellard | } |
680 | 664e0f19 | bellard | |
681 | d3eb5eae | Blue Swirl | void helper_cvtpi2pd(CPUX86State *env, XMMReg *d, MMXReg *s)
|
682 | 664e0f19 | bellard | { |
683 | 7a0e1f41 | bellard | d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); |
684 | 7a0e1f41 | bellard | d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); |
685 | 664e0f19 | bellard | } |
686 | 664e0f19 | bellard | |
687 | d3eb5eae | Blue Swirl | void helper_cvtsi2ss(CPUX86State *env, XMMReg *d, uint32_t val)
|
688 | 664e0f19 | bellard | { |
689 | 5af45186 | bellard | d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
|
690 | 664e0f19 | bellard | } |
691 | 664e0f19 | bellard | |
692 | d3eb5eae | Blue Swirl | void helper_cvtsi2sd(CPUX86State *env, XMMReg *d, uint32_t val)
|
693 | 664e0f19 | bellard | { |
694 | 5af45186 | bellard | d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
|
695 | 664e0f19 | bellard | } |
696 | 664e0f19 | bellard | |
697 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
698 | d3eb5eae | Blue Swirl | void helper_cvtsq2ss(CPUX86State *env, XMMReg *d, uint64_t val)
|
699 | 664e0f19 | bellard | { |
700 | 5af45186 | bellard | d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
|
701 | 664e0f19 | bellard | } |
702 | 664e0f19 | bellard | |
703 | d3eb5eae | Blue Swirl | void helper_cvtsq2sd(CPUX86State *env, XMMReg *d, uint64_t val)
|
704 | 664e0f19 | bellard | { |
705 | 5af45186 | bellard | d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
|
706 | 664e0f19 | bellard | } |
707 | 664e0f19 | bellard | #endif
|
708 | 664e0f19 | bellard | |
709 | 664e0f19 | bellard | /* float to integer */
|
710 | d3eb5eae | Blue Swirl | void helper_cvtps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
|
711 | 664e0f19 | bellard | { |
712 | 7a0e1f41 | bellard | d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
713 | 7a0e1f41 | bellard | d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
714 | 7a0e1f41 | bellard | d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status); |
715 | 7a0e1f41 | bellard | d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); |
716 | 664e0f19 | bellard | } |
717 | 664e0f19 | bellard | |
718 | d3eb5eae | Blue Swirl | void helper_cvtpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
|
719 | 664e0f19 | bellard | { |
720 | 7a0e1f41 | bellard | d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
721 | 7a0e1f41 | bellard | d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
722 | 664e0f19 | bellard | d->XMM_Q(1) = 0; |
723 | 664e0f19 | bellard | } |
724 | 664e0f19 | bellard | |
725 | d3eb5eae | Blue Swirl | void helper_cvtps2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
|
726 | 664e0f19 | bellard | { |
727 | 7a0e1f41 | bellard | d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
728 | 7a0e1f41 | bellard | d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
729 | 664e0f19 | bellard | } |
730 | 664e0f19 | bellard | |
731 | d3eb5eae | Blue Swirl | void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
|
732 | 664e0f19 | bellard | { |
733 | 7a0e1f41 | bellard | d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
734 | 7a0e1f41 | bellard | d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
735 | 664e0f19 | bellard | } |
736 | 664e0f19 | bellard | |
737 | d3eb5eae | Blue Swirl | int32_t helper_cvtss2si(CPUX86State *env, XMMReg *s) |
738 | 664e0f19 | bellard | { |
739 | 5af45186 | bellard | return float32_to_int32(s->XMM_S(0), &env->sse_status); |
740 | 664e0f19 | bellard | } |
741 | 664e0f19 | bellard | |
742 | d3eb5eae | Blue Swirl | int32_t helper_cvtsd2si(CPUX86State *env, XMMReg *s) |
743 | 664e0f19 | bellard | { |
744 | 5af45186 | bellard | return float64_to_int32(s->XMM_D(0), &env->sse_status); |
745 | 664e0f19 | bellard | } |
746 | 664e0f19 | bellard | |
747 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
748 | d3eb5eae | Blue Swirl | int64_t helper_cvtss2sq(CPUX86State *env, XMMReg *s) |
749 | 664e0f19 | bellard | { |
750 | 5af45186 | bellard | return float32_to_int64(s->XMM_S(0), &env->sse_status); |
751 | 664e0f19 | bellard | } |
752 | 664e0f19 | bellard | |
753 | d3eb5eae | Blue Swirl | int64_t helper_cvtsd2sq(CPUX86State *env, XMMReg *s) |
754 | 664e0f19 | bellard | { |
755 | 5af45186 | bellard | return float64_to_int64(s->XMM_D(0), &env->sse_status); |
756 | 664e0f19 | bellard | } |
757 | 664e0f19 | bellard | #endif
|
758 | 664e0f19 | bellard | |
759 | 664e0f19 | bellard | /* float to integer truncated */
|
760 | d3eb5eae | Blue Swirl | void helper_cvttps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
|
761 | 664e0f19 | bellard | { |
762 | 7a0e1f41 | bellard | d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
763 | 7a0e1f41 | bellard | d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
764 | 7a0e1f41 | bellard | d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status); |
765 | 7a0e1f41 | bellard | d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); |
766 | 664e0f19 | bellard | } |
767 | 664e0f19 | bellard | |
768 | d3eb5eae | Blue Swirl | void helper_cvttpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
|
769 | 664e0f19 | bellard | { |
770 | 7a0e1f41 | bellard | d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
771 | 7a0e1f41 | bellard | d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
772 | 664e0f19 | bellard | d->XMM_Q(1) = 0; |
773 | 664e0f19 | bellard | } |
774 | 664e0f19 | bellard | |
775 | d3eb5eae | Blue Swirl | void helper_cvttps2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
|
776 | 664e0f19 | bellard | { |
777 | 7a0e1f41 | bellard | d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
778 | 7a0e1f41 | bellard | d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
779 | 664e0f19 | bellard | } |
780 | 664e0f19 | bellard | |
781 | d3eb5eae | Blue Swirl | void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
|
782 | 664e0f19 | bellard | { |
783 | 7a0e1f41 | bellard | d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
784 | 7a0e1f41 | bellard | d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
785 | 664e0f19 | bellard | } |
786 | 664e0f19 | bellard | |
787 | d3eb5eae | Blue Swirl | int32_t helper_cvttss2si(CPUX86State *env, XMMReg *s) |
788 | 664e0f19 | bellard | { |
789 | 5af45186 | bellard | return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
790 | 664e0f19 | bellard | } |
791 | 664e0f19 | bellard | |
792 | d3eb5eae | Blue Swirl | int32_t helper_cvttsd2si(CPUX86State *env, XMMReg *s) |
793 | 664e0f19 | bellard | { |
794 | 5af45186 | bellard | return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
795 | 664e0f19 | bellard | } |
796 | 664e0f19 | bellard | |
797 | 664e0f19 | bellard | #ifdef TARGET_X86_64
|
798 | d3eb5eae | Blue Swirl | int64_t helper_cvttss2sq(CPUX86State *env, XMMReg *s) |
799 | 664e0f19 | bellard | { |
800 | 5af45186 | bellard | return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); |
801 | 664e0f19 | bellard | } |
802 | 664e0f19 | bellard | |
803 | d3eb5eae | Blue Swirl | int64_t helper_cvttsd2sq(CPUX86State *env, XMMReg *s) |
804 | 664e0f19 | bellard | { |
805 | 5af45186 | bellard | return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); |
806 | 664e0f19 | bellard | } |
807 | 664e0f19 | bellard | #endif
|
808 | 664e0f19 | bellard | |
809 | d3eb5eae | Blue Swirl | void helper_rsqrtps(CPUX86State *env, XMMReg *d, XMMReg *s)
|
810 | 664e0f19 | bellard | { |
811 | c2ef9a83 | Aurelien Jarno | d->XMM_S(0) = float32_div(float32_one,
|
812 | c2ef9a83 | Aurelien Jarno | float32_sqrt(s->XMM_S(0), &env->sse_status),
|
813 | c2ef9a83 | Aurelien Jarno | &env->sse_status); |
814 | c2ef9a83 | Aurelien Jarno | d->XMM_S(1) = float32_div(float32_one,
|
815 | c2ef9a83 | Aurelien Jarno | float32_sqrt(s->XMM_S(1), &env->sse_status),
|
816 | c2ef9a83 | Aurelien Jarno | &env->sse_status); |
817 | c2ef9a83 | Aurelien Jarno | d->XMM_S(2) = float32_div(float32_one,
|
818 | c2ef9a83 | Aurelien Jarno | float32_sqrt(s->XMM_S(2), &env->sse_status),
|
819 | c2ef9a83 | Aurelien Jarno | &env->sse_status); |
820 | c2ef9a83 | Aurelien Jarno | d->XMM_S(3) = float32_div(float32_one,
|
821 | c2ef9a83 | Aurelien Jarno | float32_sqrt(s->XMM_S(3), &env->sse_status),
|
822 | c2ef9a83 | Aurelien Jarno | &env->sse_status); |
823 | 664e0f19 | bellard | } |
824 | 664e0f19 | bellard | |
825 | d3eb5eae | Blue Swirl | void helper_rsqrtss(CPUX86State *env, XMMReg *d, XMMReg *s)
|
826 | 664e0f19 | bellard | { |
827 | c2ef9a83 | Aurelien Jarno | d->XMM_S(0) = float32_div(float32_one,
|
828 | c2ef9a83 | Aurelien Jarno | float32_sqrt(s->XMM_S(0), &env->sse_status),
|
829 | c2ef9a83 | Aurelien Jarno | &env->sse_status); |
830 | 664e0f19 | bellard | } |
831 | 664e0f19 | bellard | |
832 | d3eb5eae | Blue Swirl | void helper_rcpps(CPUX86State *env, XMMReg *d, XMMReg *s)
|
833 | 664e0f19 | bellard | { |
834 | c2ef9a83 | Aurelien Jarno | d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); |
835 | c2ef9a83 | Aurelien Jarno | d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status); |
836 | c2ef9a83 | Aurelien Jarno | d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status); |
837 | c2ef9a83 | Aurelien Jarno | d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status); |
838 | 664e0f19 | bellard | } |
839 | 664e0f19 | bellard | |
840 | d3eb5eae | Blue Swirl | void helper_rcpss(CPUX86State *env, XMMReg *d, XMMReg *s)
|
841 | 664e0f19 | bellard | { |
842 | c2ef9a83 | Aurelien Jarno | d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); |
843 | 664e0f19 | bellard | } |
844 | 664e0f19 | bellard | |
845 | d9f4bb27 | Andre Przywara | static inline uint64_t helper_extrq(uint64_t src, int shift, int len) |
846 | d9f4bb27 | Andre Przywara | { |
847 | d9f4bb27 | Andre Przywara | uint64_t mask; |
848 | d9f4bb27 | Andre Przywara | |
849 | d9f4bb27 | Andre Przywara | if (len == 0) { |
850 | d9f4bb27 | Andre Przywara | mask = ~0LL;
|
851 | d9f4bb27 | Andre Przywara | } else {
|
852 | d9f4bb27 | Andre Przywara | mask = (1ULL << len) - 1; |
853 | d9f4bb27 | Andre Przywara | } |
854 | d9f4bb27 | Andre Przywara | return (src >> shift) & mask;
|
855 | d9f4bb27 | Andre Przywara | } |
856 | d9f4bb27 | Andre Przywara | |
857 | d3eb5eae | Blue Swirl | void helper_extrq_r(CPUX86State *env, XMMReg *d, XMMReg *s)
|
858 | d9f4bb27 | Andre Przywara | { |
859 | d9f4bb27 | Andre Przywara | d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0)); |
860 | d9f4bb27 | Andre Przywara | } |
861 | d9f4bb27 | Andre Przywara | |
862 | d3eb5eae | Blue Swirl | void helper_extrq_i(CPUX86State *env, XMMReg *d, int index, int length) |
863 | d9f4bb27 | Andre Przywara | { |
864 | d9f4bb27 | Andre Przywara | d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length); |
865 | d9f4bb27 | Andre Przywara | } |
866 | d9f4bb27 | Andre Przywara | |
867 | d9f4bb27 | Andre Przywara | static inline uint64_t helper_insertq(uint64_t src, int shift, int len) |
868 | d9f4bb27 | Andre Przywara | { |
869 | d9f4bb27 | Andre Przywara | uint64_t mask; |
870 | d9f4bb27 | Andre Przywara | |
871 | d9f4bb27 | Andre Przywara | if (len == 0) { |
872 | d9f4bb27 | Andre Przywara | mask = ~0ULL;
|
873 | d9f4bb27 | Andre Przywara | } else {
|
874 | d9f4bb27 | Andre Przywara | mask = (1ULL << len) - 1; |
875 | d9f4bb27 | Andre Przywara | } |
876 | d9f4bb27 | Andre Przywara | return (src & ~(mask << shift)) | ((src & mask) << shift);
|
877 | d9f4bb27 | Andre Przywara | } |
878 | d9f4bb27 | Andre Przywara | |
879 | d3eb5eae | Blue Swirl | void helper_insertq_r(CPUX86State *env, XMMReg *d, XMMReg *s)
|
880 | d9f4bb27 | Andre Przywara | { |
881 | d9f4bb27 | Andre Przywara | d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8)); |
882 | d9f4bb27 | Andre Przywara | } |
883 | d9f4bb27 | Andre Przywara | |
884 | d3eb5eae | Blue Swirl | void helper_insertq_i(CPUX86State *env, XMMReg *d, int index, int length) |
885 | d9f4bb27 | Andre Przywara | { |
886 | d9f4bb27 | Andre Przywara | d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length); |
887 | d9f4bb27 | Andre Przywara | } |
888 | d9f4bb27 | Andre Przywara | |
889 | d3eb5eae | Blue Swirl | void helper_haddps(CPUX86State *env, XMMReg *d, XMMReg *s)
|
890 | 664e0f19 | bellard | { |
891 | 664e0f19 | bellard | XMMReg r; |
892 | e01d9d31 | Blue Swirl | |
893 | 5c6562c2 | Max Reitz | r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status); |
894 | 5c6562c2 | Max Reitz | r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status); |
895 | 5c6562c2 | Max Reitz | r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status); |
896 | 5c6562c2 | Max Reitz | r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status); |
897 | 664e0f19 | bellard | *d = r; |
898 | 664e0f19 | bellard | } |
899 | 664e0f19 | bellard | |
900 | d3eb5eae | Blue Swirl | void helper_haddpd(CPUX86State *env, XMMReg *d, XMMReg *s)
|
901 | 664e0f19 | bellard | { |
902 | 664e0f19 | bellard | XMMReg r; |
903 | e01d9d31 | Blue Swirl | |
904 | 5c6562c2 | Max Reitz | r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status); |
905 | 5c6562c2 | Max Reitz | r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status); |
906 | 664e0f19 | bellard | *d = r; |
907 | 664e0f19 | bellard | } |
908 | 664e0f19 | bellard | |
909 | d3eb5eae | Blue Swirl | void helper_hsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
|
910 | 664e0f19 | bellard | { |
911 | 664e0f19 | bellard | XMMReg r; |
912 | e01d9d31 | Blue Swirl | |
913 | 5c6562c2 | Max Reitz | r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status); |
914 | 5c6562c2 | Max Reitz | r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status); |
915 | 5c6562c2 | Max Reitz | r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status); |
916 | 5c6562c2 | Max Reitz | r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status); |
917 | 664e0f19 | bellard | *d = r; |
918 | 664e0f19 | bellard | } |
919 | 664e0f19 | bellard | |
920 | d3eb5eae | Blue Swirl | void helper_hsubpd(CPUX86State *env, XMMReg *d, XMMReg *s)
|
921 | 664e0f19 | bellard | { |
922 | 664e0f19 | bellard | XMMReg r; |
923 | e01d9d31 | Blue Swirl | |
924 | 5c6562c2 | Max Reitz | r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status); |
925 | 5c6562c2 | Max Reitz | r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status); |
926 | 664e0f19 | bellard | *d = r; |
927 | 664e0f19 | bellard | } |
928 | 664e0f19 | bellard | |
929 | d3eb5eae | Blue Swirl | void helper_addsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
|
930 | 664e0f19 | bellard | { |
931 | 5c6562c2 | Max Reitz | d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status); |
932 | 5c6562c2 | Max Reitz | d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status); |
933 | 5c6562c2 | Max Reitz | d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status); |
934 | 5c6562c2 | Max Reitz | d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status); |
935 | 664e0f19 | bellard | } |
936 | 664e0f19 | bellard | |
937 | d3eb5eae | Blue Swirl | void helper_addsubpd(CPUX86State *env, XMMReg *d, XMMReg *s)
|
938 | 664e0f19 | bellard | { |
939 | 5c6562c2 | Max Reitz | d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status); |
940 | 5c6562c2 | Max Reitz | d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status); |
941 | 664e0f19 | bellard | } |
942 | 664e0f19 | bellard | |
943 | 664e0f19 | bellard | /* XXX: unordered */
|
944 | d3eb5eae | Blue Swirl | #define SSE_HELPER_CMP(name, F) \
|
945 | d3eb5eae | Blue Swirl | void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ |
946 | d3eb5eae | Blue Swirl | { \ |
947 | d3eb5eae | Blue Swirl | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
948 | d3eb5eae | Blue Swirl | d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ |
949 | d3eb5eae | Blue Swirl | d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ |
950 | d3eb5eae | Blue Swirl | d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ |
951 | d3eb5eae | Blue Swirl | } \ |
952 | d3eb5eae | Blue Swirl | \ |
953 | d3eb5eae | Blue Swirl | void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ |
954 | d3eb5eae | Blue Swirl | { \ |
955 | d3eb5eae | Blue Swirl | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
956 | d3eb5eae | Blue Swirl | } \ |
957 | d3eb5eae | Blue Swirl | \ |
958 | d3eb5eae | Blue Swirl | void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ |
959 | d3eb5eae | Blue Swirl | { \ |
960 | d3eb5eae | Blue Swirl | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
961 | d3eb5eae | Blue Swirl | d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ |
962 | d3eb5eae | Blue Swirl | } \ |
963 | d3eb5eae | Blue Swirl | \ |
964 | d3eb5eae | Blue Swirl | void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ |
965 | d3eb5eae | Blue Swirl | { \ |
966 | d3eb5eae | Blue Swirl | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
967 | e01d9d31 | Blue Swirl | } |
968 | e01d9d31 | Blue Swirl | |
969 | e01d9d31 | Blue Swirl | #define FPU_CMPEQ(size, a, b) \
|
970 | e01d9d31 | Blue Swirl | (float ## size ## _eq_quiet(a, b, &env->sse_status) ? -1 : 0) |
971 | e01d9d31 | Blue Swirl | #define FPU_CMPLT(size, a, b) \
|
972 | e01d9d31 | Blue Swirl | (float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0) |
973 | e01d9d31 | Blue Swirl | #define FPU_CMPLE(size, a, b) \
|
974 | e01d9d31 | Blue Swirl | (float ## size ## _le(a, b, &env->sse_status) ? -1 : 0) |
975 | e01d9d31 | Blue Swirl | #define FPU_CMPUNORD(size, a, b) \
|
976 | e01d9d31 | Blue Swirl | (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? -1 : 0) |
977 | e01d9d31 | Blue Swirl | #define FPU_CMPNEQ(size, a, b) \
|
978 | e01d9d31 | Blue Swirl | (float ## size ## _eq_quiet(a, b, &env->sse_status) ? 0 : -1) |
979 | e01d9d31 | Blue Swirl | #define FPU_CMPNLT(size, a, b) \
|
980 | e01d9d31 | Blue Swirl | (float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1) |
981 | e01d9d31 | Blue Swirl | #define FPU_CMPNLE(size, a, b) \
|
982 | e01d9d31 | Blue Swirl | (float ## size ## _le(a, b, &env->sse_status) ? 0 : -1) |
983 | e01d9d31 | Blue Swirl | #define FPU_CMPORD(size, a, b) \
|
984 | e01d9d31 | Blue Swirl | (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? 0 : -1) |
985 | 664e0f19 | bellard | |
986 | 5af45186 | bellard | SSE_HELPER_CMP(cmpeq, FPU_CMPEQ) |
987 | 5af45186 | bellard | SSE_HELPER_CMP(cmplt, FPU_CMPLT) |
988 | 5af45186 | bellard | SSE_HELPER_CMP(cmple, FPU_CMPLE) |
989 | 5af45186 | bellard | SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD) |
990 | 5af45186 | bellard | SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ) |
991 | 5af45186 | bellard | SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT) |
992 | 5af45186 | bellard | SSE_HELPER_CMP(cmpnle, FPU_CMPNLE) |
993 | 5af45186 | bellard | SSE_HELPER_CMP(cmpord, FPU_CMPORD) |
994 | 664e0f19 | bellard | |
995 | 1e6eec8b | Blue Swirl | static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C}; |
996 | 43fb823b | bellard | |
997 | d3eb5eae | Blue Swirl | void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s)
|
998 | 664e0f19 | bellard | { |
999 | 43fb823b | bellard | int ret;
|
1000 | 8422b113 | bellard | float32 s0, s1; |
1001 | 664e0f19 | bellard | |
1002 | 664e0f19 | bellard | s0 = d->XMM_S(0);
|
1003 | 664e0f19 | bellard | s1 = s->XMM_S(0);
|
1004 | 43fb823b | bellard | ret = float32_compare_quiet(s0, s1, &env->sse_status); |
1005 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
1006 | 664e0f19 | bellard | } |
1007 | 664e0f19 | bellard | |
1008 | d3eb5eae | Blue Swirl | void helper_comiss(CPUX86State *env, Reg *d, Reg *s)
|
1009 | 664e0f19 | bellard | { |
1010 | 43fb823b | bellard | int ret;
|
1011 | 8422b113 | bellard | float32 s0, s1; |
1012 | 664e0f19 | bellard | |
1013 | 664e0f19 | bellard | s0 = d->XMM_S(0);
|
1014 | 664e0f19 | bellard | s1 = s->XMM_S(0);
|
1015 | 43fb823b | bellard | ret = float32_compare(s0, s1, &env->sse_status); |
1016 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
1017 | 664e0f19 | bellard | } |
1018 | 664e0f19 | bellard | |
1019 | d3eb5eae | Blue Swirl | void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s)
|
1020 | 664e0f19 | bellard | { |
1021 | 43fb823b | bellard | int ret;
|
1022 | 8422b113 | bellard | float64 d0, d1; |
1023 | 664e0f19 | bellard | |
1024 | 664e0f19 | bellard | d0 = d->XMM_D(0);
|
1025 | 664e0f19 | bellard | d1 = s->XMM_D(0);
|
1026 | 43fb823b | bellard | ret = float64_compare_quiet(d0, d1, &env->sse_status); |
1027 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
1028 | 664e0f19 | bellard | } |
1029 | 664e0f19 | bellard | |
1030 | d3eb5eae | Blue Swirl | void helper_comisd(CPUX86State *env, Reg *d, Reg *s)
|
1031 | 664e0f19 | bellard | { |
1032 | 43fb823b | bellard | int ret;
|
1033 | 8422b113 | bellard | float64 d0, d1; |
1034 | 664e0f19 | bellard | |
1035 | 664e0f19 | bellard | d0 = d->XMM_D(0);
|
1036 | 664e0f19 | bellard | d1 = s->XMM_D(0);
|
1037 | 43fb823b | bellard | ret = float64_compare(d0, d1, &env->sse_status); |
1038 | 43fb823b | bellard | CC_SRC = comis_eflags[ret + 1];
|
1039 | 664e0f19 | bellard | } |
1040 | 664e0f19 | bellard | |
1041 | d3eb5eae | Blue Swirl | uint32_t helper_movmskps(CPUX86State *env, Reg *s) |
1042 | 664e0f19 | bellard | { |
1043 | 664e0f19 | bellard | int b0, b1, b2, b3;
|
1044 | e01d9d31 | Blue Swirl | |
1045 | 664e0f19 | bellard | b0 = s->XMM_L(0) >> 31; |
1046 | 664e0f19 | bellard | b1 = s->XMM_L(1) >> 31; |
1047 | 664e0f19 | bellard | b2 = s->XMM_L(2) >> 31; |
1048 | 664e0f19 | bellard | b3 = s->XMM_L(3) >> 31; |
1049 | 5af45186 | bellard | return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3); |
1050 | 664e0f19 | bellard | } |
1051 | 664e0f19 | bellard | |
1052 | d3eb5eae | Blue Swirl | uint32_t helper_movmskpd(CPUX86State *env, Reg *s) |
1053 | 664e0f19 | bellard | { |
1054 | 664e0f19 | bellard | int b0, b1;
|
1055 | e01d9d31 | Blue Swirl | |
1056 | 664e0f19 | bellard | b0 = s->XMM_L(1) >> 31; |
1057 | 664e0f19 | bellard | b1 = s->XMM_L(3) >> 31; |
1058 | 5af45186 | bellard | return b0 | (b1 << 1); |
1059 | 664e0f19 | bellard | } |
1060 | 664e0f19 | bellard | |
1061 | 664e0f19 | bellard | #endif
|
1062 | 664e0f19 | bellard | |
1063 | d3eb5eae | Blue Swirl | uint32_t glue(helper_pmovmskb, SUFFIX)(CPUX86State *env, Reg *s) |
1064 | 5af45186 | bellard | { |
1065 | 5af45186 | bellard | uint32_t val; |
1066 | e01d9d31 | Blue Swirl | |
1067 | 5af45186 | bellard | val = 0;
|
1068 | 30913bae | aurel32 | val |= (s->B(0) >> 7); |
1069 | 30913bae | aurel32 | val |= (s->B(1) >> 6) & 0x02; |
1070 | 30913bae | aurel32 | val |= (s->B(2) >> 5) & 0x04; |
1071 | 30913bae | aurel32 | val |= (s->B(3) >> 4) & 0x08; |
1072 | 30913bae | aurel32 | val |= (s->B(4) >> 3) & 0x10; |
1073 | 30913bae | aurel32 | val |= (s->B(5) >> 2) & 0x20; |
1074 | 30913bae | aurel32 | val |= (s->B(6) >> 1) & 0x40; |
1075 | 30913bae | aurel32 | val |= (s->B(7)) & 0x80; |
1076 | 664e0f19 | bellard | #if SHIFT == 1 |
1077 | 30913bae | aurel32 | val |= (s->B(8) << 1) & 0x0100; |
1078 | 30913bae | aurel32 | val |= (s->B(9) << 2) & 0x0200; |
1079 | 30913bae | aurel32 | val |= (s->B(10) << 3) & 0x0400; |
1080 | 30913bae | aurel32 | val |= (s->B(11) << 4) & 0x0800; |
1081 | 30913bae | aurel32 | val |= (s->B(12) << 5) & 0x1000; |
1082 | 30913bae | aurel32 | val |= (s->B(13) << 6) & 0x2000; |
1083 | 30913bae | aurel32 | val |= (s->B(14) << 7) & 0x4000; |
1084 | 30913bae | aurel32 | val |= (s->B(15) << 8) & 0x8000; |
1085 | 664e0f19 | bellard | #endif
|
1086 | 5af45186 | bellard | return val;
|
1087 | 664e0f19 | bellard | } |
1088 | 664e0f19 | bellard | |
1089 | d3eb5eae | Blue Swirl | void glue(helper_packsswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1090 | 664e0f19 | bellard | { |
1091 | 5af45186 | bellard | Reg r; |
1092 | 664e0f19 | bellard | |
1093 | 664e0f19 | bellard | r.B(0) = satsb((int16_t)d->W(0)); |
1094 | 664e0f19 | bellard | r.B(1) = satsb((int16_t)d->W(1)); |
1095 | 664e0f19 | bellard | r.B(2) = satsb((int16_t)d->W(2)); |
1096 | 664e0f19 | bellard | r.B(3) = satsb((int16_t)d->W(3)); |
1097 | 664e0f19 | bellard | #if SHIFT == 1 |
1098 | 664e0f19 | bellard | r.B(4) = satsb((int16_t)d->W(4)); |
1099 | 664e0f19 | bellard | r.B(5) = satsb((int16_t)d->W(5)); |
1100 | 664e0f19 | bellard | r.B(6) = satsb((int16_t)d->W(6)); |
1101 | 664e0f19 | bellard | r.B(7) = satsb((int16_t)d->W(7)); |
1102 | 664e0f19 | bellard | #endif
|
1103 | 664e0f19 | bellard | r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0)); |
1104 | 664e0f19 | bellard | r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1)); |
1105 | 664e0f19 | bellard | r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2)); |
1106 | 664e0f19 | bellard | r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3)); |
1107 | 664e0f19 | bellard | #if SHIFT == 1 |
1108 | 664e0f19 | bellard | r.B(12) = satsb((int16_t)s->W(4)); |
1109 | 664e0f19 | bellard | r.B(13) = satsb((int16_t)s->W(5)); |
1110 | 664e0f19 | bellard | r.B(14) = satsb((int16_t)s->W(6)); |
1111 | 664e0f19 | bellard | r.B(15) = satsb((int16_t)s->W(7)); |
1112 | 664e0f19 | bellard | #endif
|
1113 | 664e0f19 | bellard | *d = r; |
1114 | 664e0f19 | bellard | } |
1115 | 664e0f19 | bellard | |
1116 | d3eb5eae | Blue Swirl | void glue(helper_packuswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1117 | 664e0f19 | bellard | { |
1118 | 5af45186 | bellard | Reg r; |
1119 | 664e0f19 | bellard | |
1120 | 664e0f19 | bellard | r.B(0) = satub((int16_t)d->W(0)); |
1121 | 664e0f19 | bellard | r.B(1) = satub((int16_t)d->W(1)); |
1122 | 664e0f19 | bellard | r.B(2) = satub((int16_t)d->W(2)); |
1123 | 664e0f19 | bellard | r.B(3) = satub((int16_t)d->W(3)); |
1124 | 664e0f19 | bellard | #if SHIFT == 1 |
1125 | 664e0f19 | bellard | r.B(4) = satub((int16_t)d->W(4)); |
1126 | 664e0f19 | bellard | r.B(5) = satub((int16_t)d->W(5)); |
1127 | 664e0f19 | bellard | r.B(6) = satub((int16_t)d->W(6)); |
1128 | 664e0f19 | bellard | r.B(7) = satub((int16_t)d->W(7)); |
1129 | 664e0f19 | bellard | #endif
|
1130 | 664e0f19 | bellard | r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0)); |
1131 | 664e0f19 | bellard | r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1)); |
1132 | 664e0f19 | bellard | r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2)); |
1133 | 664e0f19 | bellard | r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3)); |
1134 | 664e0f19 | bellard | #if SHIFT == 1 |
1135 | 664e0f19 | bellard | r.B(12) = satub((int16_t)s->W(4)); |
1136 | 664e0f19 | bellard | r.B(13) = satub((int16_t)s->W(5)); |
1137 | 664e0f19 | bellard | r.B(14) = satub((int16_t)s->W(6)); |
1138 | 664e0f19 | bellard | r.B(15) = satub((int16_t)s->W(7)); |
1139 | 664e0f19 | bellard | #endif
|
1140 | 664e0f19 | bellard | *d = r; |
1141 | 664e0f19 | bellard | } |
1142 | 664e0f19 | bellard | |
1143 | d3eb5eae | Blue Swirl | void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1144 | 664e0f19 | bellard | { |
1145 | 5af45186 | bellard | Reg r; |
1146 | 664e0f19 | bellard | |
1147 | 664e0f19 | bellard | r.W(0) = satsw(d->L(0)); |
1148 | 664e0f19 | bellard | r.W(1) = satsw(d->L(1)); |
1149 | 664e0f19 | bellard | #if SHIFT == 1 |
1150 | 664e0f19 | bellard | r.W(2) = satsw(d->L(2)); |
1151 | 664e0f19 | bellard | r.W(3) = satsw(d->L(3)); |
1152 | 664e0f19 | bellard | #endif
|
1153 | 664e0f19 | bellard | r.W((2 << SHIFT) + 0) = satsw(s->L(0)); |
1154 | 664e0f19 | bellard | r.W((2 << SHIFT) + 1) = satsw(s->L(1)); |
1155 | 664e0f19 | bellard | #if SHIFT == 1 |
1156 | 664e0f19 | bellard | r.W(6) = satsw(s->L(2)); |
1157 | 664e0f19 | bellard | r.W(7) = satsw(s->L(3)); |
1158 | 664e0f19 | bellard | #endif
|
1159 | 664e0f19 | bellard | *d = r; |
1160 | 664e0f19 | bellard | } |
1161 | 664e0f19 | bellard | |
1162 | e01d9d31 | Blue Swirl | #define UNPCK_OP(base_name, base) \
|
1163 | e01d9d31 | Blue Swirl | \ |
1164 | d3eb5eae | Blue Swirl | void glue(helper_punpck ## base_name ## bw, SUFFIX)(CPUX86State *env,\ |
1165 | d3eb5eae | Blue Swirl | Reg *d, Reg *s) \ |
1166 | e01d9d31 | Blue Swirl | { \ |
1167 | e01d9d31 | Blue Swirl | Reg r; \ |
1168 | e01d9d31 | Blue Swirl | \ |
1169 | e01d9d31 | Blue Swirl | r.B(0) = d->B((base << (SHIFT + 2)) + 0); \ |
1170 | e01d9d31 | Blue Swirl | r.B(1) = s->B((base << (SHIFT + 2)) + 0); \ |
1171 | e01d9d31 | Blue Swirl | r.B(2) = d->B((base << (SHIFT + 2)) + 1); \ |
1172 | e01d9d31 | Blue Swirl | r.B(3) = s->B((base << (SHIFT + 2)) + 1); \ |
1173 | e01d9d31 | Blue Swirl | r.B(4) = d->B((base << (SHIFT + 2)) + 2); \ |
1174 | e01d9d31 | Blue Swirl | r.B(5) = s->B((base << (SHIFT + 2)) + 2); \ |
1175 | e01d9d31 | Blue Swirl | r.B(6) = d->B((base << (SHIFT + 2)) + 3); \ |
1176 | e01d9d31 | Blue Swirl | r.B(7) = s->B((base << (SHIFT + 2)) + 3); \ |
1177 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
1178 | e01d9d31 | Blue Swirl | r.B(8) = d->B((base << (SHIFT + 2)) + 4); \ |
1179 | e01d9d31 | Blue Swirl | r.B(9) = s->B((base << (SHIFT + 2)) + 4); \ |
1180 | e01d9d31 | Blue Swirl | r.B(10) = d->B((base << (SHIFT + 2)) + 5); \ |
1181 | e01d9d31 | Blue Swirl | r.B(11) = s->B((base << (SHIFT + 2)) + 5); \ |
1182 | e01d9d31 | Blue Swirl | r.B(12) = d->B((base << (SHIFT + 2)) + 6); \ |
1183 | e01d9d31 | Blue Swirl | r.B(13) = s->B((base << (SHIFT + 2)) + 6); \ |
1184 | e01d9d31 | Blue Swirl | r.B(14) = d->B((base << (SHIFT + 2)) + 7); \ |
1185 | e01d9d31 | Blue Swirl | r.B(15) = s->B((base << (SHIFT + 2)) + 7); \ |
1186 | d3eb5eae | Blue Swirl | ) \ |
1187 | e01d9d31 | Blue Swirl | *d = r; \ |
1188 | e01d9d31 | Blue Swirl | } \ |
1189 | e01d9d31 | Blue Swirl | \ |
1190 | d3eb5eae | Blue Swirl | void glue(helper_punpck ## base_name ## wd, SUFFIX)(CPUX86State *env,\ |
1191 | d3eb5eae | Blue Swirl | Reg *d, Reg *s) \ |
1192 | e01d9d31 | Blue Swirl | { \ |
1193 | e01d9d31 | Blue Swirl | Reg r; \ |
1194 | e01d9d31 | Blue Swirl | \ |
1195 | e01d9d31 | Blue Swirl | r.W(0) = d->W((base << (SHIFT + 1)) + 0); \ |
1196 | e01d9d31 | Blue Swirl | r.W(1) = s->W((base << (SHIFT + 1)) + 0); \ |
1197 | e01d9d31 | Blue Swirl | r.W(2) = d->W((base << (SHIFT + 1)) + 1); \ |
1198 | e01d9d31 | Blue Swirl | r.W(3) = s->W((base << (SHIFT + 1)) + 1); \ |
1199 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
1200 | e01d9d31 | Blue Swirl | r.W(4) = d->W((base << (SHIFT + 1)) + 2); \ |
1201 | e01d9d31 | Blue Swirl | r.W(5) = s->W((base << (SHIFT + 1)) + 2); \ |
1202 | e01d9d31 | Blue Swirl | r.W(6) = d->W((base << (SHIFT + 1)) + 3); \ |
1203 | e01d9d31 | Blue Swirl | r.W(7) = s->W((base << (SHIFT + 1)) + 3); \ |
1204 | d3eb5eae | Blue Swirl | ) \ |
1205 | e01d9d31 | Blue Swirl | *d = r; \ |
1206 | e01d9d31 | Blue Swirl | } \ |
1207 | e01d9d31 | Blue Swirl | \ |
1208 | d3eb5eae | Blue Swirl | void glue(helper_punpck ## base_name ## dq, SUFFIX)(CPUX86State *env,\ |
1209 | d3eb5eae | Blue Swirl | Reg *d, Reg *s) \ |
1210 | e01d9d31 | Blue Swirl | { \ |
1211 | e01d9d31 | Blue Swirl | Reg r; \ |
1212 | e01d9d31 | Blue Swirl | \ |
1213 | e01d9d31 | Blue Swirl | r.L(0) = d->L((base << SHIFT) + 0); \ |
1214 | e01d9d31 | Blue Swirl | r.L(1) = s->L((base << SHIFT) + 0); \ |
1215 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
1216 | e01d9d31 | Blue Swirl | r.L(2) = d->L((base << SHIFT) + 1); \ |
1217 | e01d9d31 | Blue Swirl | r.L(3) = s->L((base << SHIFT) + 1); \ |
1218 | d3eb5eae | Blue Swirl | ) \ |
1219 | e01d9d31 | Blue Swirl | *d = r; \ |
1220 | e01d9d31 | Blue Swirl | } \ |
1221 | e01d9d31 | Blue Swirl | \ |
1222 | e01d9d31 | Blue Swirl | XMM_ONLY( \ |
1223 | d3eb5eae | Blue Swirl | void glue(helper_punpck ## base_name ## qdq, SUFFIX)(CPUX86State \ |
1224 | d3eb5eae | Blue Swirl | *env, \ |
1225 | d3eb5eae | Blue Swirl | Reg *d, \ |
1226 | e01d9d31 | Blue Swirl | Reg *s) \ |
1227 | e01d9d31 | Blue Swirl | { \ |
1228 | e01d9d31 | Blue Swirl | Reg r; \ |
1229 | e01d9d31 | Blue Swirl | \ |
1230 | e01d9d31 | Blue Swirl | r.Q(0) = d->Q(base); \
|
1231 | e01d9d31 | Blue Swirl | r.Q(1) = s->Q(base); \
|
1232 | e01d9d31 | Blue Swirl | *d = r; \ |
1233 | e01d9d31 | Blue Swirl | } \ |
1234 | e01d9d31 | Blue Swirl | ) |
1235 | 664e0f19 | bellard | |
1236 | 664e0f19 | bellard | UNPCK_OP(l, 0)
|
1237 | 664e0f19 | bellard | UNPCK_OP(h, 1)
|
1238 | 664e0f19 | bellard | |
1239 | a35f3ec7 | aurel32 | /* 3DNow! float ops */
|
1240 | a35f3ec7 | aurel32 | #if SHIFT == 0 |
1241 | d3eb5eae | Blue Swirl | void helper_pi2fd(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1242 | a35f3ec7 | aurel32 | { |
1243 | a35f3ec7 | aurel32 | d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status); |
1244 | a35f3ec7 | aurel32 | d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status); |
1245 | a35f3ec7 | aurel32 | } |
1246 | a35f3ec7 | aurel32 | |
1247 | d3eb5eae | Blue Swirl | void helper_pi2fw(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1248 | a35f3ec7 | aurel32 | { |
1249 | a35f3ec7 | aurel32 | d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status); |
1250 | a35f3ec7 | aurel32 | d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status); |
1251 | a35f3ec7 | aurel32 | } |
1252 | a35f3ec7 | aurel32 | |
1253 | d3eb5eae | Blue Swirl | void helper_pf2id(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1254 | a35f3ec7 | aurel32 | { |
1255 | a35f3ec7 | aurel32 | d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status); |
1256 | a35f3ec7 | aurel32 | d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status); |
1257 | a35f3ec7 | aurel32 | } |
1258 | a35f3ec7 | aurel32 | |
1259 | d3eb5eae | Blue Swirl | void helper_pf2iw(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1260 | a35f3ec7 | aurel32 | { |
1261 | e01d9d31 | Blue Swirl | d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), |
1262 | e01d9d31 | Blue Swirl | &env->mmx_status)); |
1263 | e01d9d31 | Blue Swirl | d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), |
1264 | e01d9d31 | Blue Swirl | &env->mmx_status)); |
1265 | a35f3ec7 | aurel32 | } |
1266 | a35f3ec7 | aurel32 | |
1267 | d3eb5eae | Blue Swirl | void helper_pfacc(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1268 | a35f3ec7 | aurel32 | { |
1269 | a35f3ec7 | aurel32 | MMXReg r; |
1270 | e01d9d31 | Blue Swirl | |
1271 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1272 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1273 | a35f3ec7 | aurel32 | *d = r; |
1274 | a35f3ec7 | aurel32 | } |
1275 | a35f3ec7 | aurel32 | |
1276 | d3eb5eae | Blue Swirl | void helper_pfadd(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1277 | a35f3ec7 | aurel32 | { |
1278 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1279 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1280 | a35f3ec7 | aurel32 | } |
1281 | a35f3ec7 | aurel32 | |
1282 | d3eb5eae | Blue Swirl | void helper_pfcmpeq(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1283 | a35f3ec7 | aurel32 | { |
1284 | e01d9d31 | Blue Swirl | d->MMX_L(0) = float32_eq_quiet(d->MMX_S(0), s->MMX_S(0), |
1285 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1286 | e01d9d31 | Blue Swirl | d->MMX_L(1) = float32_eq_quiet(d->MMX_S(1), s->MMX_S(1), |
1287 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1288 | a35f3ec7 | aurel32 | } |
1289 | a35f3ec7 | aurel32 | |
1290 | d3eb5eae | Blue Swirl | void helper_pfcmpge(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1291 | a35f3ec7 | aurel32 | { |
1292 | e01d9d31 | Blue Swirl | d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), |
1293 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1294 | e01d9d31 | Blue Swirl | d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), |
1295 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1296 | a35f3ec7 | aurel32 | } |
1297 | a35f3ec7 | aurel32 | |
1298 | d3eb5eae | Blue Swirl | void helper_pfcmpgt(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1299 | a35f3ec7 | aurel32 | { |
1300 | e01d9d31 | Blue Swirl | d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), |
1301 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1302 | e01d9d31 | Blue Swirl | d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), |
1303 | e01d9d31 | Blue Swirl | &env->mmx_status) ? -1 : 0; |
1304 | a35f3ec7 | aurel32 | } |
1305 | a35f3ec7 | aurel32 | |
1306 | d3eb5eae | Blue Swirl | void helper_pfmax(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1307 | a35f3ec7 | aurel32 | { |
1308 | e01d9d31 | Blue Swirl | if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status)) { |
1309 | a35f3ec7 | aurel32 | d->MMX_S(0) = s->MMX_S(0); |
1310 | e01d9d31 | Blue Swirl | } |
1311 | e01d9d31 | Blue Swirl | if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status)) { |
1312 | a35f3ec7 | aurel32 | d->MMX_S(1) = s->MMX_S(1); |
1313 | e01d9d31 | Blue Swirl | } |
1314 | a35f3ec7 | aurel32 | } |
1315 | a35f3ec7 | aurel32 | |
1316 | d3eb5eae | Blue Swirl | void helper_pfmin(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1317 | a35f3ec7 | aurel32 | { |
1318 | e01d9d31 | Blue Swirl | if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status)) { |
1319 | a35f3ec7 | aurel32 | d->MMX_S(0) = s->MMX_S(0); |
1320 | e01d9d31 | Blue Swirl | } |
1321 | e01d9d31 | Blue Swirl | if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status)) { |
1322 | a35f3ec7 | aurel32 | d->MMX_S(1) = s->MMX_S(1); |
1323 | e01d9d31 | Blue Swirl | } |
1324 | a35f3ec7 | aurel32 | } |
1325 | a35f3ec7 | aurel32 | |
1326 | d3eb5eae | Blue Swirl | void helper_pfmul(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1327 | a35f3ec7 | aurel32 | { |
1328 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1329 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1330 | a35f3ec7 | aurel32 | } |
1331 | a35f3ec7 | aurel32 | |
1332 | d3eb5eae | Blue Swirl | void helper_pfnacc(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1333 | a35f3ec7 | aurel32 | { |
1334 | a35f3ec7 | aurel32 | MMXReg r; |
1335 | e01d9d31 | Blue Swirl | |
1336 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1337 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1338 | a35f3ec7 | aurel32 | *d = r; |
1339 | a35f3ec7 | aurel32 | } |
1340 | a35f3ec7 | aurel32 | |
1341 | d3eb5eae | Blue Swirl | void helper_pfpnacc(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1342 | a35f3ec7 | aurel32 | { |
1343 | a35f3ec7 | aurel32 | MMXReg r; |
1344 | e01d9d31 | Blue Swirl | |
1345 | a35f3ec7 | aurel32 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
1346 | a35f3ec7 | aurel32 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
1347 | a35f3ec7 | aurel32 | *d = r; |
1348 | a35f3ec7 | aurel32 | } |
1349 | a35f3ec7 | aurel32 | |
1350 | d3eb5eae | Blue Swirl | void helper_pfrcp(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1351 | a35f3ec7 | aurel32 | { |
1352 | c2ef9a83 | Aurelien Jarno | d->MMX_S(0) = float32_div(float32_one, s->MMX_S(0), &env->mmx_status); |
1353 | a35f3ec7 | aurel32 | d->MMX_S(1) = d->MMX_S(0); |
1354 | a35f3ec7 | aurel32 | } |
1355 | a35f3ec7 | aurel32 | |
1356 | d3eb5eae | Blue Swirl | void helper_pfrsqrt(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1357 | a35f3ec7 | aurel32 | { |
1358 | a35f3ec7 | aurel32 | d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff; |
1359 | c2ef9a83 | Aurelien Jarno | d->MMX_S(1) = float32_div(float32_one,
|
1360 | c2ef9a83 | Aurelien Jarno | float32_sqrt(d->MMX_S(1), &env->mmx_status),
|
1361 | c2ef9a83 | Aurelien Jarno | &env->mmx_status); |
1362 | a35f3ec7 | aurel32 | d->MMX_L(1) |= s->MMX_L(0) & 0x80000000; |
1363 | a35f3ec7 | aurel32 | d->MMX_L(0) = d->MMX_L(1); |
1364 | a35f3ec7 | aurel32 | } |
1365 | a35f3ec7 | aurel32 | |
1366 | d3eb5eae | Blue Swirl | void helper_pfsub(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1367 | a35f3ec7 | aurel32 | { |
1368 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
1369 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
1370 | a35f3ec7 | aurel32 | } |
1371 | a35f3ec7 | aurel32 | |
1372 | d3eb5eae | Blue Swirl | void helper_pfsubr(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1373 | a35f3ec7 | aurel32 | { |
1374 | a35f3ec7 | aurel32 | d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status); |
1375 | a35f3ec7 | aurel32 | d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status); |
1376 | a35f3ec7 | aurel32 | } |
1377 | a35f3ec7 | aurel32 | |
1378 | d3eb5eae | Blue Swirl | void helper_pswapd(CPUX86State *env, MMXReg *d, MMXReg *s)
|
1379 | a35f3ec7 | aurel32 | { |
1380 | a35f3ec7 | aurel32 | MMXReg r; |
1381 | e01d9d31 | Blue Swirl | |
1382 | a35f3ec7 | aurel32 | r.MMX_L(0) = s->MMX_L(1); |
1383 | a35f3ec7 | aurel32 | r.MMX_L(1) = s->MMX_L(0); |
1384 | a35f3ec7 | aurel32 | *d = r; |
1385 | a35f3ec7 | aurel32 | } |
1386 | a35f3ec7 | aurel32 | #endif
|
1387 | a35f3ec7 | aurel32 | |
1388 | 4242b1bd | balrog | /* SSSE3 op helpers */
|
1389 | d3eb5eae | Blue Swirl | void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1390 | 4242b1bd | balrog | { |
1391 | 4242b1bd | balrog | int i;
|
1392 | 4242b1bd | balrog | Reg r; |
1393 | 4242b1bd | balrog | |
1394 | e01d9d31 | Blue Swirl | for (i = 0; i < (8 << SHIFT); i++) { |
1395 | 4242b1bd | balrog | r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1))); |
1396 | e01d9d31 | Blue Swirl | } |
1397 | 4242b1bd | balrog | |
1398 | 4242b1bd | balrog | *d = r; |
1399 | 4242b1bd | balrog | } |
1400 | 4242b1bd | balrog | |
1401 | d3eb5eae | Blue Swirl | void glue(helper_phaddw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1402 | 4242b1bd | balrog | { |
1403 | 4242b1bd | balrog | d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1); |
1404 | 4242b1bd | balrog | d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3); |
1405 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5)); |
1406 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7)); |
1407 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1); |
1408 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3); |
1409 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5)); |
1410 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7)); |
1411 | 4242b1bd | balrog | } |
1412 | 4242b1bd | balrog | |
1413 | d3eb5eae | Blue Swirl | void glue(helper_phaddd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1414 | 4242b1bd | balrog | { |
1415 | 4242b1bd | balrog | d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1); |
1416 | 4242b1bd | balrog | XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3)); |
1417 | 4242b1bd | balrog | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1); |
1418 | 4242b1bd | balrog | XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3)); |
1419 | 4242b1bd | balrog | } |
1420 | 4242b1bd | balrog | |
1421 | d3eb5eae | Blue Swirl | void glue(helper_phaddsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1422 | 4242b1bd | balrog | { |
1423 | 4242b1bd | balrog | d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1)); |
1424 | 4242b1bd | balrog | d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3)); |
1425 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5))); |
1426 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7))); |
1427 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1)); |
1428 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3)); |
1429 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5))); |
1430 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7))); |
1431 | 4242b1bd | balrog | } |
1432 | 4242b1bd | balrog | |
1433 | d3eb5eae | Blue Swirl | void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1434 | 4242b1bd | balrog | { |
1435 | e01d9d31 | Blue Swirl | d->W(0) = satsw((int8_t)s->B(0) * (uint8_t)d->B(0) + |
1436 | e01d9d31 | Blue Swirl | (int8_t)s->B(1) * (uint8_t)d->B(1)); |
1437 | e01d9d31 | Blue Swirl | d->W(1) = satsw((int8_t)s->B(2) * (uint8_t)d->B(2) + |
1438 | e01d9d31 | Blue Swirl | (int8_t)s->B(3) * (uint8_t)d->B(3)); |
1439 | e01d9d31 | Blue Swirl | d->W(2) = satsw((int8_t)s->B(4) * (uint8_t)d->B(4) + |
1440 | e01d9d31 | Blue Swirl | (int8_t)s->B(5) * (uint8_t)d->B(5)); |
1441 | e01d9d31 | Blue Swirl | d->W(3) = satsw((int8_t)s->B(6) * (uint8_t)d->B(6) + |
1442 | e01d9d31 | Blue Swirl | (int8_t)s->B(7) * (uint8_t)d->B(7)); |
1443 | 4242b1bd | balrog | #if SHIFT == 1 |
1444 | e01d9d31 | Blue Swirl | d->W(4) = satsw((int8_t)s->B(8) * (uint8_t)d->B(8) + |
1445 | e01d9d31 | Blue Swirl | (int8_t)s->B(9) * (uint8_t)d->B(9)); |
1446 | 4242b1bd | balrog | d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) + |
1447 | 4242b1bd | balrog | (int8_t)s->B(11) * (uint8_t)d->B(11)); |
1448 | 4242b1bd | balrog | d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) + |
1449 | 4242b1bd | balrog | (int8_t)s->B(13) * (uint8_t)d->B(13)); |
1450 | 4242b1bd | balrog | d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) + |
1451 | 4242b1bd | balrog | (int8_t)s->B(15) * (uint8_t)d->B(15)); |
1452 | 4242b1bd | balrog | #endif
|
1453 | 4242b1bd | balrog | } |
1454 | 4242b1bd | balrog | |
1455 | d3eb5eae | Blue Swirl | void glue(helper_phsubw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1456 | 4242b1bd | balrog | { |
1457 | 4242b1bd | balrog | d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1); |
1458 | 4242b1bd | balrog | d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3); |
1459 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5)); |
1460 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7)); |
1461 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1); |
1462 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3); |
1463 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5)); |
1464 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7)); |
1465 | 4242b1bd | balrog | } |
1466 | 4242b1bd | balrog | |
1467 | d3eb5eae | Blue Swirl | void glue(helper_phsubd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1468 | 4242b1bd | balrog | { |
1469 | 4242b1bd | balrog | d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1); |
1470 | 4242b1bd | balrog | XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3)); |
1471 | 4242b1bd | balrog | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1); |
1472 | 4242b1bd | balrog | XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3)); |
1473 | 4242b1bd | balrog | } |
1474 | 4242b1bd | balrog | |
1475 | d3eb5eae | Blue Swirl | void glue(helper_phsubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1476 | 4242b1bd | balrog | { |
1477 | 4242b1bd | balrog | d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1)); |
1478 | 4242b1bd | balrog | d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3)); |
1479 | 4242b1bd | balrog | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5))); |
1480 | 4242b1bd | balrog | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7))); |
1481 | 4242b1bd | balrog | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1)); |
1482 | 4242b1bd | balrog | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3)); |
1483 | 4242b1bd | balrog | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5))); |
1484 | 4242b1bd | balrog | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7))); |
1485 | 4242b1bd | balrog | } |
1486 | 4242b1bd | balrog | |
1487 | e01d9d31 | Blue Swirl | #define FABSB(_, x) (x > INT8_MAX ? -(int8_t)x : x)
|
1488 | e01d9d31 | Blue Swirl | #define FABSW(_, x) (x > INT16_MAX ? -(int16_t)x : x)
|
1489 | e01d9d31 | Blue Swirl | #define FABSL(_, x) (x > INT32_MAX ? -(int32_t)x : x)
|
1490 | 4242b1bd | balrog | SSE_HELPER_B(helper_pabsb, FABSB) |
1491 | 4242b1bd | balrog | SSE_HELPER_W(helper_pabsw, FABSW) |
1492 | 4242b1bd | balrog | SSE_HELPER_L(helper_pabsd, FABSL) |
1493 | 4242b1bd | balrog | |
1494 | e01d9d31 | Blue Swirl | #define FMULHRSW(d, s) (((int16_t) d * (int16_t)s + 0x4000) >> 15) |
1495 | 4242b1bd | balrog | SSE_HELPER_W(helper_pmulhrsw, FMULHRSW) |
1496 | 4242b1bd | balrog | |
1497 | e01d9d31 | Blue Swirl | #define FSIGNB(d, s) (s <= INT8_MAX ? s ? d : 0 : -(int8_t)d) |
1498 | e01d9d31 | Blue Swirl | #define FSIGNW(d, s) (s <= INT16_MAX ? s ? d : 0 : -(int16_t)d) |
1499 | e01d9d31 | Blue Swirl | #define FSIGNL(d, s) (s <= INT32_MAX ? s ? d : 0 : -(int32_t)d) |
1500 | 4242b1bd | balrog | SSE_HELPER_B(helper_psignb, FSIGNB) |
1501 | 4242b1bd | balrog | SSE_HELPER_W(helper_psignw, FSIGNW) |
1502 | 4242b1bd | balrog | SSE_HELPER_L(helper_psignd, FSIGNL) |
1503 | 4242b1bd | balrog | |
1504 | d3eb5eae | Blue Swirl | void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1505 | d3eb5eae | Blue Swirl | int32_t shift) |
1506 | 4242b1bd | balrog | { |
1507 | 4242b1bd | balrog | Reg r; |
1508 | 4242b1bd | balrog | |
1509 | 4242b1bd | balrog | /* XXX could be checked during translation */
|
1510 | 4242b1bd | balrog | if (shift >= (16 << SHIFT)) { |
1511 | 4242b1bd | balrog | r.Q(0) = 0; |
1512 | 4242b1bd | balrog | XMM_ONLY(r.Q(1) = 0); |
1513 | 4242b1bd | balrog | } else {
|
1514 | 4242b1bd | balrog | shift <<= 3;
|
1515 | 4242b1bd | balrog | #define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0) |
1516 | 4242b1bd | balrog | #if SHIFT == 0 |
1517 | e01d9d31 | Blue Swirl | r.Q(0) = SHR(s->Q(0), shift - 0) | |
1518 | e01d9d31 | Blue Swirl | SHR(d->Q(0), shift - 64); |
1519 | 4242b1bd | balrog | #else
|
1520 | e01d9d31 | Blue Swirl | r.Q(0) = SHR(s->Q(0), shift - 0) | |
1521 | e01d9d31 | Blue Swirl | SHR(s->Q(1), shift - 64) | |
1522 | e01d9d31 | Blue Swirl | SHR(d->Q(0), shift - 128) | |
1523 | e01d9d31 | Blue Swirl | SHR(d->Q(1), shift - 192); |
1524 | e01d9d31 | Blue Swirl | r.Q(1) = SHR(s->Q(0), shift + 64) | |
1525 | e01d9d31 | Blue Swirl | SHR(s->Q(1), shift - 0) | |
1526 | e01d9d31 | Blue Swirl | SHR(d->Q(0), shift - 64) | |
1527 | e01d9d31 | Blue Swirl | SHR(d->Q(1), shift - 128); |
1528 | 4242b1bd | balrog | #endif
|
1529 | 4242b1bd | balrog | #undef SHR
|
1530 | 4242b1bd | balrog | } |
1531 | 4242b1bd | balrog | |
1532 | 4242b1bd | balrog | *d = r; |
1533 | 4242b1bd | balrog | } |
1534 | 4242b1bd | balrog | |
1535 | e01d9d31 | Blue Swirl | #define XMM0 (env->xmm_regs[0]) |
1536 | 222a3336 | balrog | |
1537 | 222a3336 | balrog | #if SHIFT == 1 |
1538 | e01d9d31 | Blue Swirl | #define SSE_HELPER_V(name, elem, num, F) \
|
1539 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
|
1540 | e01d9d31 | Blue Swirl | { \ |
1541 | e01d9d31 | Blue Swirl | d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0)); \ |
1542 | e01d9d31 | Blue Swirl | d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1)); \ |
1543 | e01d9d31 | Blue Swirl | if (num > 2) { \ |
1544 | e01d9d31 | Blue Swirl | d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2)); \ |
1545 | e01d9d31 | Blue Swirl | d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3)); \ |
1546 | e01d9d31 | Blue Swirl | if (num > 4) { \ |
1547 | e01d9d31 | Blue Swirl | d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4)); \ |
1548 | e01d9d31 | Blue Swirl | d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5)); \ |
1549 | e01d9d31 | Blue Swirl | d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6)); \ |
1550 | e01d9d31 | Blue Swirl | d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7)); \ |
1551 | e01d9d31 | Blue Swirl | if (num > 8) { \ |
1552 | e01d9d31 | Blue Swirl | d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8)); \ |
1553 | e01d9d31 | Blue Swirl | d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9)); \ |
1554 | e01d9d31 | Blue Swirl | d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10)); \ |
1555 | e01d9d31 | Blue Swirl | d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11)); \ |
1556 | e01d9d31 | Blue Swirl | d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12)); \ |
1557 | e01d9d31 | Blue Swirl | d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13)); \ |
1558 | e01d9d31 | Blue Swirl | d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14)); \ |
1559 | e01d9d31 | Blue Swirl | d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15)); \ |
1560 | e01d9d31 | Blue Swirl | } \ |
1561 | e01d9d31 | Blue Swirl | } \ |
1562 | e01d9d31 | Blue Swirl | } \ |
1563 | e01d9d31 | Blue Swirl | } |
1564 | e01d9d31 | Blue Swirl | |
1565 | e01d9d31 | Blue Swirl | #define SSE_HELPER_I(name, elem, num, F) \
|
1566 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t imm) \
|
1567 | e01d9d31 | Blue Swirl | { \ |
1568 | e01d9d31 | Blue Swirl | d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1)); \ |
1569 | e01d9d31 | Blue Swirl | d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1)); \ |
1570 | e01d9d31 | Blue Swirl | if (num > 2) { \ |
1571 | e01d9d31 | Blue Swirl | d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1)); \ |
1572 | e01d9d31 | Blue Swirl | d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1)); \ |
1573 | e01d9d31 | Blue Swirl | if (num > 4) { \ |
1574 | e01d9d31 | Blue Swirl | d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1)); \ |
1575 | e01d9d31 | Blue Swirl | d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1)); \ |
1576 | e01d9d31 | Blue Swirl | d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1)); \ |
1577 | e01d9d31 | Blue Swirl | d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1)); \ |
1578 | e01d9d31 | Blue Swirl | if (num > 8) { \ |
1579 | e01d9d31 | Blue Swirl | d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1)); \ |
1580 | e01d9d31 | Blue Swirl | d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1)); \ |
1581 | e01d9d31 | Blue Swirl | d->elem(10) = F(d->elem(10), s->elem(10), \ |
1582 | e01d9d31 | Blue Swirl | ((imm >> 10) & 1)); \ |
1583 | e01d9d31 | Blue Swirl | d->elem(11) = F(d->elem(11), s->elem(11), \ |
1584 | e01d9d31 | Blue Swirl | ((imm >> 11) & 1)); \ |
1585 | e01d9d31 | Blue Swirl | d->elem(12) = F(d->elem(12), s->elem(12), \ |
1586 | e01d9d31 | Blue Swirl | ((imm >> 12) & 1)); \ |
1587 | e01d9d31 | Blue Swirl | d->elem(13) = F(d->elem(13), s->elem(13), \ |
1588 | e01d9d31 | Blue Swirl | ((imm >> 13) & 1)); \ |
1589 | e01d9d31 | Blue Swirl | d->elem(14) = F(d->elem(14), s->elem(14), \ |
1590 | e01d9d31 | Blue Swirl | ((imm >> 14) & 1)); \ |
1591 | e01d9d31 | Blue Swirl | d->elem(15) = F(d->elem(15), s->elem(15), \ |
1592 | e01d9d31 | Blue Swirl | ((imm >> 15) & 1)); \ |
1593 | e01d9d31 | Blue Swirl | } \ |
1594 | e01d9d31 | Blue Swirl | } \ |
1595 | e01d9d31 | Blue Swirl | } \ |
1596 | e01d9d31 | Blue Swirl | } |
1597 | 222a3336 | balrog | |
1598 | 222a3336 | balrog | /* SSE4.1 op helpers */
|
1599 | e01d9d31 | Blue Swirl | #define FBLENDVB(d, s, m) ((m & 0x80) ? s : d) |
1600 | e01d9d31 | Blue Swirl | #define FBLENDVPS(d, s, m) ((m & 0x80000000) ? s : d) |
1601 | e01d9d31 | Blue Swirl | #define FBLENDVPD(d, s, m) ((m & 0x8000000000000000LL) ? s : d) |
1602 | 222a3336 | balrog | SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB)
|
1603 | 222a3336 | balrog | SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS)
|
1604 | 222a3336 | balrog | SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD)
|
1605 | 222a3336 | balrog | |
1606 | d3eb5eae | Blue Swirl | void glue(helper_ptest, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1607 | 222a3336 | balrog | { |
1608 | 222a3336 | balrog | uint64_t zf = (s->Q(0) & d->Q(0)) | (s->Q(1) & d->Q(1)); |
1609 | 222a3336 | balrog | uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1)); |
1610 | 222a3336 | balrog | |
1611 | 222a3336 | balrog | CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C); |
1612 | 222a3336 | balrog | } |
1613 | 222a3336 | balrog | |
1614 | e01d9d31 | Blue Swirl | #define SSE_HELPER_F(name, elem, num, F) \
|
1615 | d3eb5eae | Blue Swirl | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
|
1616 | e01d9d31 | Blue Swirl | { \ |
1617 | e01d9d31 | Blue Swirl | d->elem(0) = F(0); \ |
1618 | e01d9d31 | Blue Swirl | d->elem(1) = F(1); \ |
1619 | e01d9d31 | Blue Swirl | if (num > 2) { \ |
1620 | e01d9d31 | Blue Swirl | d->elem(2) = F(2); \ |
1621 | e01d9d31 | Blue Swirl | d->elem(3) = F(3); \ |
1622 | e01d9d31 | Blue Swirl | if (num > 4) { \ |
1623 | e01d9d31 | Blue Swirl | d->elem(4) = F(4); \ |
1624 | e01d9d31 | Blue Swirl | d->elem(5) = F(5); \ |
1625 | e01d9d31 | Blue Swirl | d->elem(6) = F(6); \ |
1626 | e01d9d31 | Blue Swirl | d->elem(7) = F(7); \ |
1627 | e01d9d31 | Blue Swirl | } \ |
1628 | e01d9d31 | Blue Swirl | } \ |
1629 | e01d9d31 | Blue Swirl | } |
1630 | 222a3336 | balrog | |
1631 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B)
|
1632 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B)
|
1633 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B)
|
1634 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W)
|
1635 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W)
|
1636 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L)
|
1637 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B)
|
1638 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B)
|
1639 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B)
|
1640 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W)
|
1641 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W)
|
1642 | 222a3336 | balrog | SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L)
|
1643 | 222a3336 | balrog | |
1644 | d3eb5eae | Blue Swirl | void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1645 | 222a3336 | balrog | { |
1646 | e01d9d31 | Blue Swirl | d->Q(0) = (int64_t)(int32_t) d->L(0) * (int32_t) s->L(0); |
1647 | e01d9d31 | Blue Swirl | d->Q(1) = (int64_t)(int32_t) d->L(2) * (int32_t) s->L(2); |
1648 | 222a3336 | balrog | } |
1649 | 222a3336 | balrog | |
1650 | e01d9d31 | Blue Swirl | #define FCMPEQQ(d, s) (d == s ? -1 : 0) |
1651 | 222a3336 | balrog | SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ) |
1652 | 222a3336 | balrog | |
1653 | d3eb5eae | Blue Swirl | void glue(helper_packusdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1654 | 222a3336 | balrog | { |
1655 | 222a3336 | balrog | d->W(0) = satuw((int32_t) d->L(0)); |
1656 | 222a3336 | balrog | d->W(1) = satuw((int32_t) d->L(1)); |
1657 | 222a3336 | balrog | d->W(2) = satuw((int32_t) d->L(2)); |
1658 | 222a3336 | balrog | d->W(3) = satuw((int32_t) d->L(3)); |
1659 | 222a3336 | balrog | d->W(4) = satuw((int32_t) s->L(0)); |
1660 | 222a3336 | balrog | d->W(5) = satuw((int32_t) s->L(1)); |
1661 | 222a3336 | balrog | d->W(6) = satuw((int32_t) s->L(2)); |
1662 | 222a3336 | balrog | d->W(7) = satuw((int32_t) s->L(3)); |
1663 | 222a3336 | balrog | } |
1664 | 222a3336 | balrog | |
1665 | e01d9d31 | Blue Swirl | #define FMINSB(d, s) MIN((int8_t)d, (int8_t)s)
|
1666 | e01d9d31 | Blue Swirl | #define FMINSD(d, s) MIN((int32_t)d, (int32_t)s)
|
1667 | e01d9d31 | Blue Swirl | #define FMAXSB(d, s) MAX((int8_t)d, (int8_t)s)
|
1668 | e01d9d31 | Blue Swirl | #define FMAXSD(d, s) MAX((int32_t)d, (int32_t)s)
|
1669 | 222a3336 | balrog | SSE_HELPER_B(helper_pminsb, FMINSB) |
1670 | 222a3336 | balrog | SSE_HELPER_L(helper_pminsd, FMINSD) |
1671 | 222a3336 | balrog | SSE_HELPER_W(helper_pminuw, MIN) |
1672 | 222a3336 | balrog | SSE_HELPER_L(helper_pminud, MIN) |
1673 | 222a3336 | balrog | SSE_HELPER_B(helper_pmaxsb, FMAXSB) |
1674 | 222a3336 | balrog | SSE_HELPER_L(helper_pmaxsd, FMAXSD) |
1675 | 222a3336 | balrog | SSE_HELPER_W(helper_pmaxuw, MAX) |
1676 | 222a3336 | balrog | SSE_HELPER_L(helper_pmaxud, MAX) |
1677 | 222a3336 | balrog | |
1678 | e01d9d31 | Blue Swirl | #define FMULLD(d, s) ((int32_t)d * (int32_t)s)
|
1679 | 222a3336 | balrog | SSE_HELPER_L(helper_pmulld, FMULLD) |
1680 | 222a3336 | balrog | |
1681 | d3eb5eae | Blue Swirl | void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
1682 | 222a3336 | balrog | { |
1683 | 222a3336 | balrog | int idx = 0; |
1684 | 222a3336 | balrog | |
1685 | e01d9d31 | Blue Swirl | if (s->W(1) < s->W(idx)) { |
1686 | 222a3336 | balrog | idx = 1;
|
1687 | e01d9d31 | Blue Swirl | } |
1688 | e01d9d31 | Blue Swirl | if (s->W(2) < s->W(idx)) { |
1689 | 222a3336 | balrog | idx = 2;
|
1690 | e01d9d31 | Blue Swirl | } |
1691 | e01d9d31 | Blue Swirl | if (s->W(3) < s->W(idx)) { |
1692 | 222a3336 | balrog | idx = 3;
|
1693 | e01d9d31 | Blue Swirl | } |
1694 | e01d9d31 | Blue Swirl | if (s->W(4) < s->W(idx)) { |
1695 | 222a3336 | balrog | idx = 4;
|
1696 | e01d9d31 | Blue Swirl | } |
1697 | e01d9d31 | Blue Swirl | if (s->W(5) < s->W(idx)) { |
1698 | 222a3336 | balrog | idx = 5;
|
1699 | e01d9d31 | Blue Swirl | } |
1700 | e01d9d31 | Blue Swirl | if (s->W(6) < s->W(idx)) { |
1701 | 222a3336 | balrog | idx = 6;
|
1702 | e01d9d31 | Blue Swirl | } |
1703 | e01d9d31 | Blue Swirl | if (s->W(7) < s->W(idx)) { |
1704 | 222a3336 | balrog | idx = 7;
|
1705 | e01d9d31 | Blue Swirl | } |
1706 | 222a3336 | balrog | |
1707 | 222a3336 | balrog | d->Q(1) = 0; |
1708 | 222a3336 | balrog | d->L(1) = 0; |
1709 | 222a3336 | balrog | d->W(1) = idx;
|
1710 | 222a3336 | balrog | d->W(0) = s->W(idx);
|
1711 | 222a3336 | balrog | } |
1712 | 222a3336 | balrog | |
1713 | d3eb5eae | Blue Swirl | void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1714 | d3eb5eae | Blue Swirl | uint32_t mode) |
1715 | 222a3336 | balrog | { |
1716 | 222a3336 | balrog | signed char prev_rounding_mode; |
1717 | 222a3336 | balrog | |
1718 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1719 | e01d9d31 | Blue Swirl | if (!(mode & (1 << 2))) { |
1720 | 222a3336 | balrog | switch (mode & 3) { |
1721 | 222a3336 | balrog | case 0: |
1722 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1723 | 222a3336 | balrog | break;
|
1724 | 222a3336 | balrog | case 1: |
1725 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1726 | 222a3336 | balrog | break;
|
1727 | 222a3336 | balrog | case 2: |
1728 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1729 | 222a3336 | balrog | break;
|
1730 | 222a3336 | balrog | case 3: |
1731 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1732 | 222a3336 | balrog | break;
|
1733 | 222a3336 | balrog | } |
1734 | e01d9d31 | Blue Swirl | } |
1735 | 222a3336 | balrog | |
1736 | adc71666 | Aurelien Jarno | d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); |
1737 | adc71666 | Aurelien Jarno | d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status); |
1738 | adc71666 | Aurelien Jarno | d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status); |
1739 | adc71666 | Aurelien Jarno | d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status); |
1740 | 222a3336 | balrog | |
1741 | 222a3336 | balrog | #if 0 /* TODO */
|
1742 | e01d9d31 | Blue Swirl | if (mode & (1 << 3)) {
|
1743 | e01d9d31 | Blue Swirl | set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
|
1744 | e01d9d31 | Blue Swirl | ~float_flag_inexact,
|
1745 | e01d9d31 | Blue Swirl | &env->sse_status);
|
1746 | e01d9d31 | Blue Swirl | }
|
1747 | 222a3336 | balrog | #endif
|
1748 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1749 | 222a3336 | balrog | } |
1750 | 222a3336 | balrog | |
1751 | d3eb5eae | Blue Swirl | void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1752 | d3eb5eae | Blue Swirl | uint32_t mode) |
1753 | 222a3336 | balrog | { |
1754 | 222a3336 | balrog | signed char prev_rounding_mode; |
1755 | 222a3336 | balrog | |
1756 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1757 | e01d9d31 | Blue Swirl | if (!(mode & (1 << 2))) { |
1758 | 222a3336 | balrog | switch (mode & 3) { |
1759 | 222a3336 | balrog | case 0: |
1760 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1761 | 222a3336 | balrog | break;
|
1762 | 222a3336 | balrog | case 1: |
1763 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1764 | 222a3336 | balrog | break;
|
1765 | 222a3336 | balrog | case 2: |
1766 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1767 | 222a3336 | balrog | break;
|
1768 | 222a3336 | balrog | case 3: |
1769 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1770 | 222a3336 | balrog | break;
|
1771 | 222a3336 | balrog | } |
1772 | e01d9d31 | Blue Swirl | } |
1773 | 222a3336 | balrog | |
1774 | adc71666 | Aurelien Jarno | d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); |
1775 | adc71666 | Aurelien Jarno | d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status); |
1776 | 222a3336 | balrog | |
1777 | 222a3336 | balrog | #if 0 /* TODO */
|
1778 | e01d9d31 | Blue Swirl | if (mode & (1 << 3)) {
|
1779 | e01d9d31 | Blue Swirl | set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
|
1780 | e01d9d31 | Blue Swirl | ~float_flag_inexact,
|
1781 | e01d9d31 | Blue Swirl | &env->sse_status);
|
1782 | e01d9d31 | Blue Swirl | }
|
1783 | 222a3336 | balrog | #endif
|
1784 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1785 | 222a3336 | balrog | } |
1786 | 222a3336 | balrog | |
1787 | d3eb5eae | Blue Swirl | void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1788 | d3eb5eae | Blue Swirl | uint32_t mode) |
1789 | 222a3336 | balrog | { |
1790 | 222a3336 | balrog | signed char prev_rounding_mode; |
1791 | 222a3336 | balrog | |
1792 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1793 | e01d9d31 | Blue Swirl | if (!(mode & (1 << 2))) { |
1794 | 222a3336 | balrog | switch (mode & 3) { |
1795 | 222a3336 | balrog | case 0: |
1796 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1797 | 222a3336 | balrog | break;
|
1798 | 222a3336 | balrog | case 1: |
1799 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1800 | 222a3336 | balrog | break;
|
1801 | 222a3336 | balrog | case 2: |
1802 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1803 | 222a3336 | balrog | break;
|
1804 | 222a3336 | balrog | case 3: |
1805 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1806 | 222a3336 | balrog | break;
|
1807 | 222a3336 | balrog | } |
1808 | e01d9d31 | Blue Swirl | } |
1809 | 222a3336 | balrog | |
1810 | adc71666 | Aurelien Jarno | d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); |
1811 | 222a3336 | balrog | |
1812 | 222a3336 | balrog | #if 0 /* TODO */
|
1813 | e01d9d31 | Blue Swirl | if (mode & (1 << 3)) {
|
1814 | e01d9d31 | Blue Swirl | set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
|
1815 | e01d9d31 | Blue Swirl | ~float_flag_inexact,
|
1816 | e01d9d31 | Blue Swirl | &env->sse_status);
|
1817 | e01d9d31 | Blue Swirl | }
|
1818 | 222a3336 | balrog | #endif
|
1819 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1820 | 222a3336 | balrog | } |
1821 | 222a3336 | balrog | |
1822 | d3eb5eae | Blue Swirl | void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1823 | d3eb5eae | Blue Swirl | uint32_t mode) |
1824 | 222a3336 | balrog | { |
1825 | 222a3336 | balrog | signed char prev_rounding_mode; |
1826 | 222a3336 | balrog | |
1827 | 222a3336 | balrog | prev_rounding_mode = env->sse_status.float_rounding_mode; |
1828 | e01d9d31 | Blue Swirl | if (!(mode & (1 << 2))) { |
1829 | 222a3336 | balrog | switch (mode & 3) { |
1830 | 222a3336 | balrog | case 0: |
1831 | 222a3336 | balrog | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
1832 | 222a3336 | balrog | break;
|
1833 | 222a3336 | balrog | case 1: |
1834 | 222a3336 | balrog | set_float_rounding_mode(float_round_down, &env->sse_status); |
1835 | 222a3336 | balrog | break;
|
1836 | 222a3336 | balrog | case 2: |
1837 | 222a3336 | balrog | set_float_rounding_mode(float_round_up, &env->sse_status); |
1838 | 222a3336 | balrog | break;
|
1839 | 222a3336 | balrog | case 3: |
1840 | 222a3336 | balrog | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
1841 | 222a3336 | balrog | break;
|
1842 | 222a3336 | balrog | } |
1843 | e01d9d31 | Blue Swirl | } |
1844 | 222a3336 | balrog | |
1845 | adc71666 | Aurelien Jarno | d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); |
1846 | 222a3336 | balrog | |
1847 | 222a3336 | balrog | #if 0 /* TODO */
|
1848 | e01d9d31 | Blue Swirl | if (mode & (1 << 3)) {
|
1849 | e01d9d31 | Blue Swirl | set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
|
1850 | e01d9d31 | Blue Swirl | ~float_flag_inexact,
|
1851 | e01d9d31 | Blue Swirl | &env->sse_status);
|
1852 | e01d9d31 | Blue Swirl | }
|
1853 | 222a3336 | balrog | #endif
|
1854 | 222a3336 | balrog | env->sse_status.float_rounding_mode = prev_rounding_mode; |
1855 | 222a3336 | balrog | } |
1856 | 222a3336 | balrog | |
1857 | e01d9d31 | Blue Swirl | #define FBLENDP(d, s, m) (m ? s : d)
|
1858 | 222a3336 | balrog | SSE_HELPER_I(helper_blendps, L, 4, FBLENDP)
|
1859 | 222a3336 | balrog | SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP)
|
1860 | 222a3336 | balrog | SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP)
|
1861 | 222a3336 | balrog | |
1862 | d3eb5eae | Blue Swirl | void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
|
1863 | 222a3336 | balrog | { |
1864 | 170d5b4b | Aurelien Jarno | float32 iresult = float32_zero; |
1865 | 222a3336 | balrog | |
1866 | e01d9d31 | Blue Swirl | if (mask & (1 << 4)) { |
1867 | 222a3336 | balrog | iresult = float32_add(iresult, |
1868 | e01d9d31 | Blue Swirl | float32_mul(d->XMM_S(0), s->XMM_S(0), |
1869 | e01d9d31 | Blue Swirl | &env->sse_status), |
1870 | e01d9d31 | Blue Swirl | &env->sse_status); |
1871 | e01d9d31 | Blue Swirl | } |
1872 | e01d9d31 | Blue Swirl | if (mask & (1 << 5)) { |
1873 | 222a3336 | balrog | iresult = float32_add(iresult, |
1874 | e01d9d31 | Blue Swirl | float32_mul(d->XMM_S(1), s->XMM_S(1), |
1875 | e01d9d31 | Blue Swirl | &env->sse_status), |
1876 | e01d9d31 | Blue Swirl | &env->sse_status); |
1877 | e01d9d31 | Blue Swirl | } |
1878 | e01d9d31 | Blue Swirl | if (mask & (1 << 6)) { |
1879 | 222a3336 | balrog | iresult = float32_add(iresult, |
1880 | e01d9d31 | Blue Swirl | float32_mul(d->XMM_S(2), s->XMM_S(2), |
1881 | e01d9d31 | Blue Swirl | &env->sse_status), |
1882 | e01d9d31 | Blue Swirl | &env->sse_status); |
1883 | e01d9d31 | Blue Swirl | } |
1884 | e01d9d31 | Blue Swirl | if (mask & (1 << 7)) { |
1885 | 222a3336 | balrog | iresult = float32_add(iresult, |
1886 | e01d9d31 | Blue Swirl | float32_mul(d->XMM_S(3), s->XMM_S(3), |
1887 | e01d9d31 | Blue Swirl | &env->sse_status), |
1888 | e01d9d31 | Blue Swirl | &env->sse_status); |
1889 | e01d9d31 | Blue Swirl | } |
1890 | 170d5b4b | Aurelien Jarno | d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero; |
1891 | 170d5b4b | Aurelien Jarno | d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero; |
1892 | 170d5b4b | Aurelien Jarno | d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero; |
1893 | 170d5b4b | Aurelien Jarno | d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero; |
1894 | 222a3336 | balrog | } |
1895 | 222a3336 | balrog | |
1896 | d3eb5eae | Blue Swirl | void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
|
1897 | 222a3336 | balrog | { |
1898 | 170d5b4b | Aurelien Jarno | float64 iresult = float64_zero; |
1899 | 222a3336 | balrog | |
1900 | e01d9d31 | Blue Swirl | if (mask & (1 << 4)) { |
1901 | 222a3336 | balrog | iresult = float64_add(iresult, |
1902 | e01d9d31 | Blue Swirl | float64_mul(d->XMM_D(0), s->XMM_D(0), |
1903 | e01d9d31 | Blue Swirl | &env->sse_status), |
1904 | e01d9d31 | Blue Swirl | &env->sse_status); |
1905 | e01d9d31 | Blue Swirl | } |
1906 | e01d9d31 | Blue Swirl | if (mask & (1 << 5)) { |
1907 | 222a3336 | balrog | iresult = float64_add(iresult, |
1908 | e01d9d31 | Blue Swirl | float64_mul(d->XMM_D(1), s->XMM_D(1), |
1909 | e01d9d31 | Blue Swirl | &env->sse_status), |
1910 | e01d9d31 | Blue Swirl | &env->sse_status); |
1911 | e01d9d31 | Blue Swirl | } |
1912 | 170d5b4b | Aurelien Jarno | d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero; |
1913 | 170d5b4b | Aurelien Jarno | d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero; |
1914 | 222a3336 | balrog | } |
1915 | 222a3336 | balrog | |
1916 | d3eb5eae | Blue Swirl | void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
1917 | d3eb5eae | Blue Swirl | uint32_t offset) |
1918 | 222a3336 | balrog | { |
1919 | 222a3336 | balrog | int s0 = (offset & 3) << 2; |
1920 | 222a3336 | balrog | int d0 = (offset & 4) << 0; |
1921 | 222a3336 | balrog | int i;
|
1922 | 222a3336 | balrog | Reg r; |
1923 | 222a3336 | balrog | |
1924 | 222a3336 | balrog | for (i = 0; i < 8; i++, d0++) { |
1925 | 222a3336 | balrog | r.W(i) = 0;
|
1926 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0)); |
1927 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1)); |
1928 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2)); |
1929 | 222a3336 | balrog | r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3)); |
1930 | 222a3336 | balrog | } |
1931 | 222a3336 | balrog | |
1932 | 222a3336 | balrog | *d = r; |
1933 | 222a3336 | balrog | } |
1934 | 222a3336 | balrog | |
1935 | 222a3336 | balrog | /* SSE4.2 op helpers */
|
1936 | da5156cd | Aurelien Jarno | #define FCMPGTQ(d, s) ((int64_t)d > (int64_t)s ? -1 : 0) |
1937 | 222a3336 | balrog | SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ) |
1938 | 222a3336 | balrog | |
1939 | d3eb5eae | Blue Swirl | static inline int pcmp_elen(CPUX86State *env, int reg, uint32_t ctrl) |
1940 | 222a3336 | balrog | { |
1941 | 222a3336 | balrog | int val;
|
1942 | 222a3336 | balrog | |
1943 | 222a3336 | balrog | /* Presence of REX.W is indicated by a bit higher than 7 set */
|
1944 | e01d9d31 | Blue Swirl | if (ctrl >> 8) { |
1945 | e01d9d31 | Blue Swirl | val = abs1((int64_t)env->regs[reg]); |
1946 | e01d9d31 | Blue Swirl | } else {
|
1947 | e01d9d31 | Blue Swirl | val = abs1((int32_t)env->regs[reg]); |
1948 | e01d9d31 | Blue Swirl | } |
1949 | 222a3336 | balrog | |
1950 | 222a3336 | balrog | if (ctrl & 1) { |
1951 | e01d9d31 | Blue Swirl | if (val > 8) { |
1952 | 222a3336 | balrog | return 8; |
1953 | e01d9d31 | Blue Swirl | } |
1954 | e01d9d31 | Blue Swirl | } else {
|
1955 | e01d9d31 | Blue Swirl | if (val > 16) { |
1956 | 222a3336 | balrog | return 16; |
1957 | e01d9d31 | Blue Swirl | } |
1958 | e01d9d31 | Blue Swirl | } |
1959 | 222a3336 | balrog | return val;
|
1960 | 222a3336 | balrog | } |
1961 | 222a3336 | balrog | |
1962 | 222a3336 | balrog | static inline int pcmp_ilen(Reg *r, uint8_t ctrl) |
1963 | 222a3336 | balrog | { |
1964 | 222a3336 | balrog | int val = 0; |
1965 | 222a3336 | balrog | |
1966 | 222a3336 | balrog | if (ctrl & 1) { |
1967 | e01d9d31 | Blue Swirl | while (val < 8 && r->W(val)) { |
1968 | 222a3336 | balrog | val++; |
1969 | e01d9d31 | Blue Swirl | } |
1970 | e01d9d31 | Blue Swirl | } else {
|
1971 | e01d9d31 | Blue Swirl | while (val < 16 && r->B(val)) { |
1972 | 222a3336 | balrog | val++; |
1973 | e01d9d31 | Blue Swirl | } |
1974 | e01d9d31 | Blue Swirl | } |
1975 | 222a3336 | balrog | |
1976 | 222a3336 | balrog | return val;
|
1977 | 222a3336 | balrog | } |
1978 | 222a3336 | balrog | |
1979 | 222a3336 | balrog | static inline int pcmp_val(Reg *r, uint8_t ctrl, int i) |
1980 | 222a3336 | balrog | { |
1981 | 222a3336 | balrog | switch ((ctrl >> 0) & 3) { |
1982 | 222a3336 | balrog | case 0: |
1983 | 222a3336 | balrog | return r->B(i);
|
1984 | 222a3336 | balrog | case 1: |
1985 | 222a3336 | balrog | return r->W(i);
|
1986 | 222a3336 | balrog | case 2: |
1987 | e01d9d31 | Blue Swirl | return (int8_t)r->B(i);
|
1988 | 222a3336 | balrog | case 3: |
1989 | 222a3336 | balrog | default:
|
1990 | e01d9d31 | Blue Swirl | return (int16_t)r->W(i);
|
1991 | 222a3336 | balrog | } |
1992 | 222a3336 | balrog | } |
1993 | 222a3336 | balrog | |
1994 | d3eb5eae | Blue Swirl | static inline unsigned pcmpxstrx(CPUX86State *env, Reg *d, Reg *s, |
1995 | e01d9d31 | Blue Swirl | int8_t ctrl, int valids, int validd) |
1996 | 222a3336 | balrog | { |
1997 | 222a3336 | balrog | unsigned int res = 0; |
1998 | 222a3336 | balrog | int v;
|
1999 | 222a3336 | balrog | int j, i;
|
2000 | 222a3336 | balrog | int upper = (ctrl & 1) ? 7 : 15; |
2001 | 222a3336 | balrog | |
2002 | 222a3336 | balrog | valids--; |
2003 | 222a3336 | balrog | validd--; |
2004 | 222a3336 | balrog | |
2005 | 222a3336 | balrog | CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0); |
2006 | 222a3336 | balrog | |
2007 | 222a3336 | balrog | switch ((ctrl >> 2) & 3) { |
2008 | 222a3336 | balrog | case 0: |
2009 | 222a3336 | balrog | for (j = valids; j >= 0; j--) { |
2010 | 222a3336 | balrog | res <<= 1;
|
2011 | 222a3336 | balrog | v = pcmp_val(s, ctrl, j); |
2012 | e01d9d31 | Blue Swirl | for (i = validd; i >= 0; i--) { |
2013 | 222a3336 | balrog | res |= (v == pcmp_val(d, ctrl, i)); |
2014 | e01d9d31 | Blue Swirl | } |
2015 | 222a3336 | balrog | } |
2016 | 222a3336 | balrog | break;
|
2017 | 222a3336 | balrog | case 1: |
2018 | 222a3336 | balrog | for (j = valids; j >= 0; j--) { |
2019 | 222a3336 | balrog | res <<= 1;
|
2020 | 222a3336 | balrog | v = pcmp_val(s, ctrl, j); |
2021 | e01d9d31 | Blue Swirl | for (i = ((validd - 1) | 1); i >= 0; i -= 2) { |
2022 | 649ad05e | Aurelien Jarno | res |= (pcmp_val(d, ctrl, i - 0) >= v &&
|
2023 | 649ad05e | Aurelien Jarno | pcmp_val(d, ctrl, i - 1) <= v);
|
2024 | e01d9d31 | Blue Swirl | } |
2025 | 222a3336 | balrog | } |
2026 | 222a3336 | balrog | break;
|
2027 | 222a3336 | balrog | case 2: |
2028 | b27a6cac | Aurelien Jarno | res = (1 << (upper - MAX(valids, validd))) - 1; |
2029 | 222a3336 | balrog | res <<= MAX(valids, validd) - MIN(valids, validd); |
2030 | 222a3336 | balrog | for (i = MIN(valids, validd); i >= 0; i--) { |
2031 | 222a3336 | balrog | res <<= 1;
|
2032 | 222a3336 | balrog | v = pcmp_val(s, ctrl, i); |
2033 | 222a3336 | balrog | res |= (v == pcmp_val(d, ctrl, i)); |
2034 | 222a3336 | balrog | } |
2035 | 222a3336 | balrog | break;
|
2036 | 222a3336 | balrog | case 3: |
2037 | 222a3336 | balrog | for (j = valids - validd; j >= 0; j--) { |
2038 | 222a3336 | balrog | res <<= 1;
|
2039 | 75c9527e | Aurelien Jarno | v = 1;
|
2040 | e01d9d31 | Blue Swirl | for (i = MIN(upper - j, validd); i >= 0; i--) { |
2041 | 75c9527e | Aurelien Jarno | v &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i)); |
2042 | e01d9d31 | Blue Swirl | } |
2043 | 75c9527e | Aurelien Jarno | res |= v; |
2044 | 222a3336 | balrog | } |
2045 | 222a3336 | balrog | break;
|
2046 | 222a3336 | balrog | } |
2047 | 222a3336 | balrog | |
2048 | 222a3336 | balrog | switch ((ctrl >> 4) & 3) { |
2049 | 222a3336 | balrog | case 1: |
2050 | 222a3336 | balrog | res ^= (2 << upper) - 1; |
2051 | 222a3336 | balrog | break;
|
2052 | 222a3336 | balrog | case 3: |
2053 | e4eba27e | Aurelien Jarno | res ^= (1 << (valids + 1)) - 1; |
2054 | 222a3336 | balrog | break;
|
2055 | 222a3336 | balrog | } |
2056 | 222a3336 | balrog | |
2057 | e01d9d31 | Blue Swirl | if (res) {
|
2058 | e01d9d31 | Blue Swirl | CC_SRC |= CC_C; |
2059 | e01d9d31 | Blue Swirl | } |
2060 | e01d9d31 | Blue Swirl | if (res & 1) { |
2061 | e01d9d31 | Blue Swirl | CC_SRC |= CC_O; |
2062 | e01d9d31 | Blue Swirl | } |
2063 | 222a3336 | balrog | |
2064 | 222a3336 | balrog | return res;
|
2065 | 222a3336 | balrog | } |
2066 | 222a3336 | balrog | |
2067 | d3eb5eae | Blue Swirl | void glue(helper_pcmpestri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2068 | d3eb5eae | Blue Swirl | uint32_t ctrl) |
2069 | 222a3336 | balrog | { |
2070 | d3eb5eae | Blue Swirl | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
2071 | d3eb5eae | Blue Swirl | pcmp_elen(env, R_EDX, ctrl), |
2072 | d3eb5eae | Blue Swirl | pcmp_elen(env, R_EAX, ctrl)); |
2073 | 222a3336 | balrog | |
2074 | e01d9d31 | Blue Swirl | if (res) {
|
2075 | c334a388 | Aurelien Jarno | env->regs[R_ECX] = (ctrl & (1 << 6)) ? 31 - clz32(res) : ctz32(res); |
2076 | e01d9d31 | Blue Swirl | } else {
|
2077 | 222a3336 | balrog | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
2078 | e01d9d31 | Blue Swirl | } |
2079 | 222a3336 | balrog | } |
2080 | 222a3336 | balrog | |
2081 | d3eb5eae | Blue Swirl | void glue(helper_pcmpestrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2082 | d3eb5eae | Blue Swirl | uint32_t ctrl) |
2083 | 222a3336 | balrog | { |
2084 | 222a3336 | balrog | int i;
|
2085 | d3eb5eae | Blue Swirl | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
2086 | d3eb5eae | Blue Swirl | pcmp_elen(env, R_EDX, ctrl), |
2087 | d3eb5eae | Blue Swirl | pcmp_elen(env, R_EAX, ctrl)); |
2088 | 222a3336 | balrog | |
2089 | 222a3336 | balrog | if ((ctrl >> 6) & 1) { |
2090 | e01d9d31 | Blue Swirl | if (ctrl & 1) { |
2091 | bc426899 | Blue Swirl | for (i = 0; i < 8; i++, res >>= 1) { |
2092 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].W(i) = (res & 1) ? ~0 : 0; |
2093 | bc426899 | Blue Swirl | } |
2094 | e01d9d31 | Blue Swirl | } else {
|
2095 | bc426899 | Blue Swirl | for (i = 0; i < 16; i++, res >>= 1) { |
2096 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].B(i) = (res & 1) ? ~0 : 0; |
2097 | bc426899 | Blue Swirl | } |
2098 | e01d9d31 | Blue Swirl | } |
2099 | 222a3336 | balrog | } else {
|
2100 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].Q(1) = 0; |
2101 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].Q(0) = res; |
2102 | 222a3336 | balrog | } |
2103 | 222a3336 | balrog | } |
2104 | 222a3336 | balrog | |
2105 | d3eb5eae | Blue Swirl | void glue(helper_pcmpistri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2106 | d3eb5eae | Blue Swirl | uint32_t ctrl) |
2107 | 222a3336 | balrog | { |
2108 | d3eb5eae | Blue Swirl | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
2109 | e01d9d31 | Blue Swirl | pcmp_ilen(s, ctrl), |
2110 | e01d9d31 | Blue Swirl | pcmp_ilen(d, ctrl)); |
2111 | 222a3336 | balrog | |
2112 | e01d9d31 | Blue Swirl | if (res) {
|
2113 | c334a388 | Aurelien Jarno | env->regs[R_ECX] = (ctrl & (1 << 6)) ? 31 - clz32(res) : ctz32(res); |
2114 | e01d9d31 | Blue Swirl | } else {
|
2115 | 222a3336 | balrog | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
2116 | e01d9d31 | Blue Swirl | } |
2117 | 222a3336 | balrog | } |
2118 | 222a3336 | balrog | |
2119 | d3eb5eae | Blue Swirl | void glue(helper_pcmpistrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2120 | d3eb5eae | Blue Swirl | uint32_t ctrl) |
2121 | 222a3336 | balrog | { |
2122 | 222a3336 | balrog | int i;
|
2123 | d3eb5eae | Blue Swirl | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
2124 | e01d9d31 | Blue Swirl | pcmp_ilen(s, ctrl), |
2125 | e01d9d31 | Blue Swirl | pcmp_ilen(d, ctrl)); |
2126 | 222a3336 | balrog | |
2127 | 222a3336 | balrog | if ((ctrl >> 6) & 1) { |
2128 | e01d9d31 | Blue Swirl | if (ctrl & 1) { |
2129 | bc426899 | Blue Swirl | for (i = 0; i < 8; i++, res >>= 1) { |
2130 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].W(i) = (res & 1) ? ~0 : 0; |
2131 | bc426899 | Blue Swirl | } |
2132 | e01d9d31 | Blue Swirl | } else {
|
2133 | bc426899 | Blue Swirl | for (i = 0; i < 16; i++, res >>= 1) { |
2134 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].B(i) = (res & 1) ? ~0 : 0; |
2135 | bc426899 | Blue Swirl | } |
2136 | e01d9d31 | Blue Swirl | } |
2137 | 222a3336 | balrog | } else {
|
2138 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].Q(1) = 0; |
2139 | 2b8d7e9d | Aurelien Jarno | env->xmm_regs[0].Q(0) = res; |
2140 | 222a3336 | balrog | } |
2141 | 222a3336 | balrog | } |
2142 | 222a3336 | balrog | |
2143 | 222a3336 | balrog | #define CRCPOLY 0x1edc6f41 |
2144 | 222a3336 | balrog | #define CRCPOLY_BITREV 0x82f63b78 |
2145 | 222a3336 | balrog | target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len) |
2146 | 222a3336 | balrog | { |
2147 | 222a3336 | balrog | target_ulong crc = (msg & ((target_ulong) -1 >>
|
2148 | e01d9d31 | Blue Swirl | (TARGET_LONG_BITS - len))) ^ crc1; |
2149 | 222a3336 | balrog | |
2150 | e01d9d31 | Blue Swirl | while (len--) {
|
2151 | 222a3336 | balrog | crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0); |
2152 | e01d9d31 | Blue Swirl | } |
2153 | 222a3336 | balrog | |
2154 | 222a3336 | balrog | return crc;
|
2155 | 222a3336 | balrog | } |
2156 | 222a3336 | balrog | |
2157 | 222a3336 | balrog | #define POPMASK(i) ((target_ulong) -1 / ((1LL << (1 << i)) + 1)) |
2158 | e01d9d31 | Blue Swirl | #define POPCOUNT(n, i) ((n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i))) |
2159 | d3eb5eae | Blue Swirl | target_ulong helper_popcnt(CPUX86State *env, target_ulong n, uint32_t type) |
2160 | 222a3336 | balrog | { |
2161 | 222a3336 | balrog | CC_SRC = n ? 0 : CC_Z;
|
2162 | 222a3336 | balrog | |
2163 | 222a3336 | balrog | n = POPCOUNT(n, 0);
|
2164 | 222a3336 | balrog | n = POPCOUNT(n, 1);
|
2165 | 222a3336 | balrog | n = POPCOUNT(n, 2);
|
2166 | 222a3336 | balrog | n = POPCOUNT(n, 3);
|
2167 | e01d9d31 | Blue Swirl | if (type == 1) { |
2168 | 222a3336 | balrog | return n & 0xff; |
2169 | e01d9d31 | Blue Swirl | } |
2170 | 222a3336 | balrog | |
2171 | 222a3336 | balrog | n = POPCOUNT(n, 4);
|
2172 | 222a3336 | balrog | #ifndef TARGET_X86_64
|
2173 | 222a3336 | balrog | return n;
|
2174 | 222a3336 | balrog | #else
|
2175 | e01d9d31 | Blue Swirl | if (type == 2) { |
2176 | 222a3336 | balrog | return n & 0xff; |
2177 | e01d9d31 | Blue Swirl | } |
2178 | 222a3336 | balrog | |
2179 | 222a3336 | balrog | return POPCOUNT(n, 5); |
2180 | 222a3336 | balrog | #endif
|
2181 | 222a3336 | balrog | } |
2182 | e71827bc | Aurelien Jarno | |
2183 | e71827bc | Aurelien Jarno | void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2184 | e71827bc | Aurelien Jarno | uint32_t ctrl) |
2185 | e71827bc | Aurelien Jarno | { |
2186 | e71827bc | Aurelien Jarno | uint64_t ah, al, b, resh, resl; |
2187 | e71827bc | Aurelien Jarno | |
2188 | e71827bc | Aurelien Jarno | ah = 0;
|
2189 | e71827bc | Aurelien Jarno | al = d->Q((ctrl & 1) != 0); |
2190 | e71827bc | Aurelien Jarno | b = s->Q((ctrl & 16) != 0); |
2191 | e71827bc | Aurelien Jarno | resh = resl = 0;
|
2192 | e71827bc | Aurelien Jarno | |
2193 | e71827bc | Aurelien Jarno | while (b) {
|
2194 | e71827bc | Aurelien Jarno | if (b & 1) { |
2195 | e71827bc | Aurelien Jarno | resl ^= al; |
2196 | e71827bc | Aurelien Jarno | resh ^= ah; |
2197 | e71827bc | Aurelien Jarno | } |
2198 | e71827bc | Aurelien Jarno | ah = (ah << 1) | (al >> 63); |
2199 | e71827bc | Aurelien Jarno | al <<= 1;
|
2200 | e71827bc | Aurelien Jarno | b >>= 1;
|
2201 | e71827bc | Aurelien Jarno | } |
2202 | e71827bc | Aurelien Jarno | |
2203 | e71827bc | Aurelien Jarno | d->Q(0) = resl;
|
2204 | e71827bc | Aurelien Jarno | d->Q(1) = resh;
|
2205 | e71827bc | Aurelien Jarno | } |
2206 | d640045a | Aurelien Jarno | |
2207 | d640045a | Aurelien Jarno | /* AES-NI op helpers */
|
2208 | d640045a | Aurelien Jarno | static const uint8_t aes_shifts[16] = { |
2209 | d640045a | Aurelien Jarno | 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11 |
2210 | d640045a | Aurelien Jarno | }; |
2211 | d640045a | Aurelien Jarno | |
2212 | d640045a | Aurelien Jarno | static const uint8_t aes_ishifts[16] = { |
2213 | d640045a | Aurelien Jarno | 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3 |
2214 | d640045a | Aurelien Jarno | }; |
2215 | d640045a | Aurelien Jarno | |
2216 | d640045a | Aurelien Jarno | void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
2217 | d640045a | Aurelien Jarno | { |
2218 | d640045a | Aurelien Jarno | int i;
|
2219 | d640045a | Aurelien Jarno | Reg st = *d; |
2220 | d640045a | Aurelien Jarno | Reg rk = *s; |
2221 | d640045a | Aurelien Jarno | |
2222 | d640045a | Aurelien Jarno | for (i = 0 ; i < 4 ; i++) { |
2223 | d640045a | Aurelien Jarno | d->L(i) = rk.L(i) ^ bswap32(AES_Td0[st.B(aes_ishifts[4*i+0])] ^ |
2224 | d640045a | Aurelien Jarno | AES_Td1[st.B(aes_ishifts[4*i+1])] ^ |
2225 | d640045a | Aurelien Jarno | AES_Td2[st.B(aes_ishifts[4*i+2])] ^ |
2226 | d640045a | Aurelien Jarno | AES_Td3[st.B(aes_ishifts[4*i+3])]); |
2227 | d640045a | Aurelien Jarno | } |
2228 | d640045a | Aurelien Jarno | } |
2229 | d640045a | Aurelien Jarno | |
2230 | d640045a | Aurelien Jarno | void glue(helper_aesdeclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
2231 | d640045a | Aurelien Jarno | { |
2232 | d640045a | Aurelien Jarno | int i;
|
2233 | d640045a | Aurelien Jarno | Reg st = *d; |
2234 | d640045a | Aurelien Jarno | Reg rk = *s; |
2235 | d640045a | Aurelien Jarno | |
2236 | d640045a | Aurelien Jarno | for (i = 0; i < 16; i++) { |
2237 | d640045a | Aurelien Jarno | d->B(i) = rk.B(i) ^ (AES_Td4[st.B(aes_ishifts[i])] & 0xff);
|
2238 | d640045a | Aurelien Jarno | } |
2239 | d640045a | Aurelien Jarno | } |
2240 | d640045a | Aurelien Jarno | |
2241 | d640045a | Aurelien Jarno | void glue(helper_aesenc, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
2242 | d640045a | Aurelien Jarno | { |
2243 | d640045a | Aurelien Jarno | int i;
|
2244 | d640045a | Aurelien Jarno | Reg st = *d; |
2245 | d640045a | Aurelien Jarno | Reg rk = *s; |
2246 | d640045a | Aurelien Jarno | |
2247 | d640045a | Aurelien Jarno | for (i = 0 ; i < 4 ; i++) { |
2248 | d640045a | Aurelien Jarno | d->L(i) = rk.L(i) ^ bswap32(AES_Te0[st.B(aes_shifts[4*i+0])] ^ |
2249 | d640045a | Aurelien Jarno | AES_Te1[st.B(aes_shifts[4*i+1])] ^ |
2250 | d640045a | Aurelien Jarno | AES_Te2[st.B(aes_shifts[4*i+2])] ^ |
2251 | d640045a | Aurelien Jarno | AES_Te3[st.B(aes_shifts[4*i+3])]); |
2252 | d640045a | Aurelien Jarno | } |
2253 | d640045a | Aurelien Jarno | } |
2254 | d640045a | Aurelien Jarno | |
2255 | d640045a | Aurelien Jarno | void glue(helper_aesenclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
2256 | d640045a | Aurelien Jarno | { |
2257 | d640045a | Aurelien Jarno | int i;
|
2258 | d640045a | Aurelien Jarno | Reg st = *d; |
2259 | d640045a | Aurelien Jarno | Reg rk = *s; |
2260 | d640045a | Aurelien Jarno | |
2261 | d640045a | Aurelien Jarno | for (i = 0; i < 16; i++) { |
2262 | d640045a | Aurelien Jarno | d->B(i) = rk.B(i) ^ (AES_Te4[st.B(aes_shifts[i])] & 0xff);
|
2263 | d640045a | Aurelien Jarno | } |
2264 | d640045a | Aurelien Jarno | |
2265 | d640045a | Aurelien Jarno | } |
2266 | d640045a | Aurelien Jarno | |
2267 | d640045a | Aurelien Jarno | void glue(helper_aesimc, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
|
2268 | d640045a | Aurelien Jarno | { |
2269 | d640045a | Aurelien Jarno | int i;
|
2270 | d640045a | Aurelien Jarno | Reg tmp = *s; |
2271 | d640045a | Aurelien Jarno | |
2272 | d640045a | Aurelien Jarno | for (i = 0 ; i < 4 ; i++) { |
2273 | d640045a | Aurelien Jarno | d->L(i) = bswap32(AES_Td0[AES_Te4[tmp.B(4*i+0)] & 0xff] ^ |
2274 | d640045a | Aurelien Jarno | AES_Td1[AES_Te4[tmp.B(4*i+1)] & 0xff] ^ |
2275 | d640045a | Aurelien Jarno | AES_Td2[AES_Te4[tmp.B(4*i+2)] & 0xff] ^ |
2276 | d640045a | Aurelien Jarno | AES_Td3[AES_Te4[tmp.B(4*i+3)] & 0xff]); |
2277 | d640045a | Aurelien Jarno | } |
2278 | d640045a | Aurelien Jarno | } |
2279 | d640045a | Aurelien Jarno | |
2280 | d640045a | Aurelien Jarno | void glue(helper_aeskeygenassist, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
|
2281 | d640045a | Aurelien Jarno | uint32_t ctrl) |
2282 | d640045a | Aurelien Jarno | { |
2283 | d640045a | Aurelien Jarno | int i;
|
2284 | d640045a | Aurelien Jarno | Reg tmp = *s; |
2285 | d640045a | Aurelien Jarno | |
2286 | d640045a | Aurelien Jarno | for (i = 0 ; i < 4 ; i++) { |
2287 | d640045a | Aurelien Jarno | d->B(i) = AES_Te4[tmp.B(i + 4)] & 0xff; |
2288 | d640045a | Aurelien Jarno | d->B(i + 8) = AES_Te4[tmp.B(i + 12)] & 0xff; |
2289 | d640045a | Aurelien Jarno | } |
2290 | d640045a | Aurelien Jarno | d->L(1) = (d->L(0) << 24 | d->L(0) >> 8) ^ ctrl; |
2291 | d640045a | Aurelien Jarno | d->L(3) = (d->L(2) << 24 | d->L(2) >> 8) ^ ctrl; |
2292 | d640045a | Aurelien Jarno | } |
2293 | 222a3336 | balrog | #endif
|
2294 | 222a3336 | balrog | |
2295 | 664e0f19 | bellard | #undef SHIFT
|
2296 | 664e0f19 | bellard | #undef XMM_ONLY
|
2297 | 664e0f19 | bellard | #undef Reg
|
2298 | 664e0f19 | bellard | #undef B
|
2299 | 664e0f19 | bellard | #undef W
|
2300 | 664e0f19 | bellard | #undef L
|
2301 | 664e0f19 | bellard | #undef Q
|
2302 | 664e0f19 | bellard | #undef SUFFIX |