target-i386: Fix "call im" on x86_64 when executing 32-bit code
Similarly to what is done in 32938e127f50a40844a0fb9c5abb8691aeeccf7efor "jmp im", trunc the immediate to 32-bit when not running in 64-bitmode.
Reported-by: Kevin O'Connor <kevin@koconnor.net>...
Intel CPUs starting from pentium have apic
Intel CPUs starting from pentium have apic. Lets advertise it.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "kvm: x86: Save/restore exception_index"
This reverts commit ebbc8a3d8e76d0402f8a08c10c0f32e24715d41d.
As suggested by Jan Kiszka,
"It was obsoleted by d1793b836f8f123b961c613de1bb1c0c185c84cc and now saves/restores a useless field."
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: x86: Use separate exception_injected CPUState field
Marcelo correctly remarked that there are usage conflicts between QEMUcore code and KVM /wrt exception_index. So spend a separate field andalso save/restore it properly.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
target-i386: Fix evaluation of DR7 register
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplierto extract type and len.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-i386: Update CPUID feature set for TCG
The CPUID features QEMU presented to the guest were not up-to-datewith QEMU's emulated feature set.Add the missing bits of recent (and not so recent) additions toQEMU's emulation engine.For stability reasons only the user mode usable bits are exposed for...
v2: properly save kvm system time msr registers
Currently, the msrs involved in setting up pvclock are not saved overmigration and/or save/restore. This patch puts their value in specialfields in our CPUState, and deal with them using vmstate.
kvm also has to account for it, by including them in the msr list...
kvm: x86: Save/restore exception_index
As KVM now makes use of exception_index to keep pending exceptions, wehave to save&restore this field as well.
NOTE: We have to nail the arch-independent exception_index down to acertain bit width for proper vmstate processing, namely to 32 bit....
cpuid: Fix multicore setup on Intel
The multicore CPUID code detects whether the guest is an Intel or anAMD CPU, because the Linux kernel is picky about the CmpLegacy bit.KVM by default passes through the host's vendor, which was notcatched by the code. So fork out the vendor determining bits into a...
kvm: x86: Fix initial kvm_has_msr_star
KVM_GET_MSR_INDEX_LIST returns -E2BIG when the provided space is toosmall for all MSRs. But this is precisely the error we trigger with theinitial request in order to obtain that size. Do not fail in that case.
This caused a subtle corruption of the guest state as MSR_STAR was not...
kvm: x86: Add support for VCPU event states
This patch extends the qemu-kvm state sync logic with support forKVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception,interrupt and NMI states.
kvm: x86: Fix merge artifact of f8d926e9 about mp_state
kvm: Add arch reset handler
Will be required by succeeding changes.
kvm: x86: Refactor use of interrupt_bitmap
Drop interrupt_bitmap from the cpustate and solely rely on the integerinterupt_injected. This prepares us for the new injected-interruptinterface, which will deprecate the bitmap, while preservingcompatibility....
kvm: Move KVM mp_state accessors to i386-specific code
Unbreaks PowerPC and S390 KVM builds.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
v3: don't call reset functions on cpu initialization
There is absolutely no need to call reset functions when initializingdevices. Since we are already registering them, calling qemu_system_reset()should suffice. Actually, it is what happens when we reboot the machine,...
vmstate: Add version arg to VMSTATE_SINGLE_TEST()
This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TESTSigned-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning thenumber of leading zero bits in a word.As this is similar to the "bsr" instruction, reuse the existingcode. There need to be some more changes, though, as lzcnt always...
x86: add 'static' to please Sparse
target-i386: fix ARPL
The arpl implementation in target-i386/translate.c uses cpu_A0temporary across a brcond op. This patch fixes that issue.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limitedoffsets. Suggested by Laurent Desnogues.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
x86: fix miss merge
There was a missmerge, and then we got a tail recursive call to cpu_post_loadwithout case base :)
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in waythat debugging 32 or 16-bit guest code is no longer possible with qemufor x86_64 guest CPUs. Since that commit, qemu only provides registers...
x86: factor out cpu_get/put_fpreg()
x86: port cpu to vmstate
x86: mcg_cap is never 0
x86: split FPReg union
x86: split MTRRVar union
x86: port segments to vmstate
x86: factor out cpu_pre_save()
x86: factor out cpu_pre/post_load()
x86: factor out cpu_get/put_xmm_reg()
x86: factor out cpu_get/put_mttr_var()
x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden
x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change
CC: Huang Ying <ying.huang@intel.com>Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: send mce_banks as an array
x86: fpuc is uint16_t not unsigned int
x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field
x86: add fptag_vmstate to the state
It is needed to store fptags
x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap
x86: hflags is not modified at all, just save it directly
x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactlywhat we need (namely, sign extend to 64 bits when used with 64bit addresess.
Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax....
target-i386: Fix exceptions for fxsave/fxrstor
This patch corrects the following aspects of exception generation infxsave/fxrstor:
target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the contentof a 32-bit MSR, which can be freely set by the OS. This allows CPUlocal data to be queried by userspace.Linux uses this to allow a fast implementation of the getcpu()...
target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.Those include insertq and extrq, which are doing shift and mask onXMM registers, in two versions (immediate shift/length values andstored in another XMM register)....
target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.This behavior is guarded by the CR8_LEGACY CPUID bit(Fn8000_0001:ECX1).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
x86: use globals for CPU registers
Use globals for the 8 or 16 CPU registers on i386 and x86_64.
target-i386: kill a tmp register
target-i386: use subfi instead of sub with a non-freed constant
gcc wants 1st static and then const
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ioports: remove unused env parameter and compile only once
The CPU state parameter is not used, remove it and adjust callers. Now wecan compile ioport.c once for all targets.
i386: Drop redundant kvm_enabled test
cpu_synchronize_state already does this.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Work around OpenSolaris sys/regset.h namespace pollution
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
kvm_arch_get_registers() shouldn't be called directly
Direct call to kvm_arch_get_registers() bypass logic incpu_synchronize_state()
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Fix Sparse warnings: add "static"
kvm: Simplify cpu_synchronize_state()
cpu_synchronize_state() is a little unreadable since the 'modified'argument isn't self-explanatory. Simplify it by making it alwayssynchronize the kernel state into qemu, and automatically flush theregisters back to the kernel if they've been synchronized on this...
push CPUID level to 4 to allow Intel multicore decoding
Intel CPUs store the number of cores in CPUID leaf 4. So pushthe maxleaf value to 4 to allow the guests access to this leaf.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
set CPUID bits to present cores and threads topology
Controlled by the enhanced -smp option set the CPUID bits to present theguest the desired topology. This is vendor specific, but (with the exceptionof the CMP_LEGACY bit) not conflicting, so we set all bits everytime....
allow overriding of CPUID level on command line
The CPUID level determines how many CPUID leafs are exposed to the guest.Some features (like multi-core) cannot be propagated without the properlevel, but guests maybe confused by bogus entries in some leafs....
introduce kvm64 CPU
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type,which is the least common denominator of all KVM-capable x86-CPUs(based on Intel Pentium 4 Prescott). It can be used as a base typefor migration.
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Unbreak large mem support by removing kqemu
kqemu introduces a number of restrictions on the i386 target. The worst is thatit prevents large memory from working in the default build.
Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Only allow -cpu host when KVM is enabled
-cpu host is not at all useful when using tcg.
Initialize cpuid variables
This causes a build break when !KVM.
omit 3DNOW! CPUID bits from qemu64 CPU model
Since we recently do not disable 3DNOW! support anymore, we shouldavoid setting the bits in the default qemu64 CPU model to easemigration. TCG does not support it anyway and even AMD deprecatesit's usage nowadays....
Update to a hopefully more future proof FSF address
gdbstub: x86: Support for setting segment registers
This allows to set segment registers via gdb also in system emulationmode. Basic sanity checks are applied and nothing is changed if theyfail. But screwing up the target via this interface will never be...
kvm: Work around borken MSR_GET_INDEX_LIST
Allocate enough memory for KVM_GET_MSR_INDEX_LIST as older kernels shotfar beyond their limits, corrupting user space memory.
Make sure to mark MCE defines as ULL
Fixes build on 32-bit
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.- A monitor command "mce" is added to inject a MCE.- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user...
Use ctz64 in favor of ffsll
Not all host platforms support ffsll.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Suppress a GCC warning
KVM: x86: Refactor persistent CPU state
This patch aligns the KVM-related layout and encoding of the CPU stateto be saved to disk or migrated with qemu-kvm. The major differences arereordering of fields and a compressed interrupt_bitmap into a singlenumber as there can be no more than one pending IRQ at a time....
preserve the hypervisor bit while KVM trims the CPUID bits
The KVM kernel will disable all bits in CPUID which are not present inthe host. As this is mostly true for the hypervisor bit (1.ecx),preserve its value before the trim and restore it afterwards....
allow hypervisor CPUID bit to be overriden
KVM defaults to the hypervisor CPUID bit to be set, whereas pureQEMU clears it. On some occasions one wants to set or clear it theother way round (for instance to get HyperV running inside a guest).
Move the bit-set to be done before the command line parsing and...
introduce -cpu host target
Although the guest's CPUID bits can be controlled in a fine grained wayin QEMU, a simple way to inject the host CPU is missing. This is handyfor KVM desktop virtualization, where one wants the guest to support thefull host feature set....
CPUID Fn8000_0001.EAX is family/model/stepping, not features
fix KVMs GET_SUPPORTED_CPUID feature usage
If we want to trim the user provided CPUID bits for KVM to be not greaterthan that of the host, we should not remove the bits after we sentthem to the kernel.This fixes the masking of features that are not present on the host by...
remove CPUID host hacks
KVM provides an in-kernel feature to disable CPUID bits that are notpresent in the current host. So there is no need here to duplicate thiswork. Additionally allows 3DNow! on capable processors, since therestriction seems to apply to QEMU/TCG only....
Handle init/sipi in a main cpu exec loop. (v2)
This should fix compilation problem in case of CONFIG_USER_ONLY.
Currently INIT/SIPI is handled in the context of CPU that sends IPI.This patch changes this to handle them like all other events in a maincpu exec loop. When KVM will gain thread per vcpu capability it will...
allow CPUID vendor override
KVM-enabled QEMU will always report the vendor ID of the physical CPU it isrunning on. Allow to override this if explicitly requested on thecommand line. It will not suffice to name a CPU type (like -cpu phenom),but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD...
QEMU KVM: i386: Fix the cpu reset state
As per the IA32 processor manual, the accessed bit is set to 1 in theprocessor state after reset. qemu pc cpu_reset code was missing thisaccessed bit setting.
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>...
x86: Add support for resume flag
kvm: x86: Save/restore KVM-specific CPU states
Save and restore all so far neglected KVM-specific CPU states. Handlingthe TSC stabilizes migration in KVM mode. The interrupt_bitmap andmp_state are currently unused, but will become relevant for in-kernel...
kvm: Add missing bits to support live migration
This patch adds the missing hooks to allow live migration in KVM mode.It adds proper synchronization before/after saving/restoring the VCPUstates (note: PPC is untested), hooks intocpu_physical_memory_set_dirty_tracking() to enable dirty memory logging...
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
kvm: work around supported cpuid ioctl() brokenness
KVM_GET_SUPPORTED_CPUID has been known to fail to return -E2BIGwhen it runs out of entries. Detect this by always trying againwith a bigger table if the ioctl() fills the table.
Signed-off-by: Mark McLoughlin <markmc@redhat.com>
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Signed-off-by: Paul Brook <paul@codesourcery.com>
Replace gcc variadic macro extension with C99 version
Remove noisy printf when KVM masks CPU features
kvm: Add support for querying supported cpu features
kvm does not support all cpu features; add support for dunamically queryingthe supported feature set.
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Make x86 cpuid feature names available in file scope
To be used later.
Fix x86 feature modifications for features that set multiple bits
QEMU allows adding or removing cpu features by using the syntax '-cpu +feature'or '-cpu -feature'. Some cpuid features cause more than one bit to be set orcleared; but QEMU stops after just one bit has been modified, causing the...
kvm: Trim cpu features not supported by kvm
Remove cpu features that are not supported by kvm from the cpuid featuresreported to the guest.
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162