root / hw / char / parallel.c @ f53f81e0
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1 | 6508fe59 | bellard | /*
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2 | 6508fe59 | bellard | * QEMU Parallel PORT emulation
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3 | 5fafdf24 | ths | *
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4 | e57a8c0e | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5867c88a | ths | * Copyright (c) 2007 Marko Kohtala
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6 | 5fafdf24 | ths | *
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7 | 6508fe59 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 6508fe59 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 6508fe59 | bellard | * in the Software without restriction, including without limitation the rights
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10 | 6508fe59 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 6508fe59 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 6508fe59 | bellard | * furnished to do so, subject to the following conditions:
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13 | 6508fe59 | bellard | *
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14 | 6508fe59 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 6508fe59 | bellard | * all copies or substantial portions of the Software.
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16 | 6508fe59 | bellard | *
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17 | 6508fe59 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 6508fe59 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 6508fe59 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 6508fe59 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 6508fe59 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 6508fe59 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 6508fe59 | bellard | * THE SOFTWARE.
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24 | 6508fe59 | bellard | */
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25 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
26 | dccfcd0e | Paolo Bonzini | #include "sysemu/char.h" |
27 | 0d09e41a | Paolo Bonzini | #include "hw/isa/isa.h" |
28 | 0d09e41a | Paolo Bonzini | #include "hw/i386/pc.h" |
29 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
30 | 6508fe59 | bellard | |
31 | 6508fe59 | bellard | //#define DEBUG_PARALLEL
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32 | 6508fe59 | bellard | |
33 | 5867c88a | ths | #ifdef DEBUG_PARALLEL
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34 | 001faf32 | Blue Swirl | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
35 | 5867c88a | ths | #else
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36 | 001faf32 | Blue Swirl | #define pdebug(fmt, ...) ((void)0) |
37 | 5867c88a | ths | #endif
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38 | 5867c88a | ths | |
39 | 5867c88a | ths | #define PARA_REG_DATA 0 |
40 | 5867c88a | ths | #define PARA_REG_STS 1 |
41 | 5867c88a | ths | #define PARA_REG_CTR 2 |
42 | 5867c88a | ths | #define PARA_REG_EPP_ADDR 3 |
43 | 5867c88a | ths | #define PARA_REG_EPP_DATA 4 |
44 | 5867c88a | ths | |
45 | 6508fe59 | bellard | /*
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46 | 6508fe59 | bellard | * These are the definitions for the Printer Status Register
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47 | 6508fe59 | bellard | */
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48 | 6508fe59 | bellard | #define PARA_STS_BUSY 0x80 /* Busy complement */ |
49 | 6508fe59 | bellard | #define PARA_STS_ACK 0x40 /* Acknowledge */ |
50 | 6508fe59 | bellard | #define PARA_STS_PAPER 0x20 /* Out of paper */ |
51 | 6508fe59 | bellard | #define PARA_STS_ONLINE 0x10 /* Online */ |
52 | 6508fe59 | bellard | #define PARA_STS_ERROR 0x08 /* Error complement */ |
53 | 5867c88a | ths | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
54 | 6508fe59 | bellard | |
55 | 6508fe59 | bellard | /*
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56 | 6508fe59 | bellard | * These are the definitions for the Printer Control Register
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57 | 6508fe59 | bellard | */
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58 | 5867c88a | ths | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
59 | 6508fe59 | bellard | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
60 | 6508fe59 | bellard | #define PARA_CTR_SELECT 0x08 /* Select In complement */ |
61 | 6508fe59 | bellard | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
62 | 6508fe59 | bellard | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
63 | 6508fe59 | bellard | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
64 | 6508fe59 | bellard | |
65 | 5867c88a | ths | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
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66 | 5867c88a | ths | |
67 | defdb20e | Blue Swirl | typedef struct ParallelState { |
68 | 63858cd9 | Avi Kivity | MemoryRegion iomem; |
69 | 5867c88a | ths | uint8_t dataw; |
70 | 5867c88a | ths | uint8_t datar; |
71 | 5867c88a | ths | uint8_t status; |
72 | 6508fe59 | bellard | uint8_t control; |
73 | d537cf6c | pbrook | qemu_irq irq; |
74 | 6508fe59 | bellard | int irq_pending;
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75 | 6508fe59 | bellard | CharDriverState *chr; |
76 | e57a8c0e | bellard | int hw_driver;
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77 | 5867c88a | ths | int epp_timeout;
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78 | 5867c88a | ths | uint32_t last_read_offset; /* For debugging */
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79 | d60532ca | ths | /* Memory-mapped interface */
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80 | d60532ca | ths | int it_shift;
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81 | defdb20e | Blue Swirl | } ParallelState; |
82 | 6508fe59 | bellard | |
83 | b0dc5ee6 | Andreas Färber | #define TYPE_ISA_PARALLEL "isa-parallel" |
84 | b0dc5ee6 | Andreas Färber | #define ISA_PARALLEL(obj) \
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85 | b0dc5ee6 | Andreas Färber | OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) |
86 | b0dc5ee6 | Andreas Färber | |
87 | 021f0674 | Gerd Hoffmann | typedef struct ISAParallelState { |
88 | b0dc5ee6 | Andreas Färber | ISADevice parent_obj; |
89 | b0dc5ee6 | Andreas Färber | |
90 | e8ee28fb | Gerd Hoffmann | uint32_t index; |
91 | 021f0674 | Gerd Hoffmann | uint32_t iobase; |
92 | 021f0674 | Gerd Hoffmann | uint32_t isairq; |
93 | 021f0674 | Gerd Hoffmann | ParallelState state; |
94 | 021f0674 | Gerd Hoffmann | } ISAParallelState; |
95 | 021f0674 | Gerd Hoffmann | |
96 | 6508fe59 | bellard | static void parallel_update_irq(ParallelState *s) |
97 | 6508fe59 | bellard | { |
98 | 6508fe59 | bellard | if (s->irq_pending)
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99 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
100 | 6508fe59 | bellard | else
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101 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
102 | 6508fe59 | bellard | } |
103 | 6508fe59 | bellard | |
104 | 5867c88a | ths | static void |
105 | 5867c88a | ths | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
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106 | 6508fe59 | bellard | { |
107 | 6508fe59 | bellard | ParallelState *s = opaque; |
108 | 3b46e624 | ths | |
109 | 5867c88a | ths | pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
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110 | 5867c88a | ths | |
111 | 5867c88a | ths | addr &= 7;
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112 | 5867c88a | ths | switch(addr) {
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113 | 5867c88a | ths | case PARA_REG_DATA:
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114 | 0fa7f157 | ths | s->dataw = val; |
115 | 0fa7f157 | ths | parallel_update_irq(s); |
116 | 5867c88a | ths | break;
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117 | 5867c88a | ths | case PARA_REG_CTR:
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118 | 52ccc5e0 | balrog | val |= 0xc0;
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119 | 0fa7f157 | ths | if ((val & PARA_CTR_INIT) == 0 ) { |
120 | 0fa7f157 | ths | s->status = PARA_STS_BUSY; |
121 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
122 | 0fa7f157 | ths | s->status |= PARA_STS_ONLINE; |
123 | 0fa7f157 | ths | s->status |= PARA_STS_ERROR; |
124 | 0fa7f157 | ths | } |
125 | 0fa7f157 | ths | else if (val & PARA_CTR_SELECT) { |
126 | 0fa7f157 | ths | if (val & PARA_CTR_STROBE) {
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127 | 0fa7f157 | ths | s->status &= ~PARA_STS_BUSY; |
128 | 0fa7f157 | ths | if ((s->control & PARA_CTR_STROBE) == 0) |
129 | 2cc6e0a1 | Anthony Liguori | qemu_chr_fe_write(s->chr, &s->dataw, 1);
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130 | 0fa7f157 | ths | } else {
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131 | 0fa7f157 | ths | if (s->control & PARA_CTR_INTEN) {
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132 | 0fa7f157 | ths | s->irq_pending = 1;
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133 | 0fa7f157 | ths | } |
134 | 0fa7f157 | ths | } |
135 | 0fa7f157 | ths | } |
136 | 0fa7f157 | ths | parallel_update_irq(s); |
137 | 0fa7f157 | ths | s->control = val; |
138 | 5867c88a | ths | break;
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139 | 5867c88a | ths | } |
140 | 5867c88a | ths | } |
141 | 5867c88a | ths | |
142 | 5867c88a | ths | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
143 | 5867c88a | ths | { |
144 | 5867c88a | ths | ParallelState *s = opaque; |
145 | 5867c88a | ths | uint8_t parm = val; |
146 | 563e3c6e | aurel32 | int dir;
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147 | 5867c88a | ths | |
148 | 5867c88a | ths | /* Sometimes programs do several writes for timing purposes on old
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149 | 5867c88a | ths | HW. Take care not to waste time on writes that do nothing. */
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150 | 5867c88a | ths | |
151 | 5867c88a | ths | s->last_read_offset = ~0U;
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152 | 5867c88a | ths | |
153 | 6508fe59 | bellard | addr &= 7;
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154 | 6508fe59 | bellard | switch(addr) {
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155 | 5867c88a | ths | case PARA_REG_DATA:
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156 | 5867c88a | ths | if (s->dataw == val)
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157 | 0fa7f157 | ths | return;
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158 | 0fa7f157 | ths | pdebug("wd%02x\n", val);
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159 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
160 | 0fa7f157 | ths | s->dataw = val; |
161 | 6508fe59 | bellard | break;
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162 | 5867c88a | ths | case PARA_REG_STS:
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163 | 0fa7f157 | ths | pdebug("ws%02x\n", val);
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164 | 0fa7f157 | ths | if (val & PARA_STS_TMOUT)
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165 | 0fa7f157 | ths | s->epp_timeout = 0;
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166 | 0fa7f157 | ths | break;
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167 | 5867c88a | ths | case PARA_REG_CTR:
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168 | 5867c88a | ths | val |= 0xc0;
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169 | 5867c88a | ths | if (s->control == val)
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170 | 0fa7f157 | ths | return;
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171 | 0fa7f157 | ths | pdebug("wc%02x\n", val);
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172 | 563e3c6e | aurel32 | |
173 | 563e3c6e | aurel32 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
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174 | 563e3c6e | aurel32 | if (val & PARA_CTR_DIR) {
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175 | 563e3c6e | aurel32 | dir = 1;
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176 | 563e3c6e | aurel32 | } else {
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177 | 563e3c6e | aurel32 | dir = 0;
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178 | 563e3c6e | aurel32 | } |
179 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
180 | 563e3c6e | aurel32 | parm &= ~PARA_CTR_DIR; |
181 | 563e3c6e | aurel32 | } |
182 | 563e3c6e | aurel32 | |
183 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
184 | 0fa7f157 | ths | s->control = val; |
185 | 6508fe59 | bellard | break;
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186 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
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187 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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188 | 0fa7f157 | ths | /* Controls not correct for EPP address cycle, so do nothing */
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189 | 0fa7f157 | ths | pdebug("wa%02x s\n", val);
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190 | 0fa7f157 | ths | else {
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191 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
192 | 41084f1b | Anthony Liguori | if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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193 | 0fa7f157 | ths | s->epp_timeout = 1;
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194 | 0fa7f157 | ths | pdebug("wa%02x t\n", val);
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195 | 0fa7f157 | ths | } |
196 | 0fa7f157 | ths | else
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197 | 0fa7f157 | ths | pdebug("wa%02x\n", val);
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198 | 0fa7f157 | ths | } |
199 | 0fa7f157 | ths | break;
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200 | 5867c88a | ths | case PARA_REG_EPP_DATA:
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201 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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202 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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203 | 0fa7f157 | ths | pdebug("we%02x s\n", val);
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204 | 0fa7f157 | ths | else {
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205 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
206 | 41084f1b | Anthony Liguori | if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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207 | 0fa7f157 | ths | s->epp_timeout = 1;
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208 | 0fa7f157 | ths | pdebug("we%02x t\n", val);
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209 | 0fa7f157 | ths | } |
210 | 0fa7f157 | ths | else
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211 | 0fa7f157 | ths | pdebug("we%02x\n", val);
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212 | 0fa7f157 | ths | } |
213 | 0fa7f157 | ths | break;
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214 | 5867c88a | ths | } |
215 | 5867c88a | ths | } |
216 | 5867c88a | ths | |
217 | 5867c88a | ths | static void |
218 | 5867c88a | ths | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
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219 | 5867c88a | ths | { |
220 | 5867c88a | ths | ParallelState *s = opaque; |
221 | 5867c88a | ths | uint16_t eppdata = cpu_to_le16(val); |
222 | 5867c88a | ths | int err;
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223 | 5867c88a | ths | struct ParallelIOArg ioarg = {
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224 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
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225 | 5867c88a | ths | }; |
226 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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227 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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228 | 0fa7f157 | ths | pdebug("we%04x s\n", val);
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229 | 0fa7f157 | ths | return;
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230 | 5867c88a | ths | } |
231 | 41084f1b | Anthony Liguori | err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
232 | 5867c88a | ths | if (err) {
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233 | 0fa7f157 | ths | s->epp_timeout = 1;
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234 | 0fa7f157 | ths | pdebug("we%04x t\n", val);
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235 | 5867c88a | ths | } |
236 | 5867c88a | ths | else
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237 | 0fa7f157 | ths | pdebug("we%04x\n", val);
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238 | 5867c88a | ths | } |
239 | 5867c88a | ths | |
240 | 5867c88a | ths | static void |
241 | 5867c88a | ths | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
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242 | 5867c88a | ths | { |
243 | 5867c88a | ths | ParallelState *s = opaque; |
244 | 5867c88a | ths | uint32_t eppdata = cpu_to_le32(val); |
245 | 5867c88a | ths | int err;
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246 | 5867c88a | ths | struct ParallelIOArg ioarg = {
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247 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
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248 | 5867c88a | ths | }; |
249 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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250 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
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251 | 0fa7f157 | ths | pdebug("we%08x s\n", val);
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252 | 0fa7f157 | ths | return;
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253 | 5867c88a | ths | } |
254 | 41084f1b | Anthony Liguori | err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
255 | 5867c88a | ths | if (err) {
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256 | 0fa7f157 | ths | s->epp_timeout = 1;
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257 | 0fa7f157 | ths | pdebug("we%08x t\n", val);
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258 | 6508fe59 | bellard | } |
259 | 5867c88a | ths | else
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260 | 0fa7f157 | ths | pdebug("we%08x\n", val);
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261 | 6508fe59 | bellard | } |
262 | 6508fe59 | bellard | |
263 | 5867c88a | ths | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
264 | 6508fe59 | bellard | { |
265 | 6508fe59 | bellard | ParallelState *s = opaque; |
266 | 6508fe59 | bellard | uint32_t ret = 0xff;
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267 | 6508fe59 | bellard | |
268 | 6508fe59 | bellard | addr &= 7;
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269 | 6508fe59 | bellard | switch(addr) {
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270 | 5867c88a | ths | case PARA_REG_DATA:
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271 | 0fa7f157 | ths | if (s->control & PARA_CTR_DIR)
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272 | 0fa7f157 | ths | ret = s->datar; |
273 | 0fa7f157 | ths | else
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274 | 0fa7f157 | ths | ret = s->dataw; |
275 | 6508fe59 | bellard | break;
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276 | 5867c88a | ths | case PARA_REG_STS:
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277 | 0fa7f157 | ths | ret = s->status; |
278 | 0fa7f157 | ths | s->irq_pending = 0;
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279 | 0fa7f157 | ths | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
280 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
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281 | 0fa7f157 | ths | if (s->status & PARA_STS_ACK)
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282 | 0fa7f157 | ths | s->status &= ~PARA_STS_ACK; |
283 | 0fa7f157 | ths | else {
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284 | 0fa7f157 | ths | /* XXX Fixme: wait 5 microseconds */
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285 | 0fa7f157 | ths | s->status |= PARA_STS_ACK; |
286 | 0fa7f157 | ths | s->status |= PARA_STS_BUSY; |
287 | 0fa7f157 | ths | } |
288 | 0fa7f157 | ths | } |
289 | 0fa7f157 | ths | parallel_update_irq(s); |
290 | 6508fe59 | bellard | break;
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291 | 5867c88a | ths | case PARA_REG_CTR:
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292 | 6508fe59 | bellard | ret = s->control; |
293 | 6508fe59 | bellard | break;
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294 | 6508fe59 | bellard | } |
295 | 5867c88a | ths | pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
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296 | 5867c88a | ths | return ret;
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297 | 5867c88a | ths | } |
298 | 5867c88a | ths | |
299 | 5867c88a | ths | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
300 | 5867c88a | ths | { |
301 | 5867c88a | ths | ParallelState *s = opaque; |
302 | 5867c88a | ths | uint8_t ret = 0xff;
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303 | 5867c88a | ths | addr &= 7;
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304 | 5867c88a | ths | switch(addr) {
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305 | 5867c88a | ths | case PARA_REG_DATA:
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306 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
307 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->datar != ret)
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308 | 0fa7f157 | ths | pdebug("rd%02x\n", ret);
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309 | 5867c88a | ths | s->datar = ret; |
310 | 5867c88a | ths | break;
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311 | 5867c88a | ths | case PARA_REG_STS:
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312 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
313 | 0fa7f157 | ths | ret &= ~PARA_STS_TMOUT; |
314 | 0fa7f157 | ths | if (s->epp_timeout)
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315 | 0fa7f157 | ths | ret |= PARA_STS_TMOUT; |
316 | 0fa7f157 | ths | if (s->last_read_offset != addr || s->status != ret)
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317 | 0fa7f157 | ths | pdebug("rs%02x\n", ret);
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318 | 0fa7f157 | ths | s->status = ret; |
319 | 5867c88a | ths | break;
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320 | 5867c88a | ths | case PARA_REG_CTR:
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321 | 5867c88a | ths | /* s->control has some bits fixed to 1. It is zero only when
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322 | 0fa7f157 | ths | it has not been yet written to. */
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323 | 0fa7f157 | ths | if (s->control == 0) { |
324 | 41084f1b | Anthony Liguori | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
325 | 0fa7f157 | ths | if (s->last_read_offset != addr)
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326 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
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327 | 0fa7f157 | ths | s->control = ret; |
328 | 0fa7f157 | ths | } |
329 | 0fa7f157 | ths | else {
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330 | 0fa7f157 | ths | ret = s->control; |
331 | 0fa7f157 | ths | if (s->last_read_offset != addr)
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332 | 0fa7f157 | ths | pdebug("rc%02x\n", ret);
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333 | 0fa7f157 | ths | } |
334 | 5867c88a | ths | break;
|
335 | 5867c88a | ths | case PARA_REG_EPP_ADDR:
|
336 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
337 | 0fa7f157 | ths | /* Controls not correct for EPP addr cycle, so do nothing */
|
338 | 0fa7f157 | ths | pdebug("ra%02x s\n", ret);
|
339 | 0fa7f157 | ths | else {
|
340 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
341 | 41084f1b | Anthony Liguori | if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
|
342 | 0fa7f157 | ths | s->epp_timeout = 1;
|
343 | 0fa7f157 | ths | pdebug("ra%02x t\n", ret);
|
344 | 0fa7f157 | ths | } |
345 | 0fa7f157 | ths | else
|
346 | 0fa7f157 | ths | pdebug("ra%02x\n", ret);
|
347 | 0fa7f157 | ths | } |
348 | 0fa7f157 | ths | break;
|
349 | 5867c88a | ths | case PARA_REG_EPP_DATA:
|
350 | 0fa7f157 | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
351 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
352 | 0fa7f157 | ths | pdebug("re%02x s\n", ret);
|
353 | 0fa7f157 | ths | else {
|
354 | 0fa7f157 | ths | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
355 | 41084f1b | Anthony Liguori | if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
|
356 | 0fa7f157 | ths | s->epp_timeout = 1;
|
357 | 0fa7f157 | ths | pdebug("re%02x t\n", ret);
|
358 | 0fa7f157 | ths | } |
359 | 0fa7f157 | ths | else
|
360 | 0fa7f157 | ths | pdebug("re%02x\n", ret);
|
361 | 0fa7f157 | ths | } |
362 | 0fa7f157 | ths | break;
|
363 | 5867c88a | ths | } |
364 | 5867c88a | ths | s->last_read_offset = addr; |
365 | 5867c88a | ths | return ret;
|
366 | 5867c88a | ths | } |
367 | 5867c88a | ths | |
368 | 5867c88a | ths | static uint32_t
|
369 | 5867c88a | ths | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
370 | 5867c88a | ths | { |
371 | 5867c88a | ths | ParallelState *s = opaque; |
372 | 5867c88a | ths | uint32_t ret; |
373 | 5867c88a | ths | uint16_t eppdata = ~0;
|
374 | 5867c88a | ths | int err;
|
375 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
376 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
377 | 5867c88a | ths | }; |
378 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
379 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
380 | 0fa7f157 | ths | pdebug("re%04x s\n", eppdata);
|
381 | 0fa7f157 | ths | return eppdata;
|
382 | 5867c88a | ths | } |
383 | 41084f1b | Anthony Liguori | err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
384 | 5867c88a | ths | ret = le16_to_cpu(eppdata); |
385 | 5867c88a | ths | |
386 | 5867c88a | ths | if (err) {
|
387 | 0fa7f157 | ths | s->epp_timeout = 1;
|
388 | 0fa7f157 | ths | pdebug("re%04x t\n", ret);
|
389 | 5867c88a | ths | } |
390 | 5867c88a | ths | else
|
391 | 0fa7f157 | ths | pdebug("re%04x\n", ret);
|
392 | 5867c88a | ths | return ret;
|
393 | 5867c88a | ths | } |
394 | 5867c88a | ths | |
395 | 5867c88a | ths | static uint32_t
|
396 | 5867c88a | ths | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
397 | 5867c88a | ths | { |
398 | 5867c88a | ths | ParallelState *s = opaque; |
399 | 5867c88a | ths | uint32_t ret; |
400 | 5867c88a | ths | uint32_t eppdata = ~0U;
|
401 | 5867c88a | ths | int err;
|
402 | 5867c88a | ths | struct ParallelIOArg ioarg = {
|
403 | 0fa7f157 | ths | .buffer = &eppdata, .count = sizeof(eppdata)
|
404 | 5867c88a | ths | }; |
405 | 5867c88a | ths | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
406 | 0fa7f157 | ths | /* Controls not correct for EPP data cycle, so do nothing */
|
407 | 0fa7f157 | ths | pdebug("re%08x s\n", eppdata);
|
408 | 0fa7f157 | ths | return eppdata;
|
409 | 5867c88a | ths | } |
410 | 41084f1b | Anthony Liguori | err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
411 | 5867c88a | ths | ret = le32_to_cpu(eppdata); |
412 | 5867c88a | ths | |
413 | 5867c88a | ths | if (err) {
|
414 | 0fa7f157 | ths | s->epp_timeout = 1;
|
415 | 0fa7f157 | ths | pdebug("re%08x t\n", ret);
|
416 | 5867c88a | ths | } |
417 | 5867c88a | ths | else
|
418 | 0fa7f157 | ths | pdebug("re%08x\n", ret);
|
419 | 5867c88a | ths | return ret;
|
420 | 5867c88a | ths | } |
421 | 5867c88a | ths | |
422 | 5867c88a | ths | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
423 | 5867c88a | ths | { |
424 | 7f5b7d3e | Blue Swirl | pdebug("wecp%d=%02x\n", addr & 7, val); |
425 | 5867c88a | ths | } |
426 | 5867c88a | ths | |
427 | 5867c88a | ths | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
428 | 5867c88a | ths | { |
429 | 5867c88a | ths | uint8_t ret = 0xff;
|
430 | 7f5b7d3e | Blue Swirl | |
431 | 7f5b7d3e | Blue Swirl | pdebug("recp%d:%02x\n", addr & 7, ret); |
432 | 6508fe59 | bellard | return ret;
|
433 | 6508fe59 | bellard | } |
434 | 6508fe59 | bellard | |
435 | 33093a0a | aurel32 | static void parallel_reset(void *opaque) |
436 | 6508fe59 | bellard | { |
437 | 33093a0a | aurel32 | ParallelState *s = opaque; |
438 | 33093a0a | aurel32 | |
439 | 5867c88a | ths | s->datar = ~0;
|
440 | 5867c88a | ths | s->dataw = ~0;
|
441 | 6508fe59 | bellard | s->status = PARA_STS_BUSY; |
442 | 6508fe59 | bellard | s->status |= PARA_STS_ACK; |
443 | 6508fe59 | bellard | s->status |= PARA_STS_ONLINE; |
444 | 6508fe59 | bellard | s->status |= PARA_STS_ERROR; |
445 | 52ccc5e0 | balrog | s->status |= PARA_STS_TMOUT; |
446 | 6508fe59 | bellard | s->control = PARA_CTR_SELECT; |
447 | 6508fe59 | bellard | s->control |= PARA_CTR_INIT; |
448 | 52ccc5e0 | balrog | s->control |= 0xc0;
|
449 | 5867c88a | ths | s->irq_pending = 0;
|
450 | 5867c88a | ths | s->hw_driver = 0;
|
451 | 5867c88a | ths | s->epp_timeout = 0;
|
452 | 5867c88a | ths | s->last_read_offset = ~0U;
|
453 | d60532ca | ths | } |
454 | d60532ca | ths | |
455 | e8ee28fb | Gerd Hoffmann | static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
456 | e8ee28fb | Gerd Hoffmann | |
457 | 1922abd0 | Richard Henderson | static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
458 | 1922abd0 | Richard Henderson | { 0, 8, 1, |
459 | 1922abd0 | Richard Henderson | .read = parallel_ioport_read_hw, |
460 | 1922abd0 | Richard Henderson | .write = parallel_ioport_write_hw }, |
461 | 1922abd0 | Richard Henderson | { 4, 1, 2, |
462 | 1922abd0 | Richard Henderson | .read = parallel_ioport_eppdata_read_hw2, |
463 | 1922abd0 | Richard Henderson | .write = parallel_ioport_eppdata_write_hw2 }, |
464 | 1922abd0 | Richard Henderson | { 4, 1, 4, |
465 | 1922abd0 | Richard Henderson | .read = parallel_ioport_eppdata_read_hw4, |
466 | 1922abd0 | Richard Henderson | .write = parallel_ioport_eppdata_write_hw4 }, |
467 | 1922abd0 | Richard Henderson | { 0x400, 8, 1, |
468 | 1922abd0 | Richard Henderson | .read = parallel_ioport_ecp_read, |
469 | 1922abd0 | Richard Henderson | .write = parallel_ioport_ecp_write }, |
470 | 1922abd0 | Richard Henderson | PORTIO_END_OF_LIST(), |
471 | 1922abd0 | Richard Henderson | }; |
472 | 1922abd0 | Richard Henderson | |
473 | 1922abd0 | Richard Henderson | static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { |
474 | 1922abd0 | Richard Henderson | { 0, 8, 1, |
475 | 1922abd0 | Richard Henderson | .read = parallel_ioport_read_sw, |
476 | 1922abd0 | Richard Henderson | .write = parallel_ioport_write_sw }, |
477 | 1922abd0 | Richard Henderson | PORTIO_END_OF_LIST(), |
478 | 1922abd0 | Richard Henderson | }; |
479 | 1922abd0 | Richard Henderson | |
480 | db895a1e | Andreas Färber | static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
481 | d60532ca | ths | { |
482 | e8ee28fb | Gerd Hoffmann | static int index; |
483 | db895a1e | Andreas Färber | ISADevice *isadev = ISA_DEVICE(dev); |
484 | b0dc5ee6 | Andreas Färber | ISAParallelState *isa = ISA_PARALLEL(dev); |
485 | 021f0674 | Gerd Hoffmann | ParallelState *s = &isa->state; |
486 | e8ee28fb | Gerd Hoffmann | int base;
|
487 | d60532ca | ths | uint8_t dummy; |
488 | d60532ca | ths | |
489 | 021f0674 | Gerd Hoffmann | if (!s->chr) {
|
490 | db895a1e | Andreas Färber | error_setg(errp, "Can't create parallel device, empty char device");
|
491 | db895a1e | Andreas Färber | return;
|
492 | 021f0674 | Gerd Hoffmann | } |
493 | 021f0674 | Gerd Hoffmann | |
494 | db895a1e | Andreas Färber | if (isa->index == -1) { |
495 | e8ee28fb | Gerd Hoffmann | isa->index = index; |
496 | db895a1e | Andreas Färber | } |
497 | db895a1e | Andreas Färber | if (isa->index >= MAX_PARALLEL_PORTS) {
|
498 | db895a1e | Andreas Färber | error_setg(errp, "Max. supported number of parallel ports is %d.",
|
499 | db895a1e | Andreas Färber | MAX_PARALLEL_PORTS); |
500 | db895a1e | Andreas Färber | return;
|
501 | db895a1e | Andreas Färber | } |
502 | db895a1e | Andreas Färber | if (isa->iobase == -1) { |
503 | e8ee28fb | Gerd Hoffmann | isa->iobase = isa_parallel_io[isa->index]; |
504 | db895a1e | Andreas Färber | } |
505 | e8ee28fb | Gerd Hoffmann | index++; |
506 | e8ee28fb | Gerd Hoffmann | |
507 | e8ee28fb | Gerd Hoffmann | base = isa->iobase; |
508 | db895a1e | Andreas Färber | isa_init_irq(isadev, &s->irq, isa->isairq); |
509 | a08d4367 | Jan Kiszka | qemu_register_reset(parallel_reset, s); |
510 | 6508fe59 | bellard | |
511 | 41084f1b | Anthony Liguori | if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
512 | 5867c88a | ths | s->hw_driver = 1;
|
513 | 0fa7f157 | ths | s->status = dummy; |
514 | 5867c88a | ths | } |
515 | 5867c88a | ths | |
516 | db895a1e | Andreas Färber | isa_register_portio_list(isadev, base, |
517 | 1922abd0 | Richard Henderson | (s->hw_driver |
518 | 1922abd0 | Richard Henderson | ? &isa_parallel_portio_hw_list[0]
|
519 | 1922abd0 | Richard Henderson | : &isa_parallel_portio_sw_list[0]),
|
520 | 1922abd0 | Richard Henderson | s, "parallel");
|
521 | 021f0674 | Gerd Hoffmann | } |
522 | 021f0674 | Gerd Hoffmann | |
523 | d60532ca | ths | /* Memory mapped interface */
|
524 | a8170e5e | Avi Kivity | static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) |
525 | d60532ca | ths | { |
526 | d60532ca | ths | ParallelState *s = opaque; |
527 | d60532ca | ths | |
528 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; |
529 | d60532ca | ths | } |
530 | d60532ca | ths | |
531 | 9596ebb7 | pbrook | static void parallel_mm_writeb (void *opaque, |
532 | a8170e5e | Avi Kivity | hwaddr addr, uint32_t value) |
533 | d60532ca | ths | { |
534 | d60532ca | ths | ParallelState *s = opaque; |
535 | d60532ca | ths | |
536 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
|
537 | d60532ca | ths | } |
538 | d60532ca | ths | |
539 | a8170e5e | Avi Kivity | static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) |
540 | d60532ca | ths | { |
541 | d60532ca | ths | ParallelState *s = opaque; |
542 | d60532ca | ths | |
543 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; |
544 | d60532ca | ths | } |
545 | d60532ca | ths | |
546 | 9596ebb7 | pbrook | static void parallel_mm_writew (void *opaque, |
547 | a8170e5e | Avi Kivity | hwaddr addr, uint32_t value) |
548 | d60532ca | ths | { |
549 | d60532ca | ths | ParallelState *s = opaque; |
550 | d60532ca | ths | |
551 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
|
552 | d60532ca | ths | } |
553 | d60532ca | ths | |
554 | a8170e5e | Avi Kivity | static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) |
555 | d60532ca | ths | { |
556 | d60532ca | ths | ParallelState *s = opaque; |
557 | d60532ca | ths | |
558 | 8da3ff18 | pbrook | return parallel_ioport_read_sw(s, addr >> s->it_shift);
|
559 | d60532ca | ths | } |
560 | d60532ca | ths | |
561 | 9596ebb7 | pbrook | static void parallel_mm_writel (void *opaque, |
562 | a8170e5e | Avi Kivity | hwaddr addr, uint32_t value) |
563 | d60532ca | ths | { |
564 | d60532ca | ths | ParallelState *s = opaque; |
565 | d60532ca | ths | |
566 | 8da3ff18 | pbrook | parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
567 | d60532ca | ths | } |
568 | d60532ca | ths | |
569 | 63858cd9 | Avi Kivity | static const MemoryRegionOps parallel_mm_ops = { |
570 | 63858cd9 | Avi Kivity | .old_mmio = { |
571 | 63858cd9 | Avi Kivity | .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, |
572 | 63858cd9 | Avi Kivity | .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, |
573 | 63858cd9 | Avi Kivity | }, |
574 | 63858cd9 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
575 | d60532ca | ths | }; |
576 | d60532ca | ths | |
577 | d60532ca | ths | /* If fd is zero, it means that the parallel device uses the console */
|
578 | 63858cd9 | Avi Kivity | bool parallel_mm_init(MemoryRegion *address_space,
|
579 | a8170e5e | Avi Kivity | hwaddr base, int it_shift, qemu_irq irq,
|
580 | defdb20e | Blue Swirl | CharDriverState *chr) |
581 | d60532ca | ths | { |
582 | d60532ca | ths | ParallelState *s; |
583 | d60532ca | ths | |
584 | 7267c094 | Anthony Liguori | s = g_malloc0(sizeof(ParallelState));
|
585 | 33093a0a | aurel32 | s->irq = irq; |
586 | 33093a0a | aurel32 | s->chr = chr; |
587 | d60532ca | ths | s->it_shift = it_shift; |
588 | a08d4367 | Jan Kiszka | qemu_register_reset(parallel_reset, s); |
589 | d60532ca | ths | |
590 | 2c9b15ca | Paolo Bonzini | memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s,
|
591 | 63858cd9 | Avi Kivity | "parallel", 8 << it_shift); |
592 | 63858cd9 | Avi Kivity | memory_region_add_subregion(address_space, base, &s->iomem); |
593 | defdb20e | Blue Swirl | return true; |
594 | d60532ca | ths | } |
595 | 021f0674 | Gerd Hoffmann | |
596 | 39bffca2 | Anthony Liguori | static Property parallel_isa_properties[] = {
|
597 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), |
598 | c7bcc85d | Paolo Bonzini | DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
599 | 39bffca2 | Anthony Liguori | DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
600 | 39bffca2 | Anthony Liguori | DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
|
601 | 39bffca2 | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
602 | 39bffca2 | Anthony Liguori | }; |
603 | 39bffca2 | Anthony Liguori | |
604 | 8f04ee08 | Anthony Liguori | static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
605 | 8f04ee08 | Anthony Liguori | { |
606 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
607 | db895a1e | Andreas Färber | |
608 | db895a1e | Andreas Färber | dc->realize = parallel_isa_realizefn; |
609 | 39bffca2 | Anthony Liguori | dc->props = parallel_isa_properties; |
610 | 125ee0ed | Marcel Apfelbaum | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
611 | 8f04ee08 | Anthony Liguori | } |
612 | 8f04ee08 | Anthony Liguori | |
613 | 8c43a6f0 | Andreas Färber | static const TypeInfo parallel_isa_info = { |
614 | b0dc5ee6 | Andreas Färber | .name = TYPE_ISA_PARALLEL, |
615 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
616 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(ISAParallelState),
|
617 | 39bffca2 | Anthony Liguori | .class_init = parallel_isa_class_initfn, |
618 | 021f0674 | Gerd Hoffmann | }; |
619 | 021f0674 | Gerd Hoffmann | |
620 | 83f7d43a | Andreas Färber | static void parallel_register_types(void) |
621 | 021f0674 | Gerd Hoffmann | { |
622 | 39bffca2 | Anthony Liguori | type_register_static(¶llel_isa_info); |
623 | 021f0674 | Gerd Hoffmann | } |
624 | 021f0674 | Gerd Hoffmann | |
625 | 83f7d43a | Andreas Färber | type_init(parallel_register_types) |