root / hw / char / parallel.c @ f53f81e0
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/*
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* QEMU Parallel PORT emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2007 Marko Kohtala
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "sysemu/char.h" |
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#include "hw/isa/isa.h" |
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#include "hw/i386/pc.h" |
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#include "sysemu/sysemu.h" |
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//#define DEBUG_PARALLEL
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#ifdef DEBUG_PARALLEL
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#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
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#else
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#define pdebug(fmt, ...) ((void)0) |
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#endif
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#define PARA_REG_DATA 0 |
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#define PARA_REG_STS 1 |
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#define PARA_REG_CTR 2 |
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#define PARA_REG_EPP_ADDR 3 |
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#define PARA_REG_EPP_DATA 4 |
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/*
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* These are the definitions for the Printer Status Register
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*/
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#define PARA_STS_BUSY 0x80 /* Busy complement */ |
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#define PARA_STS_ACK 0x40 /* Acknowledge */ |
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#define PARA_STS_PAPER 0x20 /* Out of paper */ |
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#define PARA_STS_ONLINE 0x10 /* Online */ |
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#define PARA_STS_ERROR 0x08 /* Error complement */ |
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#define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
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/*
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* These are the definitions for the Printer Control Register
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*/
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#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
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#define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
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#define PARA_CTR_SELECT 0x08 /* Select In complement */ |
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#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ |
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#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ |
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#define PARA_CTR_STROBE 0x01 /* Strobe complement */ |
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#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
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typedef struct ParallelState { |
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MemoryRegion iomem; |
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uint8_t dataw; |
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uint8_t datar; |
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uint8_t status; |
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uint8_t control; |
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qemu_irq irq; |
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int irq_pending;
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CharDriverState *chr; |
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int hw_driver;
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int epp_timeout;
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uint32_t last_read_offset; /* For debugging */
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/* Memory-mapped interface */
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int it_shift;
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} ParallelState; |
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#define TYPE_ISA_PARALLEL "isa-parallel" |
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#define ISA_PARALLEL(obj) \
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OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) |
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typedef struct ISAParallelState { |
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ISADevice parent_obj; |
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uint32_t index; |
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uint32_t iobase; |
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uint32_t isairq; |
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ParallelState state; |
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} ISAParallelState; |
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static void parallel_update_irq(ParallelState *s) |
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{ |
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if (s->irq_pending)
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qemu_irq_raise(s->irq); |
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else
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qemu_irq_lower(s->irq); |
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} |
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static void |
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parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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s->dataw = val; |
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parallel_update_irq(s); |
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break;
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case PARA_REG_CTR:
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val |= 0xc0;
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if ((val & PARA_CTR_INIT) == 0 ) { |
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s->status = PARA_STS_BUSY; |
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s->status |= PARA_STS_ACK; |
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s->status |= PARA_STS_ONLINE; |
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s->status |= PARA_STS_ERROR; |
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} |
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else if (val & PARA_CTR_SELECT) { |
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if (val & PARA_CTR_STROBE) {
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s->status &= ~PARA_STS_BUSY; |
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if ((s->control & PARA_CTR_STROBE) == 0) |
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qemu_chr_fe_write(s->chr, &s->dataw, 1);
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} else {
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if (s->control & PARA_CTR_INTEN) {
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s->irq_pending = 1;
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} |
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} |
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} |
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parallel_update_irq(s); |
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s->control = val; |
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break;
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} |
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} |
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static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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ParallelState *s = opaque; |
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uint8_t parm = val; |
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int dir;
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/* Sometimes programs do several writes for timing purposes on old
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HW. Take care not to waste time on writes that do nothing. */
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s->last_read_offset = ~0U;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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if (s->dataw == val)
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return;
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pdebug("wd%02x\n", val);
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
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s->dataw = val; |
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break;
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case PARA_REG_STS:
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pdebug("ws%02x\n", val);
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if (val & PARA_STS_TMOUT)
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s->epp_timeout = 0;
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break;
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case PARA_REG_CTR:
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val |= 0xc0;
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if (s->control == val)
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return;
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pdebug("wc%02x\n", val);
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if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
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if (val & PARA_CTR_DIR) {
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dir = 1;
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} else {
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dir = 0;
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} |
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
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parm &= ~PARA_CTR_DIR; |
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} |
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
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s->control = val; |
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break;
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case PARA_REG_EPP_ADDR:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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/* Controls not correct for EPP address cycle, so do nothing */
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pdebug("wa%02x s\n", val);
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("wa%02x t\n", val);
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} |
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else
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pdebug("wa%02x\n", val);
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} |
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break;
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case PARA_REG_EPP_DATA:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%02x s\n", val);
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else {
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struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; |
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if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("we%02x t\n", val);
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} |
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else
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pdebug("we%02x\n", val);
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} |
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break;
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} |
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} |
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static void |
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parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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uint16_t eppdata = cpu_to_le16(val); |
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int err;
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struct ParallelIOArg ioarg = {
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.buffer = &eppdata, .count = sizeof(eppdata)
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}; |
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%04x s\n", val);
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return;
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} |
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
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if (err) {
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s->epp_timeout = 1;
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pdebug("we%04x t\n", val);
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} |
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else
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pdebug("we%04x\n", val);
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} |
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static void |
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parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
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{ |
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ParallelState *s = opaque; |
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uint32_t eppdata = cpu_to_le32(val); |
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int err;
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struct ParallelIOArg ioarg = {
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.buffer = &eppdata, .count = sizeof(eppdata)
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}; |
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("we%08x s\n", val);
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return;
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} |
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err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
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if (err) {
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s->epp_timeout = 1;
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pdebug("we%08x t\n", val);
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} |
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else
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pdebug("we%08x\n", val);
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} |
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static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
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{ |
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ParallelState *s = opaque; |
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uint32_t ret = 0xff;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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if (s->control & PARA_CTR_DIR)
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ret = s->datar; |
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else
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ret = s->dataw; |
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break;
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case PARA_REG_STS:
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ret = s->status; |
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s->irq_pending = 0;
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if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { |
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/* XXX Fixme: wait 5 microseconds */
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if (s->status & PARA_STS_ACK)
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s->status &= ~PARA_STS_ACK; |
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else {
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/* XXX Fixme: wait 5 microseconds */
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s->status |= PARA_STS_ACK; |
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s->status |= PARA_STS_BUSY; |
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} |
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} |
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parallel_update_irq(s); |
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break;
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case PARA_REG_CTR:
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ret = s->control; |
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break;
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} |
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pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
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return ret;
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} |
298 |
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static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) |
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{ |
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ParallelState *s = opaque; |
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uint8_t ret = 0xff;
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addr &= 7;
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switch(addr) {
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case PARA_REG_DATA:
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
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if (s->last_read_offset != addr || s->datar != ret)
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pdebug("rd%02x\n", ret);
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s->datar = ret; |
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break;
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case PARA_REG_STS:
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qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
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ret &= ~PARA_STS_TMOUT; |
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if (s->epp_timeout)
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ret |= PARA_STS_TMOUT; |
316 |
if (s->last_read_offset != addr || s->status != ret)
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pdebug("rs%02x\n", ret);
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s->status = ret; |
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break;
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case PARA_REG_CTR:
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/* s->control has some bits fixed to 1. It is zero only when
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it has not been yet written to. */
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if (s->control == 0) { |
324 |
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
325 |
if (s->last_read_offset != addr)
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pdebug("rc%02x\n", ret);
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s->control = ret; |
328 |
} |
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else {
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ret = s->control; |
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if (s->last_read_offset != addr)
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pdebug("rc%02x\n", ret);
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} |
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break;
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case PARA_REG_EPP_ADDR:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
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/* Controls not correct for EPP addr cycle, so do nothing */
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pdebug("ra%02x s\n", ret);
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
341 |
if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("ra%02x t\n", ret);
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} |
345 |
else
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pdebug("ra%02x\n", ret);
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} |
348 |
break;
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case PARA_REG_EPP_DATA:
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if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
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/* Controls not correct for EPP data cycle, so do nothing */
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pdebug("re%02x s\n", ret);
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else {
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struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; |
355 |
if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
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s->epp_timeout = 1;
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pdebug("re%02x t\n", ret);
|
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} |
359 |
else
|
360 |
pdebug("re%02x\n", ret);
|
361 |
} |
362 |
break;
|
363 |
} |
364 |
s->last_read_offset = addr; |
365 |
return ret;
|
366 |
} |
367 |
|
368 |
static uint32_t
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parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
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{ |
371 |
ParallelState *s = opaque; |
372 |
uint32_t ret; |
373 |
uint16_t eppdata = ~0;
|
374 |
int err;
|
375 |
struct ParallelIOArg ioarg = {
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376 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
377 |
}; |
378 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
379 |
/* Controls not correct for EPP data cycle, so do nothing */
|
380 |
pdebug("re%04x s\n", eppdata);
|
381 |
return eppdata;
|
382 |
} |
383 |
err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
384 |
ret = le16_to_cpu(eppdata); |
385 |
|
386 |
if (err) {
|
387 |
s->epp_timeout = 1;
|
388 |
pdebug("re%04x t\n", ret);
|
389 |
} |
390 |
else
|
391 |
pdebug("re%04x\n", ret);
|
392 |
return ret;
|
393 |
} |
394 |
|
395 |
static uint32_t
|
396 |
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
397 |
{ |
398 |
ParallelState *s = opaque; |
399 |
uint32_t ret; |
400 |
uint32_t eppdata = ~0U;
|
401 |
int err;
|
402 |
struct ParallelIOArg ioarg = {
|
403 |
.buffer = &eppdata, .count = sizeof(eppdata)
|
404 |
}; |
405 |
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
406 |
/* Controls not correct for EPP data cycle, so do nothing */
|
407 |
pdebug("re%08x s\n", eppdata);
|
408 |
return eppdata;
|
409 |
} |
410 |
err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
411 |
ret = le32_to_cpu(eppdata); |
412 |
|
413 |
if (err) {
|
414 |
s->epp_timeout = 1;
|
415 |
pdebug("re%08x t\n", ret);
|
416 |
} |
417 |
else
|
418 |
pdebug("re%08x\n", ret);
|
419 |
return ret;
|
420 |
} |
421 |
|
422 |
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) |
423 |
{ |
424 |
pdebug("wecp%d=%02x\n", addr & 7, val); |
425 |
} |
426 |
|
427 |
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) |
428 |
{ |
429 |
uint8_t ret = 0xff;
|
430 |
|
431 |
pdebug("recp%d:%02x\n", addr & 7, ret); |
432 |
return ret;
|
433 |
} |
434 |
|
435 |
static void parallel_reset(void *opaque) |
436 |
{ |
437 |
ParallelState *s = opaque; |
438 |
|
439 |
s->datar = ~0;
|
440 |
s->dataw = ~0;
|
441 |
s->status = PARA_STS_BUSY; |
442 |
s->status |= PARA_STS_ACK; |
443 |
s->status |= PARA_STS_ONLINE; |
444 |
s->status |= PARA_STS_ERROR; |
445 |
s->status |= PARA_STS_TMOUT; |
446 |
s->control = PARA_CTR_SELECT; |
447 |
s->control |= PARA_CTR_INIT; |
448 |
s->control |= 0xc0;
|
449 |
s->irq_pending = 0;
|
450 |
s->hw_driver = 0;
|
451 |
s->epp_timeout = 0;
|
452 |
s->last_read_offset = ~0U;
|
453 |
} |
454 |
|
455 |
static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
456 |
|
457 |
static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
458 |
{ 0, 8, 1, |
459 |
.read = parallel_ioport_read_hw, |
460 |
.write = parallel_ioport_write_hw }, |
461 |
{ 4, 1, 2, |
462 |
.read = parallel_ioport_eppdata_read_hw2, |
463 |
.write = parallel_ioport_eppdata_write_hw2 }, |
464 |
{ 4, 1, 4, |
465 |
.read = parallel_ioport_eppdata_read_hw4, |
466 |
.write = parallel_ioport_eppdata_write_hw4 }, |
467 |
{ 0x400, 8, 1, |
468 |
.read = parallel_ioport_ecp_read, |
469 |
.write = parallel_ioport_ecp_write }, |
470 |
PORTIO_END_OF_LIST(), |
471 |
}; |
472 |
|
473 |
static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { |
474 |
{ 0, 8, 1, |
475 |
.read = parallel_ioport_read_sw, |
476 |
.write = parallel_ioport_write_sw }, |
477 |
PORTIO_END_OF_LIST(), |
478 |
}; |
479 |
|
480 |
static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
481 |
{ |
482 |
static int index; |
483 |
ISADevice *isadev = ISA_DEVICE(dev); |
484 |
ISAParallelState *isa = ISA_PARALLEL(dev); |
485 |
ParallelState *s = &isa->state; |
486 |
int base;
|
487 |
uint8_t dummy; |
488 |
|
489 |
if (!s->chr) {
|
490 |
error_setg(errp, "Can't create parallel device, empty char device");
|
491 |
return;
|
492 |
} |
493 |
|
494 |
if (isa->index == -1) { |
495 |
isa->index = index; |
496 |
} |
497 |
if (isa->index >= MAX_PARALLEL_PORTS) {
|
498 |
error_setg(errp, "Max. supported number of parallel ports is %d.",
|
499 |
MAX_PARALLEL_PORTS); |
500 |
return;
|
501 |
} |
502 |
if (isa->iobase == -1) { |
503 |
isa->iobase = isa_parallel_io[isa->index]; |
504 |
} |
505 |
index++; |
506 |
|
507 |
base = isa->iobase; |
508 |
isa_init_irq(isadev, &s->irq, isa->isairq); |
509 |
qemu_register_reset(parallel_reset, s); |
510 |
|
511 |
if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
512 |
s->hw_driver = 1;
|
513 |
s->status = dummy; |
514 |
} |
515 |
|
516 |
isa_register_portio_list(isadev, base, |
517 |
(s->hw_driver |
518 |
? &isa_parallel_portio_hw_list[0]
|
519 |
: &isa_parallel_portio_sw_list[0]),
|
520 |
s, "parallel");
|
521 |
} |
522 |
|
523 |
/* Memory mapped interface */
|
524 |
static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) |
525 |
{ |
526 |
ParallelState *s = opaque; |
527 |
|
528 |
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; |
529 |
} |
530 |
|
531 |
static void parallel_mm_writeb (void *opaque, |
532 |
hwaddr addr, uint32_t value) |
533 |
{ |
534 |
ParallelState *s = opaque; |
535 |
|
536 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
|
537 |
} |
538 |
|
539 |
static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) |
540 |
{ |
541 |
ParallelState *s = opaque; |
542 |
|
543 |
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; |
544 |
} |
545 |
|
546 |
static void parallel_mm_writew (void *opaque, |
547 |
hwaddr addr, uint32_t value) |
548 |
{ |
549 |
ParallelState *s = opaque; |
550 |
|
551 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
|
552 |
} |
553 |
|
554 |
static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) |
555 |
{ |
556 |
ParallelState *s = opaque; |
557 |
|
558 |
return parallel_ioport_read_sw(s, addr >> s->it_shift);
|
559 |
} |
560 |
|
561 |
static void parallel_mm_writel (void *opaque, |
562 |
hwaddr addr, uint32_t value) |
563 |
{ |
564 |
ParallelState *s = opaque; |
565 |
|
566 |
parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
567 |
} |
568 |
|
569 |
static const MemoryRegionOps parallel_mm_ops = { |
570 |
.old_mmio = { |
571 |
.read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, |
572 |
.write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, |
573 |
}, |
574 |
.endianness = DEVICE_NATIVE_ENDIAN, |
575 |
}; |
576 |
|
577 |
/* If fd is zero, it means that the parallel device uses the console */
|
578 |
bool parallel_mm_init(MemoryRegion *address_space,
|
579 |
hwaddr base, int it_shift, qemu_irq irq,
|
580 |
CharDriverState *chr) |
581 |
{ |
582 |
ParallelState *s; |
583 |
|
584 |
s = g_malloc0(sizeof(ParallelState));
|
585 |
s->irq = irq; |
586 |
s->chr = chr; |
587 |
s->it_shift = it_shift; |
588 |
qemu_register_reset(parallel_reset, s); |
589 |
|
590 |
memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s,
|
591 |
"parallel", 8 << it_shift); |
592 |
memory_region_add_subregion(address_space, base, &s->iomem); |
593 |
return true; |
594 |
} |
595 |
|
596 |
static Property parallel_isa_properties[] = {
|
597 |
DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), |
598 |
DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
599 |
DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
600 |
DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
|
601 |
DEFINE_PROP_END_OF_LIST(), |
602 |
}; |
603 |
|
604 |
static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
605 |
{ |
606 |
DeviceClass *dc = DEVICE_CLASS(klass); |
607 |
|
608 |
dc->realize = parallel_isa_realizefn; |
609 |
dc->props = parallel_isa_properties; |
610 |
set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
611 |
} |
612 |
|
613 |
static const TypeInfo parallel_isa_info = { |
614 |
.name = TYPE_ISA_PARALLEL, |
615 |
.parent = TYPE_ISA_DEVICE, |
616 |
.instance_size = sizeof(ISAParallelState),
|
617 |
.class_init = parallel_isa_class_initfn, |
618 |
}; |
619 |
|
620 |
static void parallel_register_types(void) |
621 |
{ |
622 |
type_register_static(¶llel_isa_info); |
623 |
} |
624 |
|
625 |
type_init(parallel_register_types) |