openrisc-timer: Reduce overhead, Separate clock update functions
The clock value is only evaluated when really necessary reducingthe overhead of the timer handling.
This also solves a problem in the way the Linux kernelhandles the timer and the expected accuracy....
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
pc,pci,virtio fixes and cleanups
This includes pc and pci cleanups and enhancements,and a virtio bugfix for level interrupts.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw: Clean up bogus default boot order
We set default boot order "cad" in every single machine definitionexcept "pseries" and "moxiesim", even though very few boards actuallycare for boot order, and "cad" makes sense for even fewer.
Machines that care:...
Merge remote-tracking branch 'stefanha/block' into staging
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
aio / timers: Rename qemu_timer_* functions
Rename four functions in preparation for new API.
Rename qemu_timer_expired to timer_expiredRename qemu_timer_expire_time_ns to timer_expire_time_nsRename qemu_timer_pending to timer_pendingRename qemu_timer_expired_ns to timer_expired_ns...
hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler()
In C99 signed shift (1 << 31) is undefined behavior, since the resultexceeds INT_MAX. Use 1U instead and move the shift after the check.
Signed-off-by: Xi Wang <xi.wang@gmail.com>Acked-by: Jia Liu <proljc@gmail.com>
hw/openrisc: Fix masking in openrisc_pic_cpu_handler()
Consider the masking of PICSR and PICMR:
((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i)))
To correctly mask bits, we should use the bitwise AND "&" rather thanthe logical AND "&&". Also, the loop is not necessary for masking....
hw/openrisc: Avoid using uninitialised variable 'entry'
clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used uninitializedwhenever '&&' condition is false [-Werror,-Wsometimes-uninitialized]...
hw/openrisc: Use stderr output instead of qemu_log
We should use stderr output instead of qemu_log in order to output ErrMsgonto the screen.
Signed-off-by: Jia Liu <proljc@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Andreas Färber <afaerber@suse.de>
hw/openrisc: Indent typo
Indent typo.
memory: add owner argument to initialization functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
hw: move headers to include/
Many of these should be cleaned up with proper qdev-/QOM-ification.Right now there are many catch-all headers in include/hw/ARCH dependingon cpu.h, and this makes it necessary to compile these files per-target.However, fixing this does not belong in these patches....
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
exec: Pass CPUState to cpu_reset_interrupt()
Move it to qom/cpu.c to avoid build failures depending on include orderof cpu-qom.h and exec/cpu-all.h.
Change opaques of various ..._irq_handler() functions to theappropriate CPU type to facilitate using cpu_reset_interrupt()....
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
hw: move boards and other isolated files to hw/ARCH
target-or32: Add timer support
Add OpenRISC timer support.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-or32: Add a IIS dummy board
Add a IIS dummy board.
target-or32: Add PIC support
Add OpenRISC Programmable Interrupt Controller support.
target-or32: Add target stubs and QOM cpu
Add OpenRISC target stubs, QOM cpu and basic machine.