root / hw / pci.h @ f6dc18df
History | View | Annotate | Download (14.2 kB)
1 | 87ecb68b | pbrook | #ifndef QEMU_PCI_H
|
---|---|---|---|
2 | 87ecb68b | pbrook | #define QEMU_PCI_H
|
3 | 87ecb68b | pbrook | |
4 | 376253ec | aliguori | #include "qemu-common.h" |
5 | 376253ec | aliguori | |
6 | 6b1b92d3 | Paul Brook | #include "qdev.h" |
7 | 6b1b92d3 | Paul Brook | |
8 | 87ecb68b | pbrook | /* PCI includes legacy ISA access. */
|
9 | 87ecb68b | pbrook | #include "isa.h" |
10 | 87ecb68b | pbrook | |
11 | 87ecb68b | pbrook | /* PCI bus */
|
12 | 87ecb68b | pbrook | |
13 | c227f099 | Anthony Liguori | extern target_phys_addr_t pci_mem_base;
|
14 | 87ecb68b | pbrook | |
15 | 3ae80618 | aliguori | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
16 | 3ae80618 | aliguori | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
17 | 3ae80618 | aliguori | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
18 | 3ae80618 | aliguori | |
19 | a770dc7e | aliguori | /* Class, Vendor and Device IDs from Linux's pci_ids.h */
|
20 | a770dc7e | aliguori | #include "pci_ids.h" |
21 | 173a543b | blueswir1 | |
22 | a770dc7e | aliguori | /* QEMU-specific Vendor and Device ID definitions */
|
23 | 6f338c34 | aliguori | |
24 | a770dc7e | aliguori | /* IBM (0x1014) */
|
25 | a770dc7e | aliguori | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
26 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
27 | deb54399 | aliguori | |
28 | a770dc7e | aliguori | /* Hitachi (0x1054) */
|
29 | deb54399 | aliguori | #define PCI_VENDOR_ID_HITACHI 0x1054 |
30 | a770dc7e | aliguori | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
31 | deb54399 | aliguori | |
32 | a770dc7e | aliguori | /* Apple (0x106b) */
|
33 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
34 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
35 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
36 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
37 | a770dc7e | aliguori | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
38 | deb54399 | aliguori | |
39 | a770dc7e | aliguori | /* Realtek (0x10ec) */
|
40 | a770dc7e | aliguori | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
41 | deb54399 | aliguori | |
42 | a770dc7e | aliguori | /* Xilinx (0x10ee) */
|
43 | a770dc7e | aliguori | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
44 | deb54399 | aliguori | |
45 | a770dc7e | aliguori | /* Marvell (0x11ab) */
|
46 | a770dc7e | aliguori | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
47 | deb54399 | aliguori | |
48 | a770dc7e | aliguori | /* QEMU/Bochs VGA (0x1234) */
|
49 | 4ebcf884 | blueswir1 | #define PCI_VENDOR_ID_QEMU 0x1234 |
50 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
51 | 4ebcf884 | blueswir1 | |
52 | a770dc7e | aliguori | /* VMWare (0x15ad) */
|
53 | deb54399 | aliguori | #define PCI_VENDOR_ID_VMWARE 0x15ad |
54 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
55 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
56 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
57 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
58 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
59 | deb54399 | aliguori | |
60 | cef3017c | aliguori | /* Intel (0x8086) */
|
61 | a770dc7e | aliguori | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
62 | d6fd1e66 | Stefan Weil | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
63 | 74c62ba8 | aurel32 | |
64 | deb54399 | aliguori | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
|
65 | d350d97d | aliguori | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
66 | d350d97d | aliguori | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
67 | d350d97d | aliguori | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
68 | d350d97d | aliguori | |
69 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
70 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
71 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
72 | 14d50bef | aliguori | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
73 | d350d97d | aliguori | |
74 | 4f8589e1 | Isaku Yamahata | typedef uint64_t pcibus_t;
|
75 | 4f8589e1 | Isaku Yamahata | #define FMT_PCIBUS PRIx64
|
76 | 6e355d90 | Isaku Yamahata | |
77 | 87ecb68b | pbrook | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
78 | 87ecb68b | pbrook | uint32_t address, uint32_t data, int len);
|
79 | 87ecb68b | pbrook | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
80 | 87ecb68b | pbrook | uint32_t address, int len);
|
81 | 87ecb68b | pbrook | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
82 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type);
|
83 | 5851e08c | aliguori | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
84 | 87ecb68b | pbrook | |
85 | 87ecb68b | pbrook | typedef struct PCIIORegion { |
86 | 6e355d90 | Isaku Yamahata | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
|
87 | 6e355d90 | Isaku Yamahata | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
88 | 6e355d90 | Isaku Yamahata | pcibus_t size; |
89 | a0c7a97e | Isaku Yamahata | pcibus_t filtered_size; |
90 | 87ecb68b | pbrook | uint8_t type; |
91 | 87ecb68b | pbrook | PCIMapIORegionFunc *map_func; |
92 | 87ecb68b | pbrook | } PCIIORegion; |
93 | 87ecb68b | pbrook | |
94 | 87ecb68b | pbrook | #define PCI_ROM_SLOT 6 |
95 | 87ecb68b | pbrook | #define PCI_NUM_REGIONS 7 |
96 | 87ecb68b | pbrook | |
97 | cef3017c | aliguori | /* Declarations from linux/pci_regs.h */
|
98 | 87ecb68b | pbrook | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
99 | 87ecb68b | pbrook | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
100 | 87ecb68b | pbrook | #define PCI_COMMAND 0x04 /* 16 bits */ |
101 | 87ecb68b | pbrook | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
102 | 87ecb68b | pbrook | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
103 | b7ee1603 | Michael S. Tsirkin | #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ |
104 | cef3017c | aliguori | #define PCI_STATUS 0x06 /* 16 bits */ |
105 | f9bf77dd | Michael S. Tsirkin | #define PCI_STATUS_INTERRUPT 0x08 |
106 | cef3017c | aliguori | #define PCI_REVISION_ID 0x08 /* 8 bits */ |
107 | bd4b65ee | Michael S. Tsirkin | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
108 | 87ecb68b | pbrook | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
109 | b7ee1603 | Michael S. Tsirkin | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
110 | b7ee1603 | Michael S. Tsirkin | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
111 | cef3017c | aliguori | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
112 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_NORMAL 0 |
113 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_BRIDGE 1 |
114 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_CARDBUS 2 |
115 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
116 | b7ee1603 | Michael S. Tsirkin | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
117 | 0392a017 | Isaku Yamahata | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
118 | 0392a017 | Isaku Yamahata | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
119 | 14421258 | Isaku Yamahata | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
120 | 0392a017 | Isaku Yamahata | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
121 | b7ee1603 | Michael S. Tsirkin | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ |
122 | b7ee1603 | Michael S. Tsirkin | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ |
123 | e822a52a | Isaku Yamahata | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ |
124 | fb231628 | Isaku Yamahata | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ |
125 | fb231628 | Isaku Yamahata | #define PCI_IO_LIMIT 0x1d |
126 | a0c7a97e | Isaku Yamahata | #define PCI_IO_RANGE_TYPE_32 0x01 |
127 | fb231628 | Isaku Yamahata | #define PCI_IO_RANGE_MASK (~0x0fUL) |
128 | b7ee1603 | Michael S. Tsirkin | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
129 | fb231628 | Isaku Yamahata | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
130 | fb231628 | Isaku Yamahata | #define PCI_MEMORY_LIMIT 0x22 |
131 | fb231628 | Isaku Yamahata | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) |
132 | fb231628 | Isaku Yamahata | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ |
133 | fb231628 | Isaku Yamahata | #define PCI_PREF_MEMORY_LIMIT 0x26 |
134 | fb231628 | Isaku Yamahata | #define PCI_PREF_RANGE_MASK (~0x0fUL) |
135 | d46636b8 | Isaku Yamahata | #define PCI_PREF_RANGE_TYPE_64 0x01 |
136 | fb231628 | Isaku Yamahata | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ |
137 | a0c7a97e | Isaku Yamahata | #define PCI_PREF_LIMIT_UPPER32 0x2c |
138 | cef3017c | aliguori | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ |
139 | cef3017c | aliguori | #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ |
140 | 5330de09 | Michael S. Tsirkin | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
141 | 5330de09 | Michael S. Tsirkin | #define PCI_ROM_ADDRESS_ENABLE 0x01 |
142 | fb231628 | Isaku Yamahata | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ |
143 | fb231628 | Isaku Yamahata | #define PCI_IO_LIMIT_UPPER16 0x32 |
144 | b7ee1603 | Michael S. Tsirkin | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
145 | b3b11697 | Isaku Yamahata | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
146 | 87ecb68b | pbrook | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
147 | 87ecb68b | pbrook | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
148 | 87ecb68b | pbrook | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
149 | fb231628 | Isaku Yamahata | #define PCI_BRIDGE_CONTROL 0x3e |
150 | 87ecb68b | pbrook | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
151 | 87ecb68b | pbrook | |
152 | 6f4cbd39 | Michael S. Tsirkin | /* Capability lists */
|
153 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
154 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
155 | 6f4cbd39 | Michael S. Tsirkin | |
156 | cef3017c | aliguori | #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */ |
157 | cef3017c | aliguori | #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */ |
158 | cef3017c | aliguori | #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */ |
159 | cef3017c | aliguori | |
160 | 8098ed41 | aurel32 | /* Bits in the PCI Status Register (PCI 2.3 spec) */
|
161 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED1 0x007 |
162 | 8098ed41 | aurel32 | #define PCI_STATUS_INT_STATUS 0x008 |
163 | 6f4cbd39 | Michael S. Tsirkin | #define PCI_STATUS_CAP_LIST 0x010 |
164 | 8098ed41 | aurel32 | #define PCI_STATUS_66MHZ 0x020 |
165 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED2 0x040 |
166 | 8098ed41 | aurel32 | #define PCI_STATUS_FAST_BACK 0x080 |
167 | 8098ed41 | aurel32 | #define PCI_STATUS_DEVSEL 0x600 |
168 | 8098ed41 | aurel32 | |
169 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
|
170 | 8098ed41 | aurel32 | PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \ |
171 | 8098ed41 | aurel32 | PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK) |
172 | 8098ed41 | aurel32 | |
173 | 8098ed41 | aurel32 | #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) |
174 | 8098ed41 | aurel32 | |
175 | 475dc65f | aurel32 | /* Bits in the PCI Command Register (PCI 2.3 spec) */
|
176 | 475dc65f | aurel32 | #define PCI_COMMAND_RESERVED 0xf800 |
177 | 475dc65f | aurel32 | |
178 | 475dc65f | aurel32 | #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) |
179 | 475dc65f | aurel32 | |
180 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config header */
|
181 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_HEADER_SIZE 0x40 |
182 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config space */
|
183 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_SPACE_SIZE 0x100 |
184 | a9f49946 | Isaku Yamahata | /* Size of the standart PCIe config space: 4KB */
|
185 | a9f49946 | Isaku Yamahata | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
186 | b7ee1603 | Michael S. Tsirkin | |
187 | e369cad7 | Isaku Yamahata | #define PCI_NUM_PINS 4 /* A-D */ |
188 | e369cad7 | Isaku Yamahata | |
189 | 02eb84d0 | Michael S. Tsirkin | /* Bits in cap_present field. */
|
190 | 02eb84d0 | Michael S. Tsirkin | enum {
|
191 | 02eb84d0 | Michael S. Tsirkin | QEMU_PCI_CAP_MSIX = 0x1,
|
192 | a9f49946 | Isaku Yamahata | QEMU_PCI_CAP_EXPRESS = 0x2,
|
193 | 02eb84d0 | Michael S. Tsirkin | }; |
194 | 02eb84d0 | Michael S. Tsirkin | |
195 | 87ecb68b | pbrook | struct PCIDevice {
|
196 | 6b1b92d3 | Paul Brook | DeviceState qdev; |
197 | 87ecb68b | pbrook | /* PCI config space */
|
198 | a9f49946 | Isaku Yamahata | uint8_t *config; |
199 | b7ee1603 | Michael S. Tsirkin | |
200 | bd4b65ee | Michael S. Tsirkin | /* Used to enable config checks on load. Note that writeable bits are
|
201 | bd4b65ee | Michael S. Tsirkin | * never checked even if set in cmask. */
|
202 | a9f49946 | Isaku Yamahata | uint8_t *cmask; |
203 | bd4b65ee | Michael S. Tsirkin | |
204 | b7ee1603 | Michael S. Tsirkin | /* Used to implement R/W bytes */
|
205 | a9f49946 | Isaku Yamahata | uint8_t *wmask; |
206 | 87ecb68b | pbrook | |
207 | 6f4cbd39 | Michael S. Tsirkin | /* Used to allocate config space for capabilities. */
|
208 | a9f49946 | Isaku Yamahata | uint8_t *used; |
209 | 6f4cbd39 | Michael S. Tsirkin | |
210 | 87ecb68b | pbrook | /* the following fields are read only */
|
211 | 87ecb68b | pbrook | PCIBus *bus; |
212 | 54586bd1 | Gerd Hoffmann | uint32_t devfn; |
213 | 87ecb68b | pbrook | char name[64]; |
214 | 87ecb68b | pbrook | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
215 | 87ecb68b | pbrook | |
216 | 87ecb68b | pbrook | /* do not access the following fields */
|
217 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read; |
218 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write; |
219 | 87ecb68b | pbrook | |
220 | 87ecb68b | pbrook | /* IRQ objects for the INTA-INTD pins. */
|
221 | 87ecb68b | pbrook | qemu_irq *irq; |
222 | 87ecb68b | pbrook | |
223 | 87ecb68b | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
|
224 | d036bb21 | Michael S. Tsirkin | uint8_t irq_state; |
225 | 02eb84d0 | Michael S. Tsirkin | |
226 | 02eb84d0 | Michael S. Tsirkin | /* Capability bits */
|
227 | 02eb84d0 | Michael S. Tsirkin | uint32_t cap_present; |
228 | 02eb84d0 | Michael S. Tsirkin | |
229 | 02eb84d0 | Michael S. Tsirkin | /* Offset of MSI-X capability in config space */
|
230 | 02eb84d0 | Michael S. Tsirkin | uint8_t msix_cap; |
231 | 02eb84d0 | Michael S. Tsirkin | |
232 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X entries */
|
233 | 02eb84d0 | Michael S. Tsirkin | int msix_entries_nr;
|
234 | 02eb84d0 | Michael S. Tsirkin | |
235 | 02eb84d0 | Michael S. Tsirkin | /* Space to store MSIX table */
|
236 | 02eb84d0 | Michael S. Tsirkin | uint8_t *msix_table_page; |
237 | 02eb84d0 | Michael S. Tsirkin | /* MMIO index used to map MSIX table and pending bit entries. */
|
238 | 02eb84d0 | Michael S. Tsirkin | int msix_mmio_index;
|
239 | 02eb84d0 | Michael S. Tsirkin | /* Reference-count for entries actually in use by driver. */
|
240 | 02eb84d0 | Michael S. Tsirkin | unsigned *msix_entry_used;
|
241 | 02eb84d0 | Michael S. Tsirkin | /* Region including the MSI-X table */
|
242 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size; |
243 | f16c4abf | Juan Quintela | /* Version id needed for VMState */
|
244 | f16c4abf | Juan Quintela | int32_t version_id; |
245 | c2039bd0 | Anthony Liguori | |
246 | c2039bd0 | Anthony Liguori | /* Location of option rom */
|
247 | 8c52c8f3 | Gerd Hoffmann | char *romfile;
|
248 | c2039bd0 | Anthony Liguori | ram_addr_t rom_offset; |
249 | 87ecb68b | pbrook | }; |
250 | 87ecb68b | pbrook | |
251 | 87ecb68b | pbrook | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
252 | 87ecb68b | pbrook | int instance_size, int devfn, |
253 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read, |
254 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write); |
255 | 87ecb68b | pbrook | |
256 | 28c2c264 | Avi Kivity | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
257 | 6e355d90 | Isaku Yamahata | pcibus_t size, int type,
|
258 | 87ecb68b | pbrook | PCIMapIORegionFunc *map_func); |
259 | 87ecb68b | pbrook | |
260 | 6f4cbd39 | Michael S. Tsirkin | int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
261 | 6f4cbd39 | Michael S. Tsirkin | |
262 | 6f4cbd39 | Michael S. Tsirkin | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
263 | 6f4cbd39 | Michael S. Tsirkin | |
264 | 6f4cbd39 | Michael S. Tsirkin | void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
|
265 | 6f4cbd39 | Michael S. Tsirkin | |
266 | 6f4cbd39 | Michael S. Tsirkin | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
267 | 6f4cbd39 | Michael S. Tsirkin | |
268 | 6f4cbd39 | Michael S. Tsirkin | |
269 | 87ecb68b | pbrook | uint32_t pci_default_read_config(PCIDevice *d, |
270 | 87ecb68b | pbrook | uint32_t address, int len);
|
271 | 87ecb68b | pbrook | void pci_default_write_config(PCIDevice *d,
|
272 | 87ecb68b | pbrook | uint32_t address, uint32_t val, int len);
|
273 | 87ecb68b | pbrook | void pci_device_save(PCIDevice *s, QEMUFile *f);
|
274 | 87ecb68b | pbrook | int pci_device_load(PCIDevice *s, QEMUFile *f);
|
275 | 87ecb68b | pbrook | |
276 | 5d4e84c8 | Juan Quintela | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
277 | 87ecb68b | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
278 | ee995ffb | Gerd Hoffmann | typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state); |
279 | 21eea4b3 | Gerd Hoffmann | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
280 | 21eea4b3 | Gerd Hoffmann | const char *name, int devfn_min); |
281 | 21eea4b3 | Gerd Hoffmann | PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min); |
282 | 21eea4b3 | Gerd Hoffmann | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
283 | 21eea4b3 | Gerd Hoffmann | void *irq_opaque, int nirq); |
284 | ee995ffb | Gerd Hoffmann | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
|
285 | 02e2da45 | Paul Brook | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
286 | 02e2da45 | Paul Brook | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
287 | 5d4e84c8 | Juan Quintela | void *irq_opaque, int devfn_min, int nirq); |
288 | 87ecb68b | pbrook | |
289 | 5607c388 | Markus Armbruster | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
290 | 5607c388 | Markus Armbruster | const char *default_devaddr); |
291 | 07caea31 | Markus Armbruster | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
292 | 07caea31 | Markus Armbruster | const char *default_devaddr); |
293 | 87ecb68b | pbrook | int pci_bus_num(PCIBus *s);
|
294 | e822a52a | Isaku Yamahata | void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
295 | c469e1dd | Isaku Yamahata | PCIBus *pci_find_root_bus(int domain);
|
296 | e822a52a | Isaku Yamahata | PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
|
297 | e822a52a | Isaku Yamahata | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function); |
298 | 49bd1458 | Markus Armbruster | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
299 | 87ecb68b | pbrook | |
300 | e9283f8b | Jan Kiszka | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
301 | e9283f8b | Jan Kiszka | unsigned *slotp);
|
302 | 880345c4 | aliguori | |
303 | 376253ec | aliguori | void pci_info(Monitor *mon);
|
304 | 480b9f24 | blueswir1 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
305 | 87ecb68b | pbrook | pci_map_irq_fn map_irq, const char *name); |
306 | d6318738 | Michael S. Tsirkin | PCIDevice *pci_bridge_get_device(PCIBus *bus); |
307 | 87ecb68b | pbrook | |
308 | deb54399 | aliguori | static inline void |
309 | 64d50b8b | Michael S. Tsirkin | pci_set_byte(uint8_t *config, uint8_t val) |
310 | 64d50b8b | Michael S. Tsirkin | { |
311 | 64d50b8b | Michael S. Tsirkin | *config = val; |
312 | 64d50b8b | Michael S. Tsirkin | } |
313 | 64d50b8b | Michael S. Tsirkin | |
314 | 64d50b8b | Michael S. Tsirkin | static inline uint8_t |
315 | 64d50b8b | Michael S. Tsirkin | pci_get_byte(uint8_t *config) |
316 | 64d50b8b | Michael S. Tsirkin | { |
317 | 64d50b8b | Michael S. Tsirkin | return *config;
|
318 | 64d50b8b | Michael S. Tsirkin | } |
319 | 64d50b8b | Michael S. Tsirkin | |
320 | 64d50b8b | Michael S. Tsirkin | static inline void |
321 | 14e12559 | Michael S. Tsirkin | pci_set_word(uint8_t *config, uint16_t val) |
322 | 14e12559 | Michael S. Tsirkin | { |
323 | 14e12559 | Michael S. Tsirkin | cpu_to_le16wu((uint16_t *)config, val); |
324 | 14e12559 | Michael S. Tsirkin | } |
325 | 14e12559 | Michael S. Tsirkin | |
326 | 14e12559 | Michael S. Tsirkin | static inline uint16_t |
327 | 14e12559 | Michael S. Tsirkin | pci_get_word(uint8_t *config) |
328 | 14e12559 | Michael S. Tsirkin | { |
329 | 14e12559 | Michael S. Tsirkin | return le16_to_cpupu((uint16_t *)config);
|
330 | 14e12559 | Michael S. Tsirkin | } |
331 | 14e12559 | Michael S. Tsirkin | |
332 | 14e12559 | Michael S. Tsirkin | static inline void |
333 | 14e12559 | Michael S. Tsirkin | pci_set_long(uint8_t *config, uint32_t val) |
334 | 14e12559 | Michael S. Tsirkin | { |
335 | 14e12559 | Michael S. Tsirkin | cpu_to_le32wu((uint32_t *)config, val); |
336 | 14e12559 | Michael S. Tsirkin | } |
337 | 14e12559 | Michael S. Tsirkin | |
338 | 14e12559 | Michael S. Tsirkin | static inline uint32_t |
339 | 14e12559 | Michael S. Tsirkin | pci_get_long(uint8_t *config) |
340 | 14e12559 | Michael S. Tsirkin | { |
341 | 14e12559 | Michael S. Tsirkin | return le32_to_cpupu((uint32_t *)config);
|
342 | 14e12559 | Michael S. Tsirkin | } |
343 | 14e12559 | Michael S. Tsirkin | |
344 | 14e12559 | Michael S. Tsirkin | static inline void |
345 | fb5ce7d2 | Isaku Yamahata | pci_set_quad(uint8_t *config, uint64_t val) |
346 | fb5ce7d2 | Isaku Yamahata | { |
347 | fb5ce7d2 | Isaku Yamahata | cpu_to_le64w((uint64_t *)config, val); |
348 | fb5ce7d2 | Isaku Yamahata | } |
349 | fb5ce7d2 | Isaku Yamahata | |
350 | fb5ce7d2 | Isaku Yamahata | static inline uint64_t |
351 | fb5ce7d2 | Isaku Yamahata | pci_get_quad(uint8_t *config) |
352 | fb5ce7d2 | Isaku Yamahata | { |
353 | fb5ce7d2 | Isaku Yamahata | return le64_to_cpup((uint64_t *)config);
|
354 | fb5ce7d2 | Isaku Yamahata | } |
355 | fb5ce7d2 | Isaku Yamahata | |
356 | fb5ce7d2 | Isaku Yamahata | static inline void |
357 | deb54399 | aliguori | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
358 | deb54399 | aliguori | { |
359 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
360 | deb54399 | aliguori | } |
361 | deb54399 | aliguori | |
362 | deb54399 | aliguori | static inline void |
363 | deb54399 | aliguori | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
364 | deb54399 | aliguori | { |
365 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
366 | deb54399 | aliguori | } |
367 | deb54399 | aliguori | |
368 | 173a543b | blueswir1 | static inline void |
369 | 173a543b | blueswir1 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
370 | 173a543b | blueswir1 | { |
371 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
372 | 173a543b | blueswir1 | } |
373 | 173a543b | blueswir1 | |
374 | 81a322d4 | Gerd Hoffmann | typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
375 | 0aab0d3a | Gerd Hoffmann | typedef struct { |
376 | 0aab0d3a | Gerd Hoffmann | DeviceInfo qdev; |
377 | 0aab0d3a | Gerd Hoffmann | pci_qdev_initfn init; |
378 | e3936fa5 | Gerd Hoffmann | PCIUnregisterFunc *exit; |
379 | 0aab0d3a | Gerd Hoffmann | PCIConfigReadFunc *config_read; |
380 | 0aab0d3a | Gerd Hoffmann | PCIConfigWriteFunc *config_write; |
381 | a9f49946 | Isaku Yamahata | |
382 | fb231628 | Isaku Yamahata | /* pci config header type */
|
383 | 3c217c14 | Isaku Yamahata | uint8_t header_type; |
384 | fb231628 | Isaku Yamahata | |
385 | a9f49946 | Isaku Yamahata | /* pcie stuff */
|
386 | 3c217c14 | Isaku Yamahata | int is_express; /* is this device pci express? */ |
387 | 8c52c8f3 | Gerd Hoffmann | |
388 | 8c52c8f3 | Gerd Hoffmann | /* rom bar */
|
389 | 8c52c8f3 | Gerd Hoffmann | const char *romfile; |
390 | 0aab0d3a | Gerd Hoffmann | } PCIDeviceInfo; |
391 | 0aab0d3a | Gerd Hoffmann | |
392 | 0aab0d3a | Gerd Hoffmann | void pci_qdev_register(PCIDeviceInfo *info);
|
393 | 0aab0d3a | Gerd Hoffmann | void pci_qdev_register_many(PCIDeviceInfo *info);
|
394 | 6b1b92d3 | Paul Brook | |
395 | 499cf102 | Markus Armbruster | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
396 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
397 | 6b1b92d3 | Paul Brook | |
398 | a9f49946 | Isaku Yamahata | static inline int pci_is_express(PCIDevice *d) |
399 | a9f49946 | Isaku Yamahata | { |
400 | a9f49946 | Isaku Yamahata | return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
401 | a9f49946 | Isaku Yamahata | } |
402 | a9f49946 | Isaku Yamahata | |
403 | a9f49946 | Isaku Yamahata | static inline uint32_t pci_config_size(PCIDevice *d) |
404 | a9f49946 | Isaku Yamahata | { |
405 | a9f49946 | Isaku Yamahata | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
406 | a9f49946 | Isaku Yamahata | } |
407 | a9f49946 | Isaku Yamahata | |
408 | f49db805 | Isaku Yamahata | /* These are not pci specific. Should move into a separate header.
|
409 | f49db805 | Isaku Yamahata | * Only pci.c uses them, so keep them here for now.
|
410 | f49db805 | Isaku Yamahata | */
|
411 | f49db805 | Isaku Yamahata | |
412 | f49db805 | Isaku Yamahata | /* Get last byte of a range from offset + length.
|
413 | f49db805 | Isaku Yamahata | * Undefined for ranges that wrap around 0. */
|
414 | f49db805 | Isaku Yamahata | static inline uint64_t range_get_last(uint64_t offset, uint64_t len) |
415 | f49db805 | Isaku Yamahata | { |
416 | f49db805 | Isaku Yamahata | return offset + len - 1; |
417 | f49db805 | Isaku Yamahata | } |
418 | f49db805 | Isaku Yamahata | |
419 | f49db805 | Isaku Yamahata | /* Check whether a given range covers a given byte. */
|
420 | f49db805 | Isaku Yamahata | static inline int range_covers_byte(uint64_t offset, uint64_t len, |
421 | f49db805 | Isaku Yamahata | uint64_t byte) |
422 | f49db805 | Isaku Yamahata | { |
423 | f49db805 | Isaku Yamahata | return offset <= byte && byte <= range_get_last(offset, len);
|
424 | f49db805 | Isaku Yamahata | } |
425 | f49db805 | Isaku Yamahata | |
426 | f49db805 | Isaku Yamahata | /* Check whether 2 given ranges overlap.
|
427 | f49db805 | Isaku Yamahata | * Undefined if ranges that wrap around 0. */
|
428 | f49db805 | Isaku Yamahata | static inline int ranges_overlap(uint64_t first1, uint64_t len1, |
429 | f49db805 | Isaku Yamahata | uint64_t first2, uint64_t len2) |
430 | f49db805 | Isaku Yamahata | { |
431 | f49db805 | Isaku Yamahata | uint64_t last1 = range_get_last(first1, len1); |
432 | f49db805 | Isaku Yamahata | uint64_t last2 = range_get_last(first2, len2); |
433 | f49db805 | Isaku Yamahata | |
434 | f49db805 | Isaku Yamahata | return !(last2 < first1 || last1 < first2);
|
435 | f49db805 | Isaku Yamahata | } |
436 | f49db805 | Isaku Yamahata | |
437 | 87ecb68b | pbrook | #endif |