root / tcg / x86_64 / tcg-target.c @ f878d2d2
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | d4a9eb1f | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
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26 | d4a9eb1f | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | c896fe29 | bellard | "%rax",
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28 | c896fe29 | bellard | "%rcx",
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29 | c896fe29 | bellard | "%rdx",
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30 | c896fe29 | bellard | "%rbx",
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31 | c896fe29 | bellard | "%rsp",
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32 | c896fe29 | bellard | "%rbp",
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33 | c896fe29 | bellard | "%rsi",
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34 | c896fe29 | bellard | "%rdi",
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35 | c896fe29 | bellard | "%r8",
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36 | c896fe29 | bellard | "%r9",
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37 | c896fe29 | bellard | "%r10",
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38 | c896fe29 | bellard | "%r11",
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39 | c896fe29 | bellard | "%r12",
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40 | c896fe29 | bellard | "%r13",
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41 | c896fe29 | bellard | "%r14",
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42 | c896fe29 | bellard | "%r15",
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43 | c896fe29 | bellard | }; |
44 | d4a9eb1f | blueswir1 | #endif
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45 | c896fe29 | bellard | |
46 | d4a9eb1f | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
47 | c896fe29 | bellard | TCG_REG_RBP, |
48 | c896fe29 | bellard | TCG_REG_RBX, |
49 | c896fe29 | bellard | TCG_REG_R12, |
50 | c896fe29 | bellard | TCG_REG_R13, |
51 | c896fe29 | bellard | TCG_REG_R14, |
52 | c896fe29 | bellard | TCG_REG_R15, |
53 | 79d342dc | aurel32 | TCG_REG_R10, |
54 | 79d342dc | aurel32 | TCG_REG_R11, |
55 | 79d342dc | aurel32 | TCG_REG_R9, |
56 | 79d342dc | aurel32 | TCG_REG_R8, |
57 | 79d342dc | aurel32 | TCG_REG_RCX, |
58 | 79d342dc | aurel32 | TCG_REG_RDX, |
59 | 79d342dc | aurel32 | TCG_REG_RSI, |
60 | 79d342dc | aurel32 | TCG_REG_RDI, |
61 | 79d342dc | aurel32 | TCG_REG_RAX, |
62 | c896fe29 | bellard | }; |
63 | c896fe29 | bellard | |
64 | d4a9eb1f | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
65 | c896fe29 | bellard | TCG_REG_RDI, |
66 | c896fe29 | bellard | TCG_REG_RSI, |
67 | c896fe29 | bellard | TCG_REG_RDX, |
68 | c896fe29 | bellard | TCG_REG_RCX, |
69 | c896fe29 | bellard | TCG_REG_R8, |
70 | c896fe29 | bellard | TCG_REG_R9, |
71 | c896fe29 | bellard | }; |
72 | c896fe29 | bellard | |
73 | d4a9eb1f | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
74 | c896fe29 | bellard | TCG_REG_RAX, |
75 | c896fe29 | bellard | TCG_REG_RDX |
76 | c896fe29 | bellard | }; |
77 | c896fe29 | bellard | |
78 | b03cce8e | bellard | static uint8_t *tb_ret_addr;
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79 | b03cce8e | bellard | |
80 | c896fe29 | bellard | static void patch_reloc(uint8_t *code_ptr, int type, |
81 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
82 | c896fe29 | bellard | { |
83 | f54b3f92 | aurel32 | value += addend; |
84 | c896fe29 | bellard | switch(type) {
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85 | c896fe29 | bellard | case R_X86_64_32:
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86 | c896fe29 | bellard | if (value != (uint32_t)value)
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87 | c896fe29 | bellard | tcg_abort(); |
88 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
89 | c896fe29 | bellard | break;
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90 | c896fe29 | bellard | case R_X86_64_32S:
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91 | c896fe29 | bellard | if (value != (int32_t)value)
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92 | c896fe29 | bellard | tcg_abort(); |
93 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
94 | c896fe29 | bellard | break;
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95 | c896fe29 | bellard | case R_386_PC32:
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96 | c896fe29 | bellard | value -= (long)code_ptr;
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97 | c896fe29 | bellard | if (value != (int32_t)value)
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98 | c896fe29 | bellard | tcg_abort(); |
99 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
100 | c896fe29 | bellard | break;
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101 | c896fe29 | bellard | default:
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102 | c896fe29 | bellard | tcg_abort(); |
103 | c896fe29 | bellard | } |
104 | c896fe29 | bellard | } |
105 | c896fe29 | bellard | |
106 | c896fe29 | bellard | /* maximum number of register used for input function arguments */
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107 | c896fe29 | bellard | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
108 | c896fe29 | bellard | { |
109 | c896fe29 | bellard | return 6; |
110 | c896fe29 | bellard | } |
111 | c896fe29 | bellard | |
112 | c896fe29 | bellard | /* parse target specific constraints */
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113 | 8fcd3692 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
114 | c896fe29 | bellard | { |
115 | c896fe29 | bellard | const char *ct_str; |
116 | c896fe29 | bellard | |
117 | c896fe29 | bellard | ct_str = *pct_str; |
118 | c896fe29 | bellard | switch(ct_str[0]) { |
119 | c896fe29 | bellard | case 'a': |
120 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
121 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
122 | c896fe29 | bellard | break;
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123 | c896fe29 | bellard | case 'b': |
124 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
125 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
126 | c896fe29 | bellard | break;
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127 | c896fe29 | bellard | case 'c': |
128 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
129 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
130 | c896fe29 | bellard | break;
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131 | c896fe29 | bellard | case 'd': |
132 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
133 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
134 | c896fe29 | bellard | break;
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135 | c896fe29 | bellard | case 'S': |
136 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
137 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
138 | c896fe29 | bellard | break;
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139 | c896fe29 | bellard | case 'D': |
140 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
141 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
142 | c896fe29 | bellard | break;
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143 | c896fe29 | bellard | case 'q': |
144 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
145 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xf); |
146 | c896fe29 | bellard | break;
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147 | c896fe29 | bellard | case 'r': |
148 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
149 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
150 | c896fe29 | bellard | break;
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151 | c896fe29 | bellard | case 'L': /* qemu_ld/st constraint */ |
152 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
153 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
154 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
155 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
156 | c896fe29 | bellard | break;
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157 | c896fe29 | bellard | case 'e': |
158 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_S32; |
159 | c896fe29 | bellard | break;
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160 | c896fe29 | bellard | case 'Z': |
161 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_U32; |
162 | c896fe29 | bellard | break;
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163 | c896fe29 | bellard | default:
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164 | c896fe29 | bellard | return -1; |
165 | c896fe29 | bellard | } |
166 | c896fe29 | bellard | ct_str++; |
167 | c896fe29 | bellard | *pct_str = ct_str; |
168 | c896fe29 | bellard | return 0; |
169 | c896fe29 | bellard | } |
170 | c896fe29 | bellard | |
171 | c896fe29 | bellard | /* test if a constant matches the constraint */
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172 | c896fe29 | bellard | static inline int tcg_target_const_match(tcg_target_long val, |
173 | c896fe29 | bellard | const TCGArgConstraint *arg_ct)
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174 | c896fe29 | bellard | { |
175 | c896fe29 | bellard | int ct;
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176 | c896fe29 | bellard | ct = arg_ct->ct; |
177 | c896fe29 | bellard | if (ct & TCG_CT_CONST)
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178 | c896fe29 | bellard | return 1; |
179 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
180 | c896fe29 | bellard | return 1; |
181 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
182 | c896fe29 | bellard | return 1; |
183 | c896fe29 | bellard | else
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184 | c896fe29 | bellard | return 0; |
185 | c896fe29 | bellard | } |
186 | c896fe29 | bellard | |
187 | c896fe29 | bellard | #define ARITH_ADD 0 |
188 | c896fe29 | bellard | #define ARITH_OR 1 |
189 | c896fe29 | bellard | #define ARITH_ADC 2 |
190 | c896fe29 | bellard | #define ARITH_SBB 3 |
191 | c896fe29 | bellard | #define ARITH_AND 4 |
192 | c896fe29 | bellard | #define ARITH_SUB 5 |
193 | c896fe29 | bellard | #define ARITH_XOR 6 |
194 | c896fe29 | bellard | #define ARITH_CMP 7 |
195 | c896fe29 | bellard | |
196 | d42f183c | aurel32 | #define SHIFT_ROL 0 |
197 | d42f183c | aurel32 | #define SHIFT_ROR 1 |
198 | c896fe29 | bellard | #define SHIFT_SHL 4 |
199 | c896fe29 | bellard | #define SHIFT_SHR 5 |
200 | c896fe29 | bellard | #define SHIFT_SAR 7 |
201 | c896fe29 | bellard | |
202 | c896fe29 | bellard | #define JCC_JMP (-1) |
203 | c896fe29 | bellard | #define JCC_JO 0x0 |
204 | c896fe29 | bellard | #define JCC_JNO 0x1 |
205 | c896fe29 | bellard | #define JCC_JB 0x2 |
206 | c896fe29 | bellard | #define JCC_JAE 0x3 |
207 | c896fe29 | bellard | #define JCC_JE 0x4 |
208 | c896fe29 | bellard | #define JCC_JNE 0x5 |
209 | c896fe29 | bellard | #define JCC_JBE 0x6 |
210 | c896fe29 | bellard | #define JCC_JA 0x7 |
211 | c896fe29 | bellard | #define JCC_JS 0x8 |
212 | c896fe29 | bellard | #define JCC_JNS 0x9 |
213 | c896fe29 | bellard | #define JCC_JP 0xa |
214 | c896fe29 | bellard | #define JCC_JNP 0xb |
215 | c896fe29 | bellard | #define JCC_JL 0xc |
216 | c896fe29 | bellard | #define JCC_JGE 0xd |
217 | c896fe29 | bellard | #define JCC_JLE 0xe |
218 | c896fe29 | bellard | #define JCC_JG 0xf |
219 | c896fe29 | bellard | |
220 | c896fe29 | bellard | #define P_EXT 0x100 /* 0x0f opcode prefix */ |
221 | c896fe29 | bellard | #define P_REXW 0x200 /* set rex.w = 1 */ |
222 | 3c3a1d20 | bellard | #define P_REXB 0x400 /* force rex use for byte registers */ |
223 | c896fe29 | bellard | |
224 | c896fe29 | bellard | static const uint8_t tcg_cond_to_jcc[10] = { |
225 | c896fe29 | bellard | [TCG_COND_EQ] = JCC_JE, |
226 | c896fe29 | bellard | [TCG_COND_NE] = JCC_JNE, |
227 | c896fe29 | bellard | [TCG_COND_LT] = JCC_JL, |
228 | c896fe29 | bellard | [TCG_COND_GE] = JCC_JGE, |
229 | c896fe29 | bellard | [TCG_COND_LE] = JCC_JLE, |
230 | c896fe29 | bellard | [TCG_COND_GT] = JCC_JG, |
231 | c896fe29 | bellard | [TCG_COND_LTU] = JCC_JB, |
232 | c896fe29 | bellard | [TCG_COND_GEU] = JCC_JAE, |
233 | c896fe29 | bellard | [TCG_COND_LEU] = JCC_JBE, |
234 | c896fe29 | bellard | [TCG_COND_GTU] = JCC_JA, |
235 | c896fe29 | bellard | }; |
236 | c896fe29 | bellard | |
237 | c896fe29 | bellard | static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
238 | c896fe29 | bellard | { |
239 | c896fe29 | bellard | int rex;
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240 | c896fe29 | bellard | rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) | |
241 | c896fe29 | bellard | ((x >> 2) & 2) | ((rm >> 3) & 1); |
242 | 33759846 | bellard | if (rex || (opc & P_REXB)) {
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243 | c896fe29 | bellard | tcg_out8(s, rex | 0x40);
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244 | c896fe29 | bellard | } |
245 | c896fe29 | bellard | if (opc & P_EXT)
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246 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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247 | 9e622b15 | blueswir1 | tcg_out8(s, opc & 0xff);
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248 | c896fe29 | bellard | } |
249 | c896fe29 | bellard | |
250 | c896fe29 | bellard | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
251 | c896fe29 | bellard | { |
252 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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253 | c896fe29 | bellard | tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
254 | c896fe29 | bellard | } |
255 | c896fe29 | bellard | |
256 | c896fe29 | bellard | /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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257 | c896fe29 | bellard | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
258 | c896fe29 | bellard | tcg_target_long offset) |
259 | c896fe29 | bellard | { |
260 | c896fe29 | bellard | if (rm < 0) { |
261 | c896fe29 | bellard | tcg_target_long val; |
262 | c896fe29 | bellard | tcg_out_opc(s, opc, r, 0, 0); |
263 | c896fe29 | bellard | val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
264 | c896fe29 | bellard | if (val == (int32_t)val) {
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265 | c896fe29 | bellard | /* eip relative */
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266 | c896fe29 | bellard | tcg_out8(s, 0x05 | ((r & 7) << 3)); |
267 | c896fe29 | bellard | tcg_out32(s, val); |
268 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
269 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
270 | c896fe29 | bellard | tcg_out8(s, 0x25); /* sib */ |
271 | c896fe29 | bellard | tcg_out32(s, offset); |
272 | c896fe29 | bellard | } else {
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273 | c896fe29 | bellard | tcg_abort(); |
274 | c896fe29 | bellard | } |
275 | c896fe29 | bellard | } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
276 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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277 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
278 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
279 | c896fe29 | bellard | tcg_out8(s, 0x24);
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280 | c896fe29 | bellard | } else {
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281 | c896fe29 | bellard | tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
282 | c896fe29 | bellard | } |
283 | c896fe29 | bellard | } else if ((int8_t)offset == offset) { |
284 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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285 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
286 | c896fe29 | bellard | tcg_out8(s, 0x44 | ((r & 7) << 3)); |
287 | c896fe29 | bellard | tcg_out8(s, 0x24);
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288 | c896fe29 | bellard | } else {
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289 | c896fe29 | bellard | tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
290 | c896fe29 | bellard | } |
291 | c896fe29 | bellard | tcg_out8(s, offset); |
292 | c896fe29 | bellard | } else {
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293 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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294 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
295 | c896fe29 | bellard | tcg_out8(s, 0x84 | ((r & 7) << 3)); |
296 | c896fe29 | bellard | tcg_out8(s, 0x24);
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297 | c896fe29 | bellard | } else {
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298 | c896fe29 | bellard | tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
299 | c896fe29 | bellard | } |
300 | c896fe29 | bellard | tcg_out32(s, offset); |
301 | c896fe29 | bellard | } |
302 | c896fe29 | bellard | } |
303 | c896fe29 | bellard | |
304 | bffd92fe | blueswir1 | #if defined(CONFIG_SOFTMMU)
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305 | c896fe29 | bellard | /* XXX: incomplete. index must be different from ESP */
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306 | c896fe29 | bellard | static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
307 | c896fe29 | bellard | int index, int shift, |
308 | c896fe29 | bellard | tcg_target_long offset) |
309 | c896fe29 | bellard | { |
310 | c896fe29 | bellard | int mod;
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311 | c896fe29 | bellard | if (rm == -1) |
312 | c896fe29 | bellard | tcg_abort(); |
313 | c896fe29 | bellard | if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
314 | c896fe29 | bellard | mod = 0;
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315 | c896fe29 | bellard | } else if (offset == (int8_t)offset) { |
316 | c896fe29 | bellard | mod = 0x40;
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317 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
318 | c896fe29 | bellard | mod = 0x80;
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319 | c896fe29 | bellard | } else {
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320 | c896fe29 | bellard | tcg_abort(); |
321 | c896fe29 | bellard | } |
322 | c896fe29 | bellard | if (index == -1) { |
323 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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324 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
325 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
326 | c896fe29 | bellard | tcg_out8(s, 0x04 | (rm & 7)); |
327 | c896fe29 | bellard | } else {
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328 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
329 | c896fe29 | bellard | } |
330 | c896fe29 | bellard | } else {
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331 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, index); |
332 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
333 | c896fe29 | bellard | tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
334 | c896fe29 | bellard | } |
335 | c896fe29 | bellard | if (mod == 0x40) { |
336 | c896fe29 | bellard | tcg_out8(s, offset); |
337 | c896fe29 | bellard | } else if (mod == 0x80) { |
338 | c896fe29 | bellard | tcg_out32(s, offset); |
339 | c896fe29 | bellard | } |
340 | c896fe29 | bellard | } |
341 | bffd92fe | blueswir1 | #endif
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342 | c896fe29 | bellard | |
343 | c896fe29 | bellard | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
344 | c896fe29 | bellard | { |
345 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
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346 | c896fe29 | bellard | } |
347 | c896fe29 | bellard | |
348 | c896fe29 | bellard | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
349 | c896fe29 | bellard | int ret, tcg_target_long arg)
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350 | c896fe29 | bellard | { |
351 | c896fe29 | bellard | if (arg == 0) { |
352 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
353 | c896fe29 | bellard | } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
354 | c896fe29 | bellard | tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
355 | c896fe29 | bellard | tcg_out32(s, arg); |
356 | c896fe29 | bellard | } else if (arg == (int32_t)arg) { |
357 | c896fe29 | bellard | tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
358 | c896fe29 | bellard | tcg_out32(s, arg); |
359 | c896fe29 | bellard | } else {
|
360 | c896fe29 | bellard | tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
361 | c896fe29 | bellard | tcg_out32(s, arg); |
362 | c896fe29 | bellard | tcg_out32(s, arg >> 32);
|
363 | c896fe29 | bellard | } |
364 | c896fe29 | bellard | } |
365 | c896fe29 | bellard | |
366 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
367 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
368 | c896fe29 | bellard | { |
369 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
370 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
371 | e4d5434c | blueswir1 | else
|
372 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
373 | c896fe29 | bellard | } |
374 | c896fe29 | bellard | |
375 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
376 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
377 | c896fe29 | bellard | { |
378 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
379 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
380 | e4d5434c | blueswir1 | else
|
381 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
382 | c896fe29 | bellard | } |
383 | c896fe29 | bellard | |
384 | c896fe29 | bellard | static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
385 | c896fe29 | bellard | { |
386 | c896fe29 | bellard | if (val == (int8_t)val) {
|
387 | c896fe29 | bellard | tcg_out_modrm(s, 0x83, c, r0);
|
388 | c896fe29 | bellard | tcg_out8(s, val); |
389 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffu) { |
390 | 733fef0e | pbrook | /* movzbl */
|
391 | 733fef0e | pbrook | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
|
392 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffffu) { |
393 | 733fef0e | pbrook | /* movzwl */
|
394 | 733fef0e | pbrook | tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
|
395 | c896fe29 | bellard | } else {
|
396 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
|
397 | c896fe29 | bellard | tcg_out32(s, val); |
398 | c896fe29 | bellard | } |
399 | c896fe29 | bellard | } |
400 | c896fe29 | bellard | |
401 | c896fe29 | bellard | static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
402 | c896fe29 | bellard | { |
403 | c896fe29 | bellard | if (val == (int8_t)val) {
|
404 | c896fe29 | bellard | tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
|
405 | c896fe29 | bellard | tcg_out8(s, val); |
406 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffu) { |
407 | 733fef0e | pbrook | /* movzbl */
|
408 | 733fef0e | pbrook | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
|
409 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffffu) { |
410 | 733fef0e | pbrook | /* movzwl */
|
411 | 733fef0e | pbrook | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
|
412 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffffffffu) { |
413 | 733fef0e | pbrook | /* 32-bit mov zero extends */
|
414 | 733fef0e | pbrook | tcg_out_modrm(s, 0x8b, r0, r0);
|
415 | c896fe29 | bellard | } else if (val == (int32_t)val) { |
416 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
417 | c896fe29 | bellard | tcg_out32(s, val); |
418 | c896fe29 | bellard | } else if (c == ARITH_AND && val == (uint32_t)val) { |
419 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
|
420 | c896fe29 | bellard | tcg_out32(s, val); |
421 | c896fe29 | bellard | } else {
|
422 | c896fe29 | bellard | tcg_abort(); |
423 | c896fe29 | bellard | } |
424 | c896fe29 | bellard | } |
425 | c896fe29 | bellard | |
426 | 8fcd3692 | blueswir1 | static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
427 | c896fe29 | bellard | { |
428 | c896fe29 | bellard | if (val != 0) |
429 | c896fe29 | bellard | tgen_arithi64(s, ARITH_ADD, reg, val); |
430 | c896fe29 | bellard | } |
431 | c896fe29 | bellard | |
432 | c896fe29 | bellard | static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
433 | c896fe29 | bellard | { |
434 | c896fe29 | bellard | int32_t val, val1; |
435 | c896fe29 | bellard | TCGLabel *l = &s->labels[label_index]; |
436 | c896fe29 | bellard | |
437 | c896fe29 | bellard | if (l->has_value) {
|
438 | c896fe29 | bellard | val = l->u.value - (tcg_target_long)s->code_ptr; |
439 | c896fe29 | bellard | val1 = val - 2;
|
440 | c896fe29 | bellard | if ((int8_t)val1 == val1) {
|
441 | c896fe29 | bellard | if (opc == -1) |
442 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
443 | c896fe29 | bellard | else
|
444 | c896fe29 | bellard | tcg_out8(s, 0x70 + opc);
|
445 | c896fe29 | bellard | tcg_out8(s, val1); |
446 | c896fe29 | bellard | } else {
|
447 | c896fe29 | bellard | if (opc == -1) { |
448 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
449 | c896fe29 | bellard | tcg_out32(s, val - 5);
|
450 | c896fe29 | bellard | } else {
|
451 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
452 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
453 | c896fe29 | bellard | tcg_out32(s, val - 6);
|
454 | c896fe29 | bellard | } |
455 | c896fe29 | bellard | } |
456 | c896fe29 | bellard | } else {
|
457 | c896fe29 | bellard | if (opc == -1) { |
458 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
459 | c896fe29 | bellard | } else {
|
460 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
461 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
462 | c896fe29 | bellard | } |
463 | c896fe29 | bellard | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
464 | 623e265c | pbrook | s->code_ptr += 4;
|
465 | c896fe29 | bellard | } |
466 | c896fe29 | bellard | } |
467 | c896fe29 | bellard | |
468 | c896fe29 | bellard | static void tcg_out_brcond(TCGContext *s, int cond, |
469 | c896fe29 | bellard | TCGArg arg1, TCGArg arg2, int const_arg2,
|
470 | c896fe29 | bellard | int label_index, int rexw) |
471 | c896fe29 | bellard | { |
472 | c896fe29 | bellard | if (const_arg2) {
|
473 | c896fe29 | bellard | if (arg2 == 0) { |
474 | c896fe29 | bellard | /* test r, r */
|
475 | c896fe29 | bellard | tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
476 | c896fe29 | bellard | } else {
|
477 | c896fe29 | bellard | if (rexw)
|
478 | c896fe29 | bellard | tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
479 | c896fe29 | bellard | else
|
480 | c896fe29 | bellard | tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
481 | c896fe29 | bellard | } |
482 | c896fe29 | bellard | } else {
|
483 | bb210e78 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
484 | c896fe29 | bellard | } |
485 | 560f92cc | bellard | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
486 | c896fe29 | bellard | } |
487 | c896fe29 | bellard | |
488 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
489 | c896fe29 | bellard | |
490 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
491 | c896fe29 | bellard | |
492 | c896fe29 | bellard | static void *qemu_ld_helpers[4] = { |
493 | c896fe29 | bellard | __ldb_mmu, |
494 | c896fe29 | bellard | __ldw_mmu, |
495 | c896fe29 | bellard | __ldl_mmu, |
496 | c896fe29 | bellard | __ldq_mmu, |
497 | c896fe29 | bellard | }; |
498 | c896fe29 | bellard | |
499 | c896fe29 | bellard | static void *qemu_st_helpers[4] = { |
500 | c896fe29 | bellard | __stb_mmu, |
501 | c896fe29 | bellard | __stw_mmu, |
502 | c896fe29 | bellard | __stl_mmu, |
503 | c896fe29 | bellard | __stq_mmu, |
504 | c896fe29 | bellard | }; |
505 | c896fe29 | bellard | #endif
|
506 | c896fe29 | bellard | |
507 | c896fe29 | bellard | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
508 | c896fe29 | bellard | int opc)
|
509 | c896fe29 | bellard | { |
510 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
511 | 379f6698 | Paul Brook | int32_t offset; |
512 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
513 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
514 | c896fe29 | bellard | #endif
|
515 | c896fe29 | bellard | |
516 | c896fe29 | bellard | data_reg = *args++; |
517 | c896fe29 | bellard | addr_reg = *args++; |
518 | c896fe29 | bellard | mem_index = *args; |
519 | c896fe29 | bellard | s_bits = opc & 3;
|
520 | c896fe29 | bellard | |
521 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
522 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
523 | c896fe29 | bellard | |
524 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
525 | c896fe29 | bellard | rexw = 0;
|
526 | c896fe29 | bellard | #else
|
527 | c896fe29 | bellard | rexw = P_REXW; |
528 | c896fe29 | bellard | #endif
|
529 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
530 | c896fe29 | bellard | /* mov */
|
531 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
532 | c896fe29 | bellard | |
533 | c896fe29 | bellard | /* mov */
|
534 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
535 | c896fe29 | bellard | |
536 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
537 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
538 | c896fe29 | bellard | |
539 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
540 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
541 | c896fe29 | bellard | |
542 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
543 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
544 | c896fe29 | bellard | |
545 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
546 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
547 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
548 | c896fe29 | bellard | |
549 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
550 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
551 | c896fe29 | bellard | |
552 | c896fe29 | bellard | /* mov */
|
553 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
554 | c896fe29 | bellard | |
555 | c896fe29 | bellard | /* je label1 */
|
556 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
557 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
558 | c896fe29 | bellard | s->code_ptr++; |
559 | c896fe29 | bellard | |
560 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
561 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
562 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
563 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - |
564 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
565 | c896fe29 | bellard | |
566 | c896fe29 | bellard | switch(opc) {
|
567 | c896fe29 | bellard | case 0 | 4: |
568 | c896fe29 | bellard | /* movsbq */
|
569 | c896fe29 | bellard | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
570 | c896fe29 | bellard | break;
|
571 | c896fe29 | bellard | case 1 | 4: |
572 | c896fe29 | bellard | /* movswq */
|
573 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
574 | c896fe29 | bellard | break;
|
575 | c896fe29 | bellard | case 2 | 4: |
576 | c896fe29 | bellard | /* movslq */
|
577 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
578 | c896fe29 | bellard | break;
|
579 | c896fe29 | bellard | case 0: |
580 | 9db3ba4d | aurel32 | /* movzbq */
|
581 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
582 | 9db3ba4d | aurel32 | break;
|
583 | c896fe29 | bellard | case 1: |
584 | 9db3ba4d | aurel32 | /* movzwq */
|
585 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
586 | 9db3ba4d | aurel32 | break;
|
587 | c896fe29 | bellard | case 2: |
588 | c896fe29 | bellard | default:
|
589 | c896fe29 | bellard | /* movl */
|
590 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
|
591 | c896fe29 | bellard | break;
|
592 | c896fe29 | bellard | case 3: |
593 | c896fe29 | bellard | tcg_out_mov(s, data_reg, TCG_REG_RAX); |
594 | c896fe29 | bellard | break;
|
595 | c896fe29 | bellard | } |
596 | c896fe29 | bellard | |
597 | c896fe29 | bellard | /* jmp label2 */
|
598 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
599 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
600 | c896fe29 | bellard | s->code_ptr++; |
601 | c896fe29 | bellard | |
602 | c896fe29 | bellard | /* label1: */
|
603 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
604 | c896fe29 | bellard | |
605 | c896fe29 | bellard | /* add x(r1), r0 */
|
606 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
607 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_read)); |
608 | 379f6698 | Paul Brook | offset = 0;
|
609 | c896fe29 | bellard | #else
|
610 | 379f6698 | Paul Brook | if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
611 | 379f6698 | Paul Brook | r0 = addr_reg; |
612 | 379f6698 | Paul Brook | offset = GUEST_BASE; |
613 | 379f6698 | Paul Brook | } else {
|
614 | 379f6698 | Paul Brook | offset = 0;
|
615 | 379f6698 | Paul Brook | /* movq $GUEST_BASE, r0 */
|
616 | 379f6698 | Paul Brook | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
617 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE); |
618 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE >> 32);
|
619 | 379f6698 | Paul Brook | /* addq addr_reg, r0 */
|
620 | 379f6698 | Paul Brook | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
621 | 379f6698 | Paul Brook | } |
622 | c896fe29 | bellard | #endif
|
623 | c896fe29 | bellard | |
624 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
625 | c896fe29 | bellard | bswap = 1;
|
626 | c896fe29 | bellard | #else
|
627 | c896fe29 | bellard | bswap = 0;
|
628 | c896fe29 | bellard | #endif
|
629 | c896fe29 | bellard | switch(opc) {
|
630 | c896fe29 | bellard | case 0: |
631 | c896fe29 | bellard | /* movzbl */
|
632 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
|
633 | c896fe29 | bellard | break;
|
634 | c896fe29 | bellard | case 0 | 4: |
635 | c896fe29 | bellard | /* movsbX */
|
636 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
|
637 | c896fe29 | bellard | break;
|
638 | c896fe29 | bellard | case 1: |
639 | c896fe29 | bellard | /* movzwl */
|
640 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
641 | c896fe29 | bellard | if (bswap) {
|
642 | c896fe29 | bellard | /* rolw $8, data_reg */
|
643 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
644 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
645 | c896fe29 | bellard | tcg_out8(s, 8);
|
646 | c896fe29 | bellard | } |
647 | c896fe29 | bellard | break;
|
648 | c896fe29 | bellard | case 1 | 4: |
649 | c896fe29 | bellard | if (bswap) {
|
650 | c896fe29 | bellard | /* movzwl */
|
651 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
652 | c896fe29 | bellard | /* rolw $8, data_reg */
|
653 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
654 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
655 | c896fe29 | bellard | tcg_out8(s, 8);
|
656 | c896fe29 | bellard | |
657 | c896fe29 | bellard | /* movswX data_reg, data_reg */
|
658 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
659 | c896fe29 | bellard | } else {
|
660 | c896fe29 | bellard | /* movswX */
|
661 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
|
662 | c896fe29 | bellard | } |
663 | c896fe29 | bellard | break;
|
664 | c896fe29 | bellard | case 2: |
665 | c896fe29 | bellard | /* movl (r0), data_reg */
|
666 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
667 | c896fe29 | bellard | if (bswap) {
|
668 | c896fe29 | bellard | /* bswap */
|
669 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
670 | c896fe29 | bellard | } |
671 | c896fe29 | bellard | break;
|
672 | c896fe29 | bellard | case 2 | 4: |
673 | c896fe29 | bellard | if (bswap) {
|
674 | c896fe29 | bellard | /* movl (r0), data_reg */
|
675 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
676 | c896fe29 | bellard | /* bswap */
|
677 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
678 | c896fe29 | bellard | /* movslq */
|
679 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
680 | c896fe29 | bellard | } else {
|
681 | c896fe29 | bellard | /* movslq */
|
682 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
|
683 | c896fe29 | bellard | } |
684 | c896fe29 | bellard | break;
|
685 | c896fe29 | bellard | case 3: |
686 | c896fe29 | bellard | /* movq (r0), data_reg */
|
687 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
|
688 | c896fe29 | bellard | if (bswap) {
|
689 | c896fe29 | bellard | /* bswap */
|
690 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
691 | c896fe29 | bellard | } |
692 | c896fe29 | bellard | break;
|
693 | c896fe29 | bellard | default:
|
694 | c896fe29 | bellard | tcg_abort(); |
695 | c896fe29 | bellard | } |
696 | c896fe29 | bellard | |
697 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
698 | c896fe29 | bellard | /* label2: */
|
699 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
700 | c896fe29 | bellard | #endif
|
701 | c896fe29 | bellard | } |
702 | c896fe29 | bellard | |
703 | c896fe29 | bellard | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
704 | c896fe29 | bellard | int opc)
|
705 | c896fe29 | bellard | { |
706 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
707 | 379f6698 | Paul Brook | int32_t offset; |
708 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
709 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
710 | c896fe29 | bellard | #endif
|
711 | c896fe29 | bellard | |
712 | c896fe29 | bellard | data_reg = *args++; |
713 | c896fe29 | bellard | addr_reg = *args++; |
714 | c896fe29 | bellard | mem_index = *args; |
715 | c896fe29 | bellard | |
716 | c896fe29 | bellard | s_bits = opc; |
717 | c896fe29 | bellard | |
718 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
719 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
720 | c896fe29 | bellard | |
721 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
722 | c896fe29 | bellard | rexw = 0;
|
723 | c896fe29 | bellard | #else
|
724 | c896fe29 | bellard | rexw = P_REXW; |
725 | c896fe29 | bellard | #endif
|
726 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
727 | c896fe29 | bellard | /* mov */
|
728 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
729 | c896fe29 | bellard | |
730 | c896fe29 | bellard | /* mov */
|
731 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
732 | c896fe29 | bellard | |
733 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
734 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
735 | c896fe29 | bellard | |
736 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
737 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
738 | c896fe29 | bellard | |
739 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
740 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
741 | c896fe29 | bellard | |
742 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
743 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
744 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
745 | c896fe29 | bellard | |
746 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
747 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
748 | c896fe29 | bellard | |
749 | c896fe29 | bellard | /* mov */
|
750 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
751 | c896fe29 | bellard | |
752 | c896fe29 | bellard | /* je label1 */
|
753 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
754 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
755 | c896fe29 | bellard | s->code_ptr++; |
756 | c896fe29 | bellard | |
757 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
758 | c896fe29 | bellard | switch(opc) {
|
759 | c896fe29 | bellard | case 0: |
760 | c896fe29 | bellard | /* movzbl */
|
761 | 3c3a1d20 | bellard | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
|
762 | c896fe29 | bellard | break;
|
763 | c896fe29 | bellard | case 1: |
764 | c896fe29 | bellard | /* movzwl */
|
765 | c896fe29 | bellard | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
766 | c896fe29 | bellard | break;
|
767 | c896fe29 | bellard | case 2: |
768 | c896fe29 | bellard | /* movl */
|
769 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
|
770 | c896fe29 | bellard | break;
|
771 | c896fe29 | bellard | default:
|
772 | c896fe29 | bellard | case 3: |
773 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_RSI, data_reg); |
774 | c896fe29 | bellard | break;
|
775 | c896fe29 | bellard | } |
776 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
777 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
778 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
779 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
780 | c896fe29 | bellard | |
781 | c896fe29 | bellard | /* jmp label2 */
|
782 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
783 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
784 | c896fe29 | bellard | s->code_ptr++; |
785 | c896fe29 | bellard | |
786 | c896fe29 | bellard | /* label1: */
|
787 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
788 | c896fe29 | bellard | |
789 | c896fe29 | bellard | /* add x(r1), r0 */
|
790 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
791 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_write)); |
792 | 379f6698 | Paul Brook | offset = 0;
|
793 | c896fe29 | bellard | #else
|
794 | 379f6698 | Paul Brook | if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
795 | 379f6698 | Paul Brook | r0 = addr_reg; |
796 | 379f6698 | Paul Brook | offset = GUEST_BASE; |
797 | 379f6698 | Paul Brook | } else {
|
798 | 379f6698 | Paul Brook | offset = 0;
|
799 | 379f6698 | Paul Brook | /* movq $GUEST_BASE, r0 */
|
800 | 379f6698 | Paul Brook | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
801 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE); |
802 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE >> 32);
|
803 | 379f6698 | Paul Brook | /* addq addr_reg, r0 */
|
804 | 379f6698 | Paul Brook | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
805 | 379f6698 | Paul Brook | } |
806 | c896fe29 | bellard | #endif
|
807 | c896fe29 | bellard | |
808 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
809 | c896fe29 | bellard | bswap = 1;
|
810 | c896fe29 | bellard | #else
|
811 | c896fe29 | bellard | bswap = 0;
|
812 | c896fe29 | bellard | #endif
|
813 | c896fe29 | bellard | switch(opc) {
|
814 | c896fe29 | bellard | case 0: |
815 | c896fe29 | bellard | /* movb */
|
816 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset);
|
817 | c896fe29 | bellard | break;
|
818 | c896fe29 | bellard | case 1: |
819 | c896fe29 | bellard | if (bswap) {
|
820 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
821 | c896fe29 | bellard | tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
822 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, r1); |
823 | c896fe29 | bellard | tcg_out8(s, 8);
|
824 | c896fe29 | bellard | data_reg = r1; |
825 | c896fe29 | bellard | } |
826 | c896fe29 | bellard | /* movw */
|
827 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
828 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
829 | c896fe29 | bellard | break;
|
830 | c896fe29 | bellard | case 2: |
831 | c896fe29 | bellard | if (bswap) {
|
832 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
833 | c896fe29 | bellard | /* bswap data_reg */
|
834 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
835 | c896fe29 | bellard | data_reg = r1; |
836 | c896fe29 | bellard | } |
837 | c896fe29 | bellard | /* movl */
|
838 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
839 | c896fe29 | bellard | break;
|
840 | c896fe29 | bellard | case 3: |
841 | c896fe29 | bellard | if (bswap) {
|
842 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
843 | c896fe29 | bellard | /* bswap data_reg */
|
844 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
845 | c896fe29 | bellard | data_reg = r1; |
846 | c896fe29 | bellard | } |
847 | c896fe29 | bellard | /* movq */
|
848 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
|
849 | c896fe29 | bellard | break;
|
850 | c896fe29 | bellard | default:
|
851 | c896fe29 | bellard | tcg_abort(); |
852 | c896fe29 | bellard | } |
853 | c896fe29 | bellard | |
854 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
855 | c896fe29 | bellard | /* label2: */
|
856 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
857 | c896fe29 | bellard | #endif
|
858 | c896fe29 | bellard | } |
859 | c896fe29 | bellard | |
860 | c896fe29 | bellard | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
861 | c896fe29 | bellard | const int *const_args) |
862 | c896fe29 | bellard | { |
863 | c896fe29 | bellard | int c;
|
864 | c896fe29 | bellard | |
865 | c896fe29 | bellard | switch(opc) {
|
866 | c896fe29 | bellard | case INDEX_op_exit_tb:
|
867 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
868 | b03cce8e | bellard | tcg_out8(s, 0xe9); /* jmp tb_ret_addr */ |
869 | b03cce8e | bellard | tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
|
870 | c896fe29 | bellard | break;
|
871 | c896fe29 | bellard | case INDEX_op_goto_tb:
|
872 | c896fe29 | bellard | if (s->tb_jmp_offset) {
|
873 | c896fe29 | bellard | /* direct jump method */
|
874 | c896fe29 | bellard | tcg_out8(s, 0xe9); /* jmp im */ |
875 | c896fe29 | bellard | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
876 | c896fe29 | bellard | tcg_out32(s, 0);
|
877 | c896fe29 | bellard | } else {
|
878 | c896fe29 | bellard | /* indirect jump method */
|
879 | c896fe29 | bellard | /* jmp Ev */
|
880 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xff, 4, -1, |
881 | c896fe29 | bellard | (tcg_target_long)(s->tb_next + |
882 | c896fe29 | bellard | args[0]));
|
883 | c896fe29 | bellard | } |
884 | c896fe29 | bellard | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
885 | c896fe29 | bellard | break;
|
886 | c896fe29 | bellard | case INDEX_op_call:
|
887 | c896fe29 | bellard | if (const_args[0]) { |
888 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
889 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
890 | c896fe29 | bellard | } else {
|
891 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 2, args[0]); |
892 | c896fe29 | bellard | } |
893 | c896fe29 | bellard | break;
|
894 | c896fe29 | bellard | case INDEX_op_jmp:
|
895 | c896fe29 | bellard | if (const_args[0]) { |
896 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
897 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
898 | c896fe29 | bellard | } else {
|
899 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 4, args[0]); |
900 | c896fe29 | bellard | } |
901 | c896fe29 | bellard | break;
|
902 | c896fe29 | bellard | case INDEX_op_br:
|
903 | c896fe29 | bellard | tcg_out_jxx(s, JCC_JMP, args[0]);
|
904 | c896fe29 | bellard | break;
|
905 | c896fe29 | bellard | case INDEX_op_movi_i32:
|
906 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
907 | c896fe29 | bellard | break;
|
908 | c896fe29 | bellard | case INDEX_op_movi_i64:
|
909 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
910 | c896fe29 | bellard | break;
|
911 | c896fe29 | bellard | case INDEX_op_ld8u_i32:
|
912 | c896fe29 | bellard | case INDEX_op_ld8u_i64:
|
913 | c896fe29 | bellard | /* movzbl */
|
914 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
915 | c896fe29 | bellard | break;
|
916 | c896fe29 | bellard | case INDEX_op_ld8s_i32:
|
917 | c896fe29 | bellard | /* movsbl */
|
918 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
919 | c896fe29 | bellard | break;
|
920 | c896fe29 | bellard | case INDEX_op_ld8s_i64:
|
921 | c896fe29 | bellard | /* movsbq */
|
922 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
923 | c896fe29 | bellard | break;
|
924 | c896fe29 | bellard | case INDEX_op_ld16u_i32:
|
925 | c896fe29 | bellard | case INDEX_op_ld16u_i64:
|
926 | c896fe29 | bellard | /* movzwl */
|
927 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
928 | c896fe29 | bellard | break;
|
929 | c896fe29 | bellard | case INDEX_op_ld16s_i32:
|
930 | c896fe29 | bellard | /* movswl */
|
931 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
932 | c896fe29 | bellard | break;
|
933 | c896fe29 | bellard | case INDEX_op_ld16s_i64:
|
934 | c896fe29 | bellard | /* movswq */
|
935 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
936 | c896fe29 | bellard | break;
|
937 | c896fe29 | bellard | case INDEX_op_ld_i32:
|
938 | c896fe29 | bellard | case INDEX_op_ld32u_i64:
|
939 | c896fe29 | bellard | /* movl */
|
940 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
941 | c896fe29 | bellard | break;
|
942 | c896fe29 | bellard | case INDEX_op_ld32s_i64:
|
943 | c896fe29 | bellard | /* movslq */
|
944 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
945 | c896fe29 | bellard | break;
|
946 | c896fe29 | bellard | case INDEX_op_ld_i64:
|
947 | c896fe29 | bellard | /* movq */
|
948 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
949 | c896fe29 | bellard | break;
|
950 | c896fe29 | bellard | |
951 | c896fe29 | bellard | case INDEX_op_st8_i32:
|
952 | c896fe29 | bellard | case INDEX_op_st8_i64:
|
953 | c896fe29 | bellard | /* movb */
|
954 | 3c3a1d20 | bellard | tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]); |
955 | c896fe29 | bellard | break;
|
956 | c896fe29 | bellard | case INDEX_op_st16_i32:
|
957 | c896fe29 | bellard | case INDEX_op_st16_i64:
|
958 | c896fe29 | bellard | /* movw */
|
959 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
960 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
961 | c896fe29 | bellard | break;
|
962 | c896fe29 | bellard | case INDEX_op_st_i32:
|
963 | c896fe29 | bellard | case INDEX_op_st32_i64:
|
964 | c896fe29 | bellard | /* movl */
|
965 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
966 | c896fe29 | bellard | break;
|
967 | c896fe29 | bellard | case INDEX_op_st_i64:
|
968 | c896fe29 | bellard | /* movq */
|
969 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
970 | c896fe29 | bellard | break;
|
971 | c896fe29 | bellard | |
972 | c896fe29 | bellard | case INDEX_op_sub_i32:
|
973 | c896fe29 | bellard | c = ARITH_SUB; |
974 | c896fe29 | bellard | goto gen_arith32;
|
975 | c896fe29 | bellard | case INDEX_op_and_i32:
|
976 | c896fe29 | bellard | c = ARITH_AND; |
977 | c896fe29 | bellard | goto gen_arith32;
|
978 | c896fe29 | bellard | case INDEX_op_or_i32:
|
979 | c896fe29 | bellard | c = ARITH_OR; |
980 | c896fe29 | bellard | goto gen_arith32;
|
981 | c896fe29 | bellard | case INDEX_op_xor_i32:
|
982 | c896fe29 | bellard | c = ARITH_XOR; |
983 | c896fe29 | bellard | goto gen_arith32;
|
984 | c896fe29 | bellard | case INDEX_op_add_i32:
|
985 | c896fe29 | bellard | c = ARITH_ADD; |
986 | c896fe29 | bellard | gen_arith32:
|
987 | c896fe29 | bellard | if (const_args[2]) { |
988 | c896fe29 | bellard | tgen_arithi32(s, c, args[0], args[2]); |
989 | c896fe29 | bellard | } else {
|
990 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
991 | c896fe29 | bellard | } |
992 | c896fe29 | bellard | break;
|
993 | c896fe29 | bellard | |
994 | c896fe29 | bellard | case INDEX_op_sub_i64:
|
995 | c896fe29 | bellard | c = ARITH_SUB; |
996 | c896fe29 | bellard | goto gen_arith64;
|
997 | c896fe29 | bellard | case INDEX_op_and_i64:
|
998 | c896fe29 | bellard | c = ARITH_AND; |
999 | c896fe29 | bellard | goto gen_arith64;
|
1000 | c896fe29 | bellard | case INDEX_op_or_i64:
|
1001 | c896fe29 | bellard | c = ARITH_OR; |
1002 | c896fe29 | bellard | goto gen_arith64;
|
1003 | c896fe29 | bellard | case INDEX_op_xor_i64:
|
1004 | c896fe29 | bellard | c = ARITH_XOR; |
1005 | c896fe29 | bellard | goto gen_arith64;
|
1006 | c896fe29 | bellard | case INDEX_op_add_i64:
|
1007 | c896fe29 | bellard | c = ARITH_ADD; |
1008 | c896fe29 | bellard | gen_arith64:
|
1009 | c896fe29 | bellard | if (const_args[2]) { |
1010 | c896fe29 | bellard | tgen_arithi64(s, c, args[0], args[2]); |
1011 | c896fe29 | bellard | } else {
|
1012 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
1013 | c896fe29 | bellard | } |
1014 | c896fe29 | bellard | break;
|
1015 | c896fe29 | bellard | |
1016 | c896fe29 | bellard | case INDEX_op_mul_i32:
|
1017 | c896fe29 | bellard | if (const_args[2]) { |
1018 | c896fe29 | bellard | int32_t val; |
1019 | c896fe29 | bellard | val = args[2];
|
1020 | c896fe29 | bellard | if (val == (int8_t)val) {
|
1021 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b, args[0], args[0]); |
1022 | c896fe29 | bellard | tcg_out8(s, val); |
1023 | c896fe29 | bellard | } else {
|
1024 | c896fe29 | bellard | tcg_out_modrm(s, 0x69, args[0], args[0]); |
1025 | c896fe29 | bellard | tcg_out32(s, val); |
1026 | c896fe29 | bellard | } |
1027 | c896fe29 | bellard | } else {
|
1028 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
1029 | c896fe29 | bellard | } |
1030 | c896fe29 | bellard | break;
|
1031 | c896fe29 | bellard | case INDEX_op_mul_i64:
|
1032 | c896fe29 | bellard | if (const_args[2]) { |
1033 | c896fe29 | bellard | int32_t val; |
1034 | c896fe29 | bellard | val = args[2];
|
1035 | c896fe29 | bellard | if (val == (int8_t)val) {
|
1036 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
1037 | c896fe29 | bellard | tcg_out8(s, val); |
1038 | c896fe29 | bellard | } else {
|
1039 | c896fe29 | bellard | tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
1040 | c896fe29 | bellard | tcg_out32(s, val); |
1041 | c896fe29 | bellard | } |
1042 | c896fe29 | bellard | } else {
|
1043 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
1044 | c896fe29 | bellard | } |
1045 | c896fe29 | bellard | break;
|
1046 | c896fe29 | bellard | case INDEX_op_div2_i32:
|
1047 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 7, args[4]); |
1048 | c896fe29 | bellard | break;
|
1049 | c896fe29 | bellard | case INDEX_op_divu2_i32:
|
1050 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 6, args[4]); |
1051 | c896fe29 | bellard | break;
|
1052 | c896fe29 | bellard | case INDEX_op_div2_i64:
|
1053 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
1054 | c896fe29 | bellard | break;
|
1055 | c896fe29 | bellard | case INDEX_op_divu2_i64:
|
1056 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
1057 | c896fe29 | bellard | break;
|
1058 | c896fe29 | bellard | |
1059 | c896fe29 | bellard | case INDEX_op_shl_i32:
|
1060 | c896fe29 | bellard | c = SHIFT_SHL; |
1061 | c896fe29 | bellard | gen_shift32:
|
1062 | c896fe29 | bellard | if (const_args[2]) { |
1063 | c896fe29 | bellard | if (args[2] == 1) { |
1064 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1, c, args[0]); |
1065 | c896fe29 | bellard | } else {
|
1066 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, c, args[0]); |
1067 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1068 | c896fe29 | bellard | } |
1069 | c896fe29 | bellard | } else {
|
1070 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3, c, args[0]); |
1071 | c896fe29 | bellard | } |
1072 | c896fe29 | bellard | break;
|
1073 | c896fe29 | bellard | case INDEX_op_shr_i32:
|
1074 | c896fe29 | bellard | c = SHIFT_SHR; |
1075 | c896fe29 | bellard | goto gen_shift32;
|
1076 | c896fe29 | bellard | case INDEX_op_sar_i32:
|
1077 | c896fe29 | bellard | c = SHIFT_SAR; |
1078 | c896fe29 | bellard | goto gen_shift32;
|
1079 | d42f183c | aurel32 | case INDEX_op_rotl_i32:
|
1080 | d42f183c | aurel32 | c = SHIFT_ROL; |
1081 | d42f183c | aurel32 | goto gen_shift32;
|
1082 | d42f183c | aurel32 | case INDEX_op_rotr_i32:
|
1083 | d42f183c | aurel32 | c = SHIFT_ROR; |
1084 | d42f183c | aurel32 | goto gen_shift32;
|
1085 | d42f183c | aurel32 | |
1086 | c896fe29 | bellard | case INDEX_op_shl_i64:
|
1087 | c896fe29 | bellard | c = SHIFT_SHL; |
1088 | c896fe29 | bellard | gen_shift64:
|
1089 | c896fe29 | bellard | if (const_args[2]) { |
1090 | c896fe29 | bellard | if (args[2] == 1) { |
1091 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
1092 | c896fe29 | bellard | } else {
|
1093 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
1094 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1095 | c896fe29 | bellard | } |
1096 | c896fe29 | bellard | } else {
|
1097 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
1098 | c896fe29 | bellard | } |
1099 | c896fe29 | bellard | break;
|
1100 | c896fe29 | bellard | case INDEX_op_shr_i64:
|
1101 | c896fe29 | bellard | c = SHIFT_SHR; |
1102 | c896fe29 | bellard | goto gen_shift64;
|
1103 | c896fe29 | bellard | case INDEX_op_sar_i64:
|
1104 | c896fe29 | bellard | c = SHIFT_SAR; |
1105 | c896fe29 | bellard | goto gen_shift64;
|
1106 | d42f183c | aurel32 | case INDEX_op_rotl_i64:
|
1107 | d42f183c | aurel32 | c = SHIFT_ROL; |
1108 | d42f183c | aurel32 | goto gen_shift64;
|
1109 | d42f183c | aurel32 | case INDEX_op_rotr_i64:
|
1110 | d42f183c | aurel32 | c = SHIFT_ROR; |
1111 | d42f183c | aurel32 | goto gen_shift64;
|
1112 | d42f183c | aurel32 | |
1113 | c896fe29 | bellard | case INDEX_op_brcond_i32:
|
1114 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1115 | c896fe29 | bellard | args[3], 0); |
1116 | c896fe29 | bellard | break;
|
1117 | c896fe29 | bellard | case INDEX_op_brcond_i64:
|
1118 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1119 | c896fe29 | bellard | args[3], P_REXW);
|
1120 | c896fe29 | bellard | break;
|
1121 | c896fe29 | bellard | |
1122 | 86dbdd40 | aurel32 | case INDEX_op_bswap16_i32:
|
1123 | 86dbdd40 | aurel32 | case INDEX_op_bswap16_i64:
|
1124 | 86dbdd40 | aurel32 | tcg_out8(s, 0x66);
|
1125 | 86dbdd40 | aurel32 | tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1126 | 86dbdd40 | aurel32 | tcg_out8(s, 8);
|
1127 | 86dbdd40 | aurel32 | break;
|
1128 | 66896cb8 | aurel32 | case INDEX_op_bswap32_i32:
|
1129 | 86dbdd40 | aurel32 | case INDEX_op_bswap32_i64:
|
1130 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
1131 | c896fe29 | bellard | break;
|
1132 | 66896cb8 | aurel32 | case INDEX_op_bswap64_i64:
|
1133 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
1134 | c896fe29 | bellard | break;
|
1135 | c896fe29 | bellard | |
1136 | 390efc54 | pbrook | case INDEX_op_neg_i32:
|
1137 | 390efc54 | pbrook | tcg_out_modrm(s, 0xf7, 3, args[0]); |
1138 | 390efc54 | pbrook | break;
|
1139 | 390efc54 | pbrook | case INDEX_op_neg_i64:
|
1140 | 390efc54 | pbrook | tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]); |
1141 | 390efc54 | pbrook | break;
|
1142 | 390efc54 | pbrook | |
1143 | d2604285 | aurel32 | case INDEX_op_not_i32:
|
1144 | d2604285 | aurel32 | tcg_out_modrm(s, 0xf7, 2, args[0]); |
1145 | d2604285 | aurel32 | break;
|
1146 | d2604285 | aurel32 | case INDEX_op_not_i64:
|
1147 | d2604285 | aurel32 | tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]); |
1148 | d2604285 | aurel32 | break;
|
1149 | d2604285 | aurel32 | |
1150 | b6d17150 | pbrook | case INDEX_op_ext8s_i32:
|
1151 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]); |
1152 | b6d17150 | pbrook | break;
|
1153 | b6d17150 | pbrook | case INDEX_op_ext16s_i32:
|
1154 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1155 | b6d17150 | pbrook | break;
|
1156 | b6d17150 | pbrook | case INDEX_op_ext8s_i64:
|
1157 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]); |
1158 | b6d17150 | pbrook | break;
|
1159 | b6d17150 | pbrook | case INDEX_op_ext16s_i64:
|
1160 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]); |
1161 | b6d17150 | pbrook | break;
|
1162 | b6d17150 | pbrook | case INDEX_op_ext32s_i64:
|
1163 | b6d17150 | pbrook | tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]); |
1164 | b6d17150 | pbrook | break;
|
1165 | b6d17150 | pbrook | |
1166 | c896fe29 | bellard | case INDEX_op_qemu_ld8u:
|
1167 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0);
|
1168 | c896fe29 | bellard | break;
|
1169 | c896fe29 | bellard | case INDEX_op_qemu_ld8s:
|
1170 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0 | 4); |
1171 | c896fe29 | bellard | break;
|
1172 | c896fe29 | bellard | case INDEX_op_qemu_ld16u:
|
1173 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1);
|
1174 | c896fe29 | bellard | break;
|
1175 | c896fe29 | bellard | case INDEX_op_qemu_ld16s:
|
1176 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1 | 4); |
1177 | c896fe29 | bellard | break;
|
1178 | c896fe29 | bellard | case INDEX_op_qemu_ld32u:
|
1179 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2);
|
1180 | c896fe29 | bellard | break;
|
1181 | c896fe29 | bellard | case INDEX_op_qemu_ld32s:
|
1182 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2 | 4); |
1183 | c896fe29 | bellard | break;
|
1184 | c896fe29 | bellard | case INDEX_op_qemu_ld64:
|
1185 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 3);
|
1186 | c896fe29 | bellard | break;
|
1187 | c896fe29 | bellard | |
1188 | c896fe29 | bellard | case INDEX_op_qemu_st8:
|
1189 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 0);
|
1190 | c896fe29 | bellard | break;
|
1191 | c896fe29 | bellard | case INDEX_op_qemu_st16:
|
1192 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 1);
|
1193 | c896fe29 | bellard | break;
|
1194 | c896fe29 | bellard | case INDEX_op_qemu_st32:
|
1195 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 2);
|
1196 | c896fe29 | bellard | break;
|
1197 | c896fe29 | bellard | case INDEX_op_qemu_st64:
|
1198 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 3);
|
1199 | c896fe29 | bellard | break;
|
1200 | c896fe29 | bellard | |
1201 | c896fe29 | bellard | default:
|
1202 | c896fe29 | bellard | tcg_abort(); |
1203 | c896fe29 | bellard | } |
1204 | c896fe29 | bellard | } |
1205 | c896fe29 | bellard | |
1206 | b03cce8e | bellard | static int tcg_target_callee_save_regs[] = { |
1207 | b03cce8e | bellard | TCG_REG_RBP, |
1208 | b03cce8e | bellard | TCG_REG_RBX, |
1209 | b03cce8e | bellard | TCG_REG_R12, |
1210 | b03cce8e | bellard | TCG_REG_R13, |
1211 | b03cce8e | bellard | /* TCG_REG_R14, */ /* currently used for the global env, so no |
1212 | b03cce8e | bellard | need to save */
|
1213 | b03cce8e | bellard | TCG_REG_R15, |
1214 | b03cce8e | bellard | }; |
1215 | b03cce8e | bellard | |
1216 | b03cce8e | bellard | static inline void tcg_out_push(TCGContext *s, int reg) |
1217 | b03cce8e | bellard | { |
1218 | b03cce8e | bellard | tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0); |
1219 | b03cce8e | bellard | } |
1220 | b03cce8e | bellard | |
1221 | b03cce8e | bellard | static inline void tcg_out_pop(TCGContext *s, int reg) |
1222 | b03cce8e | bellard | { |
1223 | b03cce8e | bellard | tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0); |
1224 | b03cce8e | bellard | } |
1225 | b03cce8e | bellard | |
1226 | b03cce8e | bellard | /* Generate global QEMU prologue and epilogue code */
|
1227 | b03cce8e | bellard | void tcg_target_qemu_prologue(TCGContext *s)
|
1228 | b03cce8e | bellard | { |
1229 | b03cce8e | bellard | int i, frame_size, push_size, stack_addend;
|
1230 | b03cce8e | bellard | |
1231 | b03cce8e | bellard | /* TB prologue */
|
1232 | b03cce8e | bellard | /* save all callee saved registers */
|
1233 | b03cce8e | bellard | for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1234 | b03cce8e | bellard | tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1235 | b03cce8e | bellard | |
1236 | b03cce8e | bellard | } |
1237 | b03cce8e | bellard | /* reserve some stack space */
|
1238 | b03cce8e | bellard | push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8; |
1239 | b03cce8e | bellard | frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1240 | b03cce8e | bellard | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1241 | b03cce8e | bellard | ~(TCG_TARGET_STACK_ALIGN - 1);
|
1242 | b03cce8e | bellard | stack_addend = frame_size - push_size; |
1243 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_RSP, -stack_addend); |
1244 | b03cce8e | bellard | |
1245 | b03cce8e | bellard | tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */ |
1246 | b03cce8e | bellard | |
1247 | b03cce8e | bellard | /* TB epilogue */
|
1248 | b03cce8e | bellard | tb_ret_addr = s->code_ptr; |
1249 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_RSP, stack_addend); |
1250 | b03cce8e | bellard | for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1251 | b03cce8e | bellard | tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1252 | b03cce8e | bellard | } |
1253 | b03cce8e | bellard | tcg_out8(s, 0xc3); /* ret */ |
1254 | b03cce8e | bellard | } |
1255 | b03cce8e | bellard | |
1256 | c896fe29 | bellard | static const TCGTargetOpDef x86_64_op_defs[] = { |
1257 | c896fe29 | bellard | { INDEX_op_exit_tb, { } }, |
1258 | c896fe29 | bellard | { INDEX_op_goto_tb, { } }, |
1259 | c896fe29 | bellard | { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1260 | c896fe29 | bellard | { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1261 | c896fe29 | bellard | { INDEX_op_br, { } }, |
1262 | c896fe29 | bellard | |
1263 | c896fe29 | bellard | { INDEX_op_mov_i32, { "r", "r" } }, |
1264 | c896fe29 | bellard | { INDEX_op_movi_i32, { "r" } },
|
1265 | c896fe29 | bellard | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1266 | c896fe29 | bellard | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1267 | c896fe29 | bellard | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1268 | c896fe29 | bellard | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1269 | c896fe29 | bellard | { INDEX_op_ld_i32, { "r", "r" } }, |
1270 | c896fe29 | bellard | { INDEX_op_st8_i32, { "r", "r" } }, |
1271 | c896fe29 | bellard | { INDEX_op_st16_i32, { "r", "r" } }, |
1272 | c896fe29 | bellard | { INDEX_op_st_i32, { "r", "r" } }, |
1273 | c896fe29 | bellard | |
1274 | c896fe29 | bellard | { INDEX_op_add_i32, { "r", "0", "ri" } }, |
1275 | c896fe29 | bellard | { INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1276 | c896fe29 | bellard | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1277 | c896fe29 | bellard | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1278 | c896fe29 | bellard | { INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1279 | c896fe29 | bellard | { INDEX_op_and_i32, { "r", "0", "ri" } }, |
1280 | c896fe29 | bellard | { INDEX_op_or_i32, { "r", "0", "ri" } }, |
1281 | c896fe29 | bellard | { INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1282 | c896fe29 | bellard | |
1283 | c896fe29 | bellard | { INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1284 | c896fe29 | bellard | { INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1285 | c896fe29 | bellard | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1286 | d42f183c | aurel32 | { INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1287 | d42f183c | aurel32 | { INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1288 | c896fe29 | bellard | |
1289 | c896fe29 | bellard | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1290 | c896fe29 | bellard | |
1291 | c896fe29 | bellard | { INDEX_op_mov_i64, { "r", "r" } }, |
1292 | c896fe29 | bellard | { INDEX_op_movi_i64, { "r" } },
|
1293 | c896fe29 | bellard | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1294 | c896fe29 | bellard | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1295 | c896fe29 | bellard | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1296 | c896fe29 | bellard | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1297 | c896fe29 | bellard | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1298 | c896fe29 | bellard | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1299 | c896fe29 | bellard | { INDEX_op_ld_i64, { "r", "r" } }, |
1300 | c896fe29 | bellard | { INDEX_op_st8_i64, { "r", "r" } }, |
1301 | c896fe29 | bellard | { INDEX_op_st16_i64, { "r", "r" } }, |
1302 | c896fe29 | bellard | { INDEX_op_st32_i64, { "r", "r" } }, |
1303 | c896fe29 | bellard | { INDEX_op_st_i64, { "r", "r" } }, |
1304 | c896fe29 | bellard | |
1305 | c896fe29 | bellard | { INDEX_op_add_i64, { "r", "0", "re" } }, |
1306 | c896fe29 | bellard | { INDEX_op_mul_i64, { "r", "0", "re" } }, |
1307 | c896fe29 | bellard | { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
1308 | c896fe29 | bellard | { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
1309 | c896fe29 | bellard | { INDEX_op_sub_i64, { "r", "0", "re" } }, |
1310 | c896fe29 | bellard | { INDEX_op_and_i64, { "r", "0", "reZ" } }, |
1311 | c896fe29 | bellard | { INDEX_op_or_i64, { "r", "0", "re" } }, |
1312 | c896fe29 | bellard | { INDEX_op_xor_i64, { "r", "0", "re" } }, |
1313 | c896fe29 | bellard | |
1314 | c896fe29 | bellard | { INDEX_op_shl_i64, { "r", "0", "ci" } }, |
1315 | c896fe29 | bellard | { INDEX_op_shr_i64, { "r", "0", "ci" } }, |
1316 | c896fe29 | bellard | { INDEX_op_sar_i64, { "r", "0", "ci" } }, |
1317 | d42f183c | aurel32 | { INDEX_op_rotl_i64, { "r", "0", "ci" } }, |
1318 | d42f183c | aurel32 | { INDEX_op_rotr_i64, { "r", "0", "ci" } }, |
1319 | c896fe29 | bellard | |
1320 | c896fe29 | bellard | { INDEX_op_brcond_i64, { "r", "re" } }, |
1321 | c896fe29 | bellard | |
1322 | 86dbdd40 | aurel32 | { INDEX_op_bswap16_i32, { "r", "0" } }, |
1323 | 86dbdd40 | aurel32 | { INDEX_op_bswap16_i64, { "r", "0" } }, |
1324 | 66896cb8 | aurel32 | { INDEX_op_bswap32_i32, { "r", "0" } }, |
1325 | 86dbdd40 | aurel32 | { INDEX_op_bswap32_i64, { "r", "0" } }, |
1326 | 66896cb8 | aurel32 | { INDEX_op_bswap64_i64, { "r", "0" } }, |
1327 | c896fe29 | bellard | |
1328 | 390efc54 | pbrook | { INDEX_op_neg_i32, { "r", "0" } }, |
1329 | 390efc54 | pbrook | { INDEX_op_neg_i64, { "r", "0" } }, |
1330 | 390efc54 | pbrook | |
1331 | d2604285 | aurel32 | { INDEX_op_not_i32, { "r", "0" } }, |
1332 | d2604285 | aurel32 | { INDEX_op_not_i64, { "r", "0" } }, |
1333 | d2604285 | aurel32 | |
1334 | b6d17150 | pbrook | { INDEX_op_ext8s_i32, { "r", "r"} }, |
1335 | b6d17150 | pbrook | { INDEX_op_ext16s_i32, { "r", "r"} }, |
1336 | b6d17150 | pbrook | { INDEX_op_ext8s_i64, { "r", "r"} }, |
1337 | b6d17150 | pbrook | { INDEX_op_ext16s_i64, { "r", "r"} }, |
1338 | b6d17150 | pbrook | { INDEX_op_ext32s_i64, { "r", "r"} }, |
1339 | b6d17150 | pbrook | |
1340 | c896fe29 | bellard | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1341 | c896fe29 | bellard | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1342 | c896fe29 | bellard | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1343 | c896fe29 | bellard | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1344 | c896fe29 | bellard | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1345 | c896fe29 | bellard | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1346 | c896fe29 | bellard | { INDEX_op_qemu_ld64, { "r", "L" } }, |
1347 | c896fe29 | bellard | |
1348 | c896fe29 | bellard | { INDEX_op_qemu_st8, { "L", "L" } }, |
1349 | c896fe29 | bellard | { INDEX_op_qemu_st16, { "L", "L" } }, |
1350 | c896fe29 | bellard | { INDEX_op_qemu_st32, { "L", "L" } }, |
1351 | c896fe29 | bellard | { INDEX_op_qemu_st64, { "L", "L", "L" } }, |
1352 | c896fe29 | bellard | |
1353 | c896fe29 | bellard | { -1 },
|
1354 | c896fe29 | bellard | }; |
1355 | c896fe29 | bellard | |
1356 | c896fe29 | bellard | void tcg_target_init(TCGContext *s)
|
1357 | c896fe29 | bellard | { |
1358 | b03cce8e | bellard | /* fail safe */
|
1359 | b03cce8e | bellard | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1360 | b03cce8e | bellard | tcg_abort(); |
1361 | b03cce8e | bellard | |
1362 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
1363 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
1364 | c896fe29 | bellard | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1365 | c896fe29 | bellard | (1 << TCG_REG_RDI) |
|
1366 | c896fe29 | bellard | (1 << TCG_REG_RSI) |
|
1367 | c896fe29 | bellard | (1 << TCG_REG_RDX) |
|
1368 | c896fe29 | bellard | (1 << TCG_REG_RCX) |
|
1369 | c896fe29 | bellard | (1 << TCG_REG_R8) |
|
1370 | c896fe29 | bellard | (1 << TCG_REG_R9) |
|
1371 | c896fe29 | bellard | (1 << TCG_REG_RAX) |
|
1372 | c896fe29 | bellard | (1 << TCG_REG_R10) |
|
1373 | c896fe29 | bellard | (1 << TCG_REG_R11));
|
1374 | c896fe29 | bellard | |
1375 | c896fe29 | bellard | tcg_regset_clear(s->reserved_regs); |
1376 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
1377 | 3c3a1d20 | bellard | |
1378 | c896fe29 | bellard | tcg_add_target_add_op_defs(x86_64_op_defs); |
1379 | c896fe29 | bellard | } |