root / tcg / x86_64 / tcg-target.c @ f878d2d2
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"%rax",
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"%rcx",
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"%rdx",
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"%rbx",
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"%rsp",
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"%rbp",
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"%rsi",
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"%rdi",
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"%r8",
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"%r9",
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"%r10",
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"%r11",
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"%r12",
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"%r13",
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"%r14",
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"%r15",
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}; |
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#endif
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_RBP, |
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TCG_REG_RBX, |
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TCG_REG_R12, |
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TCG_REG_R13, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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TCG_REG_R10, |
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TCG_REG_R11, |
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TCG_REG_R9, |
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TCG_REG_R8, |
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TCG_REG_RCX, |
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TCG_REG_RDX, |
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TCG_REG_RSI, |
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TCG_REG_RDI, |
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TCG_REG_RAX, |
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}; |
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|
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static const int tcg_target_call_iarg_regs[6] = { |
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TCG_REG_RDI, |
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TCG_REG_RSI, |
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TCG_REG_RDX, |
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TCG_REG_RCX, |
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TCG_REG_R8, |
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TCG_REG_R9, |
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}; |
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|
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static const int tcg_target_call_oarg_regs[2] = { |
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TCG_REG_RAX, |
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TCG_REG_RDX |
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}; |
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static uint8_t *tb_ret_addr;
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|
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static void patch_reloc(uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{ |
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value += addend; |
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switch(type) {
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case R_X86_64_32:
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if (value != (uint32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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case R_X86_64_32S:
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if (value != (int32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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case R_386_PC32:
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value -= (long)code_ptr;
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if (value != (int32_t)value)
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tcg_abort(); |
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*(uint32_t *)code_ptr = value; |
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break;
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{ |
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return 6; |
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} |
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|
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{ |
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch(ct_str[0]) { |
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case 'a': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
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break;
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case 'b': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
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break;
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case 'c': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
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break;
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case 'd': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
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break;
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case 'S': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
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break;
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case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
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break;
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case 'q': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xf); |
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break;
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffff); |
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break;
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case 'L': /* qemu_ld/st constraint */ |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xffff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
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break;
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case 'e': |
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ct->ct |= TCG_CT_CONST_S32; |
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break;
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case 'Z': |
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ct->ct |= TCG_CT_CONST_U32; |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
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{ |
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int ct;
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
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return 1; |
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else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
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return 1; |
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else
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return 0; |
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} |
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#define ARITH_ADD 0 |
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#define ARITH_OR 1 |
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#define ARITH_ADC 2 |
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#define ARITH_SBB 3 |
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#define ARITH_AND 4 |
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#define ARITH_SUB 5 |
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#define ARITH_XOR 6 |
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#define ARITH_CMP 7 |
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#define SHIFT_ROL 0 |
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#define SHIFT_ROR 1 |
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#define SHIFT_SHL 4 |
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#define SHIFT_SHR 5 |
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#define SHIFT_SAR 7 |
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#define JCC_JMP (-1) |
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#define JCC_JO 0x0 |
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#define JCC_JNO 0x1 |
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#define JCC_JB 0x2 |
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#define JCC_JAE 0x3 |
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#define JCC_JE 0x4 |
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#define JCC_JNE 0x5 |
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#define JCC_JBE 0x6 |
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#define JCC_JA 0x7 |
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#define JCC_JS 0x8 |
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#define JCC_JNS 0x9 |
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#define JCC_JP 0xa |
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#define JCC_JNP 0xb |
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#define JCC_JL 0xc |
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#define JCC_JGE 0xd |
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#define JCC_JLE 0xe |
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#define JCC_JG 0xf |
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|
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#define P_EXT 0x100 /* 0x0f opcode prefix */ |
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#define P_REXW 0x200 /* set rex.w = 1 */ |
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#define P_REXB 0x400 /* force rex use for byte registers */ |
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static const uint8_t tcg_cond_to_jcc[10] = { |
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[TCG_COND_EQ] = JCC_JE, |
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[TCG_COND_NE] = JCC_JNE, |
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[TCG_COND_LT] = JCC_JL, |
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[TCG_COND_GE] = JCC_JGE, |
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[TCG_COND_LE] = JCC_JLE, |
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[TCG_COND_GT] = JCC_JG, |
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[TCG_COND_LTU] = JCC_JB, |
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[TCG_COND_GEU] = JCC_JAE, |
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[TCG_COND_LEU] = JCC_JBE, |
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[TCG_COND_GTU] = JCC_JA, |
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}; |
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static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
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{ |
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int rex;
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rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) | |
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((x >> 2) & 2) | ((rm >> 3) & 1); |
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if (rex || (opc & P_REXB)) {
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tcg_out8(s, rex | 0x40);
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} |
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if (opc & P_EXT)
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tcg_out8(s, 0x0f);
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tcg_out8(s, opc & 0xff);
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} |
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
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{ |
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tcg_out_opc(s, opc, r, rm, 0);
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tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
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} |
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/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
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tcg_target_long offset) |
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{ |
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if (rm < 0) { |
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tcg_target_long val; |
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tcg_out_opc(s, opc, r, 0, 0); |
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val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
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if (val == (int32_t)val) {
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/* eip relative */
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tcg_out8(s, 0x05 | ((r & 7) << 3)); |
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tcg_out32(s, val); |
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} else if (offset == (int32_t)offset) { |
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tcg_out8(s, 0x04 | ((r & 7) << 3)); |
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tcg_out8(s, 0x25); /* sib */ |
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tcg_out32(s, offset); |
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} else {
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tcg_abort(); |
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} |
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} else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
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tcg_out_opc(s, opc, r, rm, 0);
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if ((rm & 7) == TCG_REG_RSP) { |
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tcg_out8(s, 0x04 | ((r & 7) << 3)); |
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tcg_out8(s, 0x24);
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} else {
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tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
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} |
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} else if ((int8_t)offset == offset) { |
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tcg_out_opc(s, opc, r, rm, 0);
|
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if ((rm & 7) == TCG_REG_RSP) { |
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tcg_out8(s, 0x44 | ((r & 7) << 3)); |
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tcg_out8(s, 0x24);
|
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} else {
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tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
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} |
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tcg_out8(s, offset); |
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} else {
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tcg_out_opc(s, opc, r, rm, 0);
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if ((rm & 7) == TCG_REG_RSP) { |
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tcg_out8(s, 0x84 | ((r & 7) << 3)); |
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tcg_out8(s, 0x24);
|
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} else {
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tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
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} |
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tcg_out32(s, offset); |
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} |
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} |
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|
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#if defined(CONFIG_SOFTMMU)
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/* XXX: incomplete. index must be different from ESP */
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static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
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int index, int shift, |
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tcg_target_long offset) |
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{ |
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int mod;
|
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if (rm == -1) |
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tcg_abort(); |
313 |
if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
314 |
mod = 0;
|
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} else if (offset == (int8_t)offset) { |
316 |
mod = 0x40;
|
317 |
} else if (offset == (int32_t)offset) { |
318 |
mod = 0x80;
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} else {
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tcg_abort(); |
321 |
} |
322 |
if (index == -1) { |
323 |
tcg_out_opc(s, opc, r, rm, 0);
|
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if ((rm & 7) == TCG_REG_RSP) { |
325 |
tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
326 |
tcg_out8(s, 0x04 | (rm & 7)); |
327 |
} else {
|
328 |
tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
329 |
} |
330 |
} else {
|
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tcg_out_opc(s, opc, r, rm, index); |
332 |
tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
333 |
tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
334 |
} |
335 |
if (mod == 0x40) { |
336 |
tcg_out8(s, offset); |
337 |
} else if (mod == 0x80) { |
338 |
tcg_out32(s, offset); |
339 |
} |
340 |
} |
341 |
#endif
|
342 |
|
343 |
static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
344 |
{ |
345 |
tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
|
346 |
} |
347 |
|
348 |
static inline void tcg_out_movi(TCGContext *s, TCGType type, |
349 |
int ret, tcg_target_long arg)
|
350 |
{ |
351 |
if (arg == 0) { |
352 |
tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
353 |
} else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
354 |
tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
355 |
tcg_out32(s, arg); |
356 |
} else if (arg == (int32_t)arg) { |
357 |
tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
358 |
tcg_out32(s, arg); |
359 |
} else {
|
360 |
tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
361 |
tcg_out32(s, arg); |
362 |
tcg_out32(s, arg >> 32);
|
363 |
} |
364 |
} |
365 |
|
366 |
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
367 |
int arg1, tcg_target_long arg2)
|
368 |
{ |
369 |
if (type == TCG_TYPE_I32)
|
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tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
371 |
else
|
372 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
373 |
} |
374 |
|
375 |
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
376 |
int arg1, tcg_target_long arg2)
|
377 |
{ |
378 |
if (type == TCG_TYPE_I32)
|
379 |
tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
380 |
else
|
381 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
382 |
} |
383 |
|
384 |
static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
385 |
{ |
386 |
if (val == (int8_t)val) {
|
387 |
tcg_out_modrm(s, 0x83, c, r0);
|
388 |
tcg_out8(s, val); |
389 |
} else if (c == ARITH_AND && val == 0xffu) { |
390 |
/* movzbl */
|
391 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0);
|
392 |
} else if (c == ARITH_AND && val == 0xffffu) { |
393 |
/* movzwl */
|
394 |
tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
|
395 |
} else {
|
396 |
tcg_out_modrm(s, 0x81, c, r0);
|
397 |
tcg_out32(s, val); |
398 |
} |
399 |
} |
400 |
|
401 |
static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
402 |
{ |
403 |
if (val == (int8_t)val) {
|
404 |
tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
|
405 |
tcg_out8(s, val); |
406 |
} else if (c == ARITH_AND && val == 0xffu) { |
407 |
/* movzbl */
|
408 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0);
|
409 |
} else if (c == ARITH_AND && val == 0xffffu) { |
410 |
/* movzwl */
|
411 |
tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0);
|
412 |
} else if (c == ARITH_AND && val == 0xffffffffu) { |
413 |
/* 32-bit mov zero extends */
|
414 |
tcg_out_modrm(s, 0x8b, r0, r0);
|
415 |
} else if (val == (int32_t)val) { |
416 |
tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
417 |
tcg_out32(s, val); |
418 |
} else if (c == ARITH_AND && val == (uint32_t)val) { |
419 |
tcg_out_modrm(s, 0x81, c, r0);
|
420 |
tcg_out32(s, val); |
421 |
} else {
|
422 |
tcg_abort(); |
423 |
} |
424 |
} |
425 |
|
426 |
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
427 |
{ |
428 |
if (val != 0) |
429 |
tgen_arithi64(s, ARITH_ADD, reg, val); |
430 |
} |
431 |
|
432 |
static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
433 |
{ |
434 |
int32_t val, val1; |
435 |
TCGLabel *l = &s->labels[label_index]; |
436 |
|
437 |
if (l->has_value) {
|
438 |
val = l->u.value - (tcg_target_long)s->code_ptr; |
439 |
val1 = val - 2;
|
440 |
if ((int8_t)val1 == val1) {
|
441 |
if (opc == -1) |
442 |
tcg_out8(s, 0xeb);
|
443 |
else
|
444 |
tcg_out8(s, 0x70 + opc);
|
445 |
tcg_out8(s, val1); |
446 |
} else {
|
447 |
if (opc == -1) { |
448 |
tcg_out8(s, 0xe9);
|
449 |
tcg_out32(s, val - 5);
|
450 |
} else {
|
451 |
tcg_out8(s, 0x0f);
|
452 |
tcg_out8(s, 0x80 + opc);
|
453 |
tcg_out32(s, val - 6);
|
454 |
} |
455 |
} |
456 |
} else {
|
457 |
if (opc == -1) { |
458 |
tcg_out8(s, 0xe9);
|
459 |
} else {
|
460 |
tcg_out8(s, 0x0f);
|
461 |
tcg_out8(s, 0x80 + opc);
|
462 |
} |
463 |
tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
464 |
s->code_ptr += 4;
|
465 |
} |
466 |
} |
467 |
|
468 |
static void tcg_out_brcond(TCGContext *s, int cond, |
469 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
470 |
int label_index, int rexw) |
471 |
{ |
472 |
if (const_arg2) {
|
473 |
if (arg2 == 0) { |
474 |
/* test r, r */
|
475 |
tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
476 |
} else {
|
477 |
if (rexw)
|
478 |
tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
479 |
else
|
480 |
tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
481 |
} |
482 |
} else {
|
483 |
tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
484 |
} |
485 |
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
486 |
} |
487 |
|
488 |
#if defined(CONFIG_SOFTMMU)
|
489 |
|
490 |
#include "../../softmmu_defs.h" |
491 |
|
492 |
static void *qemu_ld_helpers[4] = { |
493 |
__ldb_mmu, |
494 |
__ldw_mmu, |
495 |
__ldl_mmu, |
496 |
__ldq_mmu, |
497 |
}; |
498 |
|
499 |
static void *qemu_st_helpers[4] = { |
500 |
__stb_mmu, |
501 |
__stw_mmu, |
502 |
__stl_mmu, |
503 |
__stq_mmu, |
504 |
}; |
505 |
#endif
|
506 |
|
507 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
508 |
int opc)
|
509 |
{ |
510 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
511 |
int32_t offset; |
512 |
#if defined(CONFIG_SOFTMMU)
|
513 |
uint8_t *label1_ptr, *label2_ptr; |
514 |
#endif
|
515 |
|
516 |
data_reg = *args++; |
517 |
addr_reg = *args++; |
518 |
mem_index = *args; |
519 |
s_bits = opc & 3;
|
520 |
|
521 |
r0 = TCG_REG_RDI; |
522 |
r1 = TCG_REG_RSI; |
523 |
|
524 |
#if TARGET_LONG_BITS == 32 |
525 |
rexw = 0;
|
526 |
#else
|
527 |
rexw = P_REXW; |
528 |
#endif
|
529 |
#if defined(CONFIG_SOFTMMU)
|
530 |
/* mov */
|
531 |
tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
532 |
|
533 |
/* mov */
|
534 |
tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
535 |
|
536 |
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
537 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
538 |
|
539 |
tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
540 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
541 |
|
542 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
543 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
544 |
|
545 |
/* lea offset(r1, env), r1 */
|
546 |
tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
547 |
offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
548 |
|
549 |
/* cmp 0(r1), r0 */
|
550 |
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
551 |
|
552 |
/* mov */
|
553 |
tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
554 |
|
555 |
/* je label1 */
|
556 |
tcg_out8(s, 0x70 + JCC_JE);
|
557 |
label1_ptr = s->code_ptr; |
558 |
s->code_ptr++; |
559 |
|
560 |
/* XXX: move that code at the end of the TB */
|
561 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
562 |
tcg_out8(s, 0xe8);
|
563 |
tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - |
564 |
(tcg_target_long)s->code_ptr - 4);
|
565 |
|
566 |
switch(opc) {
|
567 |
case 0 | 4: |
568 |
/* movsbq */
|
569 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
570 |
break;
|
571 |
case 1 | 4: |
572 |
/* movswq */
|
573 |
tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
574 |
break;
|
575 |
case 2 | 4: |
576 |
/* movslq */
|
577 |
tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
578 |
break;
|
579 |
case 0: |
580 |
/* movzbq */
|
581 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
582 |
break;
|
583 |
case 1: |
584 |
/* movzwq */
|
585 |
tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
586 |
break;
|
587 |
case 2: |
588 |
default:
|
589 |
/* movl */
|
590 |
tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
|
591 |
break;
|
592 |
case 3: |
593 |
tcg_out_mov(s, data_reg, TCG_REG_RAX); |
594 |
break;
|
595 |
} |
596 |
|
597 |
/* jmp label2 */
|
598 |
tcg_out8(s, 0xeb);
|
599 |
label2_ptr = s->code_ptr; |
600 |
s->code_ptr++; |
601 |
|
602 |
/* label1: */
|
603 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
604 |
|
605 |
/* add x(r1), r0 */
|
606 |
tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
607 |
offsetof(CPUTLBEntry, addr_read)); |
608 |
offset = 0;
|
609 |
#else
|
610 |
if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
611 |
r0 = addr_reg; |
612 |
offset = GUEST_BASE; |
613 |
} else {
|
614 |
offset = 0;
|
615 |
/* movq $GUEST_BASE, r0 */
|
616 |
tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
617 |
tcg_out32(s, GUEST_BASE); |
618 |
tcg_out32(s, GUEST_BASE >> 32);
|
619 |
/* addq addr_reg, r0 */
|
620 |
tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
621 |
} |
622 |
#endif
|
623 |
|
624 |
#ifdef TARGET_WORDS_BIGENDIAN
|
625 |
bswap = 1;
|
626 |
#else
|
627 |
bswap = 0;
|
628 |
#endif
|
629 |
switch(opc) {
|
630 |
case 0: |
631 |
/* movzbl */
|
632 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
|
633 |
break;
|
634 |
case 0 | 4: |
635 |
/* movsbX */
|
636 |
tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
|
637 |
break;
|
638 |
case 1: |
639 |
/* movzwl */
|
640 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
641 |
if (bswap) {
|
642 |
/* rolw $8, data_reg */
|
643 |
tcg_out8(s, 0x66);
|
644 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
645 |
tcg_out8(s, 8);
|
646 |
} |
647 |
break;
|
648 |
case 1 | 4: |
649 |
if (bswap) {
|
650 |
/* movzwl */
|
651 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
652 |
/* rolw $8, data_reg */
|
653 |
tcg_out8(s, 0x66);
|
654 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
655 |
tcg_out8(s, 8);
|
656 |
|
657 |
/* movswX data_reg, data_reg */
|
658 |
tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
659 |
} else {
|
660 |
/* movswX */
|
661 |
tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
|
662 |
} |
663 |
break;
|
664 |
case 2: |
665 |
/* movl (r0), data_reg */
|
666 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
667 |
if (bswap) {
|
668 |
/* bswap */
|
669 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
670 |
} |
671 |
break;
|
672 |
case 2 | 4: |
673 |
if (bswap) {
|
674 |
/* movl (r0), data_reg */
|
675 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
676 |
/* bswap */
|
677 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
678 |
/* movslq */
|
679 |
tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
680 |
} else {
|
681 |
/* movslq */
|
682 |
tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
|
683 |
} |
684 |
break;
|
685 |
case 3: |
686 |
/* movq (r0), data_reg */
|
687 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
|
688 |
if (bswap) {
|
689 |
/* bswap */
|
690 |
tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
691 |
} |
692 |
break;
|
693 |
default:
|
694 |
tcg_abort(); |
695 |
} |
696 |
|
697 |
#if defined(CONFIG_SOFTMMU)
|
698 |
/* label2: */
|
699 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
700 |
#endif
|
701 |
} |
702 |
|
703 |
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
704 |
int opc)
|
705 |
{ |
706 |
int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
707 |
int32_t offset; |
708 |
#if defined(CONFIG_SOFTMMU)
|
709 |
uint8_t *label1_ptr, *label2_ptr; |
710 |
#endif
|
711 |
|
712 |
data_reg = *args++; |
713 |
addr_reg = *args++; |
714 |
mem_index = *args; |
715 |
|
716 |
s_bits = opc; |
717 |
|
718 |
r0 = TCG_REG_RDI; |
719 |
r1 = TCG_REG_RSI; |
720 |
|
721 |
#if TARGET_LONG_BITS == 32 |
722 |
rexw = 0;
|
723 |
#else
|
724 |
rexw = P_REXW; |
725 |
#endif
|
726 |
#if defined(CONFIG_SOFTMMU)
|
727 |
/* mov */
|
728 |
tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
729 |
|
730 |
/* mov */
|
731 |
tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
732 |
|
733 |
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
734 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
735 |
|
736 |
tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
737 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
738 |
|
739 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
740 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
741 |
|
742 |
/* lea offset(r1, env), r1 */
|
743 |
tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
744 |
offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
745 |
|
746 |
/* cmp 0(r1), r0 */
|
747 |
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
748 |
|
749 |
/* mov */
|
750 |
tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
751 |
|
752 |
/* je label1 */
|
753 |
tcg_out8(s, 0x70 + JCC_JE);
|
754 |
label1_ptr = s->code_ptr; |
755 |
s->code_ptr++; |
756 |
|
757 |
/* XXX: move that code at the end of the TB */
|
758 |
switch(opc) {
|
759 |
case 0: |
760 |
/* movzbl */
|
761 |
tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg);
|
762 |
break;
|
763 |
case 1: |
764 |
/* movzwl */
|
765 |
tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
766 |
break;
|
767 |
case 2: |
768 |
/* movl */
|
769 |
tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
|
770 |
break;
|
771 |
default:
|
772 |
case 3: |
773 |
tcg_out_mov(s, TCG_REG_RSI, data_reg); |
774 |
break;
|
775 |
} |
776 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
777 |
tcg_out8(s, 0xe8);
|
778 |
tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
779 |
(tcg_target_long)s->code_ptr - 4);
|
780 |
|
781 |
/* jmp label2 */
|
782 |
tcg_out8(s, 0xeb);
|
783 |
label2_ptr = s->code_ptr; |
784 |
s->code_ptr++; |
785 |
|
786 |
/* label1: */
|
787 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
788 |
|
789 |
/* add x(r1), r0 */
|
790 |
tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
791 |
offsetof(CPUTLBEntry, addr_write)); |
792 |
offset = 0;
|
793 |
#else
|
794 |
if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
795 |
r0 = addr_reg; |
796 |
offset = GUEST_BASE; |
797 |
} else {
|
798 |
offset = 0;
|
799 |
/* movq $GUEST_BASE, r0 */
|
800 |
tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
801 |
tcg_out32(s, GUEST_BASE); |
802 |
tcg_out32(s, GUEST_BASE >> 32);
|
803 |
/* addq addr_reg, r0 */
|
804 |
tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
805 |
} |
806 |
#endif
|
807 |
|
808 |
#ifdef TARGET_WORDS_BIGENDIAN
|
809 |
bswap = 1;
|
810 |
#else
|
811 |
bswap = 0;
|
812 |
#endif
|
813 |
switch(opc) {
|
814 |
case 0: |
815 |
/* movb */
|
816 |
tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset);
|
817 |
break;
|
818 |
case 1: |
819 |
if (bswap) {
|
820 |
tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
821 |
tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
822 |
tcg_out_modrm(s, 0xc1, 0, r1); |
823 |
tcg_out8(s, 8);
|
824 |
data_reg = r1; |
825 |
} |
826 |
/* movw */
|
827 |
tcg_out8(s, 0x66);
|
828 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
829 |
break;
|
830 |
case 2: |
831 |
if (bswap) {
|
832 |
tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
833 |
/* bswap data_reg */
|
834 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
835 |
data_reg = r1; |
836 |
} |
837 |
/* movl */
|
838 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
839 |
break;
|
840 |
case 3: |
841 |
if (bswap) {
|
842 |
tcg_out_mov(s, r1, data_reg); |
843 |
/* bswap data_reg */
|
844 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
845 |
data_reg = r1; |
846 |
} |
847 |
/* movq */
|
848 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
|
849 |
break;
|
850 |
default:
|
851 |
tcg_abort(); |
852 |
} |
853 |
|
854 |
#if defined(CONFIG_SOFTMMU)
|
855 |
/* label2: */
|
856 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
857 |
#endif
|
858 |
} |
859 |
|
860 |
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
861 |
const int *const_args) |
862 |
{ |
863 |
int c;
|
864 |
|
865 |
switch(opc) {
|
866 |
case INDEX_op_exit_tb:
|
867 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
868 |
tcg_out8(s, 0xe9); /* jmp tb_ret_addr */ |
869 |
tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
|
870 |
break;
|
871 |
case INDEX_op_goto_tb:
|
872 |
if (s->tb_jmp_offset) {
|
873 |
/* direct jump method */
|
874 |
tcg_out8(s, 0xe9); /* jmp im */ |
875 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
876 |
tcg_out32(s, 0);
|
877 |
} else {
|
878 |
/* indirect jump method */
|
879 |
/* jmp Ev */
|
880 |
tcg_out_modrm_offset(s, 0xff, 4, -1, |
881 |
(tcg_target_long)(s->tb_next + |
882 |
args[0]));
|
883 |
} |
884 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
885 |
break;
|
886 |
case INDEX_op_call:
|
887 |
if (const_args[0]) { |
888 |
tcg_out8(s, 0xe8);
|
889 |
tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
890 |
} else {
|
891 |
tcg_out_modrm(s, 0xff, 2, args[0]); |
892 |
} |
893 |
break;
|
894 |
case INDEX_op_jmp:
|
895 |
if (const_args[0]) { |
896 |
tcg_out8(s, 0xe9);
|
897 |
tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
898 |
} else {
|
899 |
tcg_out_modrm(s, 0xff, 4, args[0]); |
900 |
} |
901 |
break;
|
902 |
case INDEX_op_br:
|
903 |
tcg_out_jxx(s, JCC_JMP, args[0]);
|
904 |
break;
|
905 |
case INDEX_op_movi_i32:
|
906 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
907 |
break;
|
908 |
case INDEX_op_movi_i64:
|
909 |
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
910 |
break;
|
911 |
case INDEX_op_ld8u_i32:
|
912 |
case INDEX_op_ld8u_i64:
|
913 |
/* movzbl */
|
914 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
915 |
break;
|
916 |
case INDEX_op_ld8s_i32:
|
917 |
/* movsbl */
|
918 |
tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
919 |
break;
|
920 |
case INDEX_op_ld8s_i64:
|
921 |
/* movsbq */
|
922 |
tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
923 |
break;
|
924 |
case INDEX_op_ld16u_i32:
|
925 |
case INDEX_op_ld16u_i64:
|
926 |
/* movzwl */
|
927 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
928 |
break;
|
929 |
case INDEX_op_ld16s_i32:
|
930 |
/* movswl */
|
931 |
tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
932 |
break;
|
933 |
case INDEX_op_ld16s_i64:
|
934 |
/* movswq */
|
935 |
tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
936 |
break;
|
937 |
case INDEX_op_ld_i32:
|
938 |
case INDEX_op_ld32u_i64:
|
939 |
/* movl */
|
940 |
tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
941 |
break;
|
942 |
case INDEX_op_ld32s_i64:
|
943 |
/* movslq */
|
944 |
tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
945 |
break;
|
946 |
case INDEX_op_ld_i64:
|
947 |
/* movq */
|
948 |
tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
949 |
break;
|
950 |
|
951 |
case INDEX_op_st8_i32:
|
952 |
case INDEX_op_st8_i64:
|
953 |
/* movb */
|
954 |
tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]); |
955 |
break;
|
956 |
case INDEX_op_st16_i32:
|
957 |
case INDEX_op_st16_i64:
|
958 |
/* movw */
|
959 |
tcg_out8(s, 0x66);
|
960 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
961 |
break;
|
962 |
case INDEX_op_st_i32:
|
963 |
case INDEX_op_st32_i64:
|
964 |
/* movl */
|
965 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
966 |
break;
|
967 |
case INDEX_op_st_i64:
|
968 |
/* movq */
|
969 |
tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
970 |
break;
|
971 |
|
972 |
case INDEX_op_sub_i32:
|
973 |
c = ARITH_SUB; |
974 |
goto gen_arith32;
|
975 |
case INDEX_op_and_i32:
|
976 |
c = ARITH_AND; |
977 |
goto gen_arith32;
|
978 |
case INDEX_op_or_i32:
|
979 |
c = ARITH_OR; |
980 |
goto gen_arith32;
|
981 |
case INDEX_op_xor_i32:
|
982 |
c = ARITH_XOR; |
983 |
goto gen_arith32;
|
984 |
case INDEX_op_add_i32:
|
985 |
c = ARITH_ADD; |
986 |
gen_arith32:
|
987 |
if (const_args[2]) { |
988 |
tgen_arithi32(s, c, args[0], args[2]); |
989 |
} else {
|
990 |
tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
991 |
} |
992 |
break;
|
993 |
|
994 |
case INDEX_op_sub_i64:
|
995 |
c = ARITH_SUB; |
996 |
goto gen_arith64;
|
997 |
case INDEX_op_and_i64:
|
998 |
c = ARITH_AND; |
999 |
goto gen_arith64;
|
1000 |
case INDEX_op_or_i64:
|
1001 |
c = ARITH_OR; |
1002 |
goto gen_arith64;
|
1003 |
case INDEX_op_xor_i64:
|
1004 |
c = ARITH_XOR; |
1005 |
goto gen_arith64;
|
1006 |
case INDEX_op_add_i64:
|
1007 |
c = ARITH_ADD; |
1008 |
gen_arith64:
|
1009 |
if (const_args[2]) { |
1010 |
tgen_arithi64(s, c, args[0], args[2]); |
1011 |
} else {
|
1012 |
tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
1013 |
} |
1014 |
break;
|
1015 |
|
1016 |
case INDEX_op_mul_i32:
|
1017 |
if (const_args[2]) { |
1018 |
int32_t val; |
1019 |
val = args[2];
|
1020 |
if (val == (int8_t)val) {
|
1021 |
tcg_out_modrm(s, 0x6b, args[0], args[0]); |
1022 |
tcg_out8(s, val); |
1023 |
} else {
|
1024 |
tcg_out_modrm(s, 0x69, args[0], args[0]); |
1025 |
tcg_out32(s, val); |
1026 |
} |
1027 |
} else {
|
1028 |
tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
1029 |
} |
1030 |
break;
|
1031 |
case INDEX_op_mul_i64:
|
1032 |
if (const_args[2]) { |
1033 |
int32_t val; |
1034 |
val = args[2];
|
1035 |
if (val == (int8_t)val) {
|
1036 |
tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
1037 |
tcg_out8(s, val); |
1038 |
} else {
|
1039 |
tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
1040 |
tcg_out32(s, val); |
1041 |
} |
1042 |
} else {
|
1043 |
tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
1044 |
} |
1045 |
break;
|
1046 |
case INDEX_op_div2_i32:
|
1047 |
tcg_out_modrm(s, 0xf7, 7, args[4]); |
1048 |
break;
|
1049 |
case INDEX_op_divu2_i32:
|
1050 |
tcg_out_modrm(s, 0xf7, 6, args[4]); |
1051 |
break;
|
1052 |
case INDEX_op_div2_i64:
|
1053 |
tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
1054 |
break;
|
1055 |
case INDEX_op_divu2_i64:
|
1056 |
tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
1057 |
break;
|
1058 |
|
1059 |
case INDEX_op_shl_i32:
|
1060 |
c = SHIFT_SHL; |
1061 |
gen_shift32:
|
1062 |
if (const_args[2]) { |
1063 |
if (args[2] == 1) { |
1064 |
tcg_out_modrm(s, 0xd1, c, args[0]); |
1065 |
} else {
|
1066 |
tcg_out_modrm(s, 0xc1, c, args[0]); |
1067 |
tcg_out8(s, args[2]);
|
1068 |
} |
1069 |
} else {
|
1070 |
tcg_out_modrm(s, 0xd3, c, args[0]); |
1071 |
} |
1072 |
break;
|
1073 |
case INDEX_op_shr_i32:
|
1074 |
c = SHIFT_SHR; |
1075 |
goto gen_shift32;
|
1076 |
case INDEX_op_sar_i32:
|
1077 |
c = SHIFT_SAR; |
1078 |
goto gen_shift32;
|
1079 |
case INDEX_op_rotl_i32:
|
1080 |
c = SHIFT_ROL; |
1081 |
goto gen_shift32;
|
1082 |
case INDEX_op_rotr_i32:
|
1083 |
c = SHIFT_ROR; |
1084 |
goto gen_shift32;
|
1085 |
|
1086 |
case INDEX_op_shl_i64:
|
1087 |
c = SHIFT_SHL; |
1088 |
gen_shift64:
|
1089 |
if (const_args[2]) { |
1090 |
if (args[2] == 1) { |
1091 |
tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
1092 |
} else {
|
1093 |
tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
1094 |
tcg_out8(s, args[2]);
|
1095 |
} |
1096 |
} else {
|
1097 |
tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
1098 |
} |
1099 |
break;
|
1100 |
case INDEX_op_shr_i64:
|
1101 |
c = SHIFT_SHR; |
1102 |
goto gen_shift64;
|
1103 |
case INDEX_op_sar_i64:
|
1104 |
c = SHIFT_SAR; |
1105 |
goto gen_shift64;
|
1106 |
case INDEX_op_rotl_i64:
|
1107 |
c = SHIFT_ROL; |
1108 |
goto gen_shift64;
|
1109 |
case INDEX_op_rotr_i64:
|
1110 |
c = SHIFT_ROR; |
1111 |
goto gen_shift64;
|
1112 |
|
1113 |
case INDEX_op_brcond_i32:
|
1114 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1115 |
args[3], 0); |
1116 |
break;
|
1117 |
case INDEX_op_brcond_i64:
|
1118 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1119 |
args[3], P_REXW);
|
1120 |
break;
|
1121 |
|
1122 |
case INDEX_op_bswap16_i32:
|
1123 |
case INDEX_op_bswap16_i64:
|
1124 |
tcg_out8(s, 0x66);
|
1125 |
tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1126 |
tcg_out8(s, 8);
|
1127 |
break;
|
1128 |
case INDEX_op_bswap32_i32:
|
1129 |
case INDEX_op_bswap32_i64:
|
1130 |
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
1131 |
break;
|
1132 |
case INDEX_op_bswap64_i64:
|
1133 |
tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
1134 |
break;
|
1135 |
|
1136 |
case INDEX_op_neg_i32:
|
1137 |
tcg_out_modrm(s, 0xf7, 3, args[0]); |
1138 |
break;
|
1139 |
case INDEX_op_neg_i64:
|
1140 |
tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]); |
1141 |
break;
|
1142 |
|
1143 |
case INDEX_op_not_i32:
|
1144 |
tcg_out_modrm(s, 0xf7, 2, args[0]); |
1145 |
break;
|
1146 |
case INDEX_op_not_i64:
|
1147 |
tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]); |
1148 |
break;
|
1149 |
|
1150 |
case INDEX_op_ext8s_i32:
|
1151 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]); |
1152 |
break;
|
1153 |
case INDEX_op_ext16s_i32:
|
1154 |
tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1155 |
break;
|
1156 |
case INDEX_op_ext8s_i64:
|
1157 |
tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]); |
1158 |
break;
|
1159 |
case INDEX_op_ext16s_i64:
|
1160 |
tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]); |
1161 |
break;
|
1162 |
case INDEX_op_ext32s_i64:
|
1163 |
tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]); |
1164 |
break;
|
1165 |
|
1166 |
case INDEX_op_qemu_ld8u:
|
1167 |
tcg_out_qemu_ld(s, args, 0);
|
1168 |
break;
|
1169 |
case INDEX_op_qemu_ld8s:
|
1170 |
tcg_out_qemu_ld(s, args, 0 | 4); |
1171 |
break;
|
1172 |
case INDEX_op_qemu_ld16u:
|
1173 |
tcg_out_qemu_ld(s, args, 1);
|
1174 |
break;
|
1175 |
case INDEX_op_qemu_ld16s:
|
1176 |
tcg_out_qemu_ld(s, args, 1 | 4); |
1177 |
break;
|
1178 |
case INDEX_op_qemu_ld32u:
|
1179 |
tcg_out_qemu_ld(s, args, 2);
|
1180 |
break;
|
1181 |
case INDEX_op_qemu_ld32s:
|
1182 |
tcg_out_qemu_ld(s, args, 2 | 4); |
1183 |
break;
|
1184 |
case INDEX_op_qemu_ld64:
|
1185 |
tcg_out_qemu_ld(s, args, 3);
|
1186 |
break;
|
1187 |
|
1188 |
case INDEX_op_qemu_st8:
|
1189 |
tcg_out_qemu_st(s, args, 0);
|
1190 |
break;
|
1191 |
case INDEX_op_qemu_st16:
|
1192 |
tcg_out_qemu_st(s, args, 1);
|
1193 |
break;
|
1194 |
case INDEX_op_qemu_st32:
|
1195 |
tcg_out_qemu_st(s, args, 2);
|
1196 |
break;
|
1197 |
case INDEX_op_qemu_st64:
|
1198 |
tcg_out_qemu_st(s, args, 3);
|
1199 |
break;
|
1200 |
|
1201 |
default:
|
1202 |
tcg_abort(); |
1203 |
} |
1204 |
} |
1205 |
|
1206 |
static int tcg_target_callee_save_regs[] = { |
1207 |
TCG_REG_RBP, |
1208 |
TCG_REG_RBX, |
1209 |
TCG_REG_R12, |
1210 |
TCG_REG_R13, |
1211 |
/* TCG_REG_R14, */ /* currently used for the global env, so no |
1212 |
need to save */
|
1213 |
TCG_REG_R15, |
1214 |
}; |
1215 |
|
1216 |
static inline void tcg_out_push(TCGContext *s, int reg) |
1217 |
{ |
1218 |
tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0); |
1219 |
} |
1220 |
|
1221 |
static inline void tcg_out_pop(TCGContext *s, int reg) |
1222 |
{ |
1223 |
tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0); |
1224 |
} |
1225 |
|
1226 |
/* Generate global QEMU prologue and epilogue code */
|
1227 |
void tcg_target_qemu_prologue(TCGContext *s)
|
1228 |
{ |
1229 |
int i, frame_size, push_size, stack_addend;
|
1230 |
|
1231 |
/* TB prologue */
|
1232 |
/* save all callee saved registers */
|
1233 |
for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1234 |
tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1235 |
|
1236 |
} |
1237 |
/* reserve some stack space */
|
1238 |
push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8; |
1239 |
frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1240 |
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1241 |
~(TCG_TARGET_STACK_ALIGN - 1);
|
1242 |
stack_addend = frame_size - push_size; |
1243 |
tcg_out_addi(s, TCG_REG_RSP, -stack_addend); |
1244 |
|
1245 |
tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */ |
1246 |
|
1247 |
/* TB epilogue */
|
1248 |
tb_ret_addr = s->code_ptr; |
1249 |
tcg_out_addi(s, TCG_REG_RSP, stack_addend); |
1250 |
for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1251 |
tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1252 |
} |
1253 |
tcg_out8(s, 0xc3); /* ret */ |
1254 |
} |
1255 |
|
1256 |
static const TCGTargetOpDef x86_64_op_defs[] = { |
1257 |
{ INDEX_op_exit_tb, { } }, |
1258 |
{ INDEX_op_goto_tb, { } }, |
1259 |
{ INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1260 |
{ INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1261 |
{ INDEX_op_br, { } }, |
1262 |
|
1263 |
{ INDEX_op_mov_i32, { "r", "r" } }, |
1264 |
{ INDEX_op_movi_i32, { "r" } },
|
1265 |
{ INDEX_op_ld8u_i32, { "r", "r" } }, |
1266 |
{ INDEX_op_ld8s_i32, { "r", "r" } }, |
1267 |
{ INDEX_op_ld16u_i32, { "r", "r" } }, |
1268 |
{ INDEX_op_ld16s_i32, { "r", "r" } }, |
1269 |
{ INDEX_op_ld_i32, { "r", "r" } }, |
1270 |
{ INDEX_op_st8_i32, { "r", "r" } }, |
1271 |
{ INDEX_op_st16_i32, { "r", "r" } }, |
1272 |
{ INDEX_op_st_i32, { "r", "r" } }, |
1273 |
|
1274 |
{ INDEX_op_add_i32, { "r", "0", "ri" } }, |
1275 |
{ INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1276 |
{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1277 |
{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1278 |
{ INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1279 |
{ INDEX_op_and_i32, { "r", "0", "ri" } }, |
1280 |
{ INDEX_op_or_i32, { "r", "0", "ri" } }, |
1281 |
{ INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1282 |
|
1283 |
{ INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1284 |
{ INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1285 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1286 |
{ INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1287 |
{ INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1288 |
|
1289 |
{ INDEX_op_brcond_i32, { "r", "ri" } }, |
1290 |
|
1291 |
{ INDEX_op_mov_i64, { "r", "r" } }, |
1292 |
{ INDEX_op_movi_i64, { "r" } },
|
1293 |
{ INDEX_op_ld8u_i64, { "r", "r" } }, |
1294 |
{ INDEX_op_ld8s_i64, { "r", "r" } }, |
1295 |
{ INDEX_op_ld16u_i64, { "r", "r" } }, |
1296 |
{ INDEX_op_ld16s_i64, { "r", "r" } }, |
1297 |
{ INDEX_op_ld32u_i64, { "r", "r" } }, |
1298 |
{ INDEX_op_ld32s_i64, { "r", "r" } }, |
1299 |
{ INDEX_op_ld_i64, { "r", "r" } }, |
1300 |
{ INDEX_op_st8_i64, { "r", "r" } }, |
1301 |
{ INDEX_op_st16_i64, { "r", "r" } }, |
1302 |
{ INDEX_op_st32_i64, { "r", "r" } }, |
1303 |
{ INDEX_op_st_i64, { "r", "r" } }, |
1304 |
|
1305 |
{ INDEX_op_add_i64, { "r", "0", "re" } }, |
1306 |
{ INDEX_op_mul_i64, { "r", "0", "re" } }, |
1307 |
{ INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
1308 |
{ INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
1309 |
{ INDEX_op_sub_i64, { "r", "0", "re" } }, |
1310 |
{ INDEX_op_and_i64, { "r", "0", "reZ" } }, |
1311 |
{ INDEX_op_or_i64, { "r", "0", "re" } }, |
1312 |
{ INDEX_op_xor_i64, { "r", "0", "re" } }, |
1313 |
|
1314 |
{ INDEX_op_shl_i64, { "r", "0", "ci" } }, |
1315 |
{ INDEX_op_shr_i64, { "r", "0", "ci" } }, |
1316 |
{ INDEX_op_sar_i64, { "r", "0", "ci" } }, |
1317 |
{ INDEX_op_rotl_i64, { "r", "0", "ci" } }, |
1318 |
{ INDEX_op_rotr_i64, { "r", "0", "ci" } }, |
1319 |
|
1320 |
{ INDEX_op_brcond_i64, { "r", "re" } }, |
1321 |
|
1322 |
{ INDEX_op_bswap16_i32, { "r", "0" } }, |
1323 |
{ INDEX_op_bswap16_i64, { "r", "0" } }, |
1324 |
{ INDEX_op_bswap32_i32, { "r", "0" } }, |
1325 |
{ INDEX_op_bswap32_i64, { "r", "0" } }, |
1326 |
{ INDEX_op_bswap64_i64, { "r", "0" } }, |
1327 |
|
1328 |
{ INDEX_op_neg_i32, { "r", "0" } }, |
1329 |
{ INDEX_op_neg_i64, { "r", "0" } }, |
1330 |
|
1331 |
{ INDEX_op_not_i32, { "r", "0" } }, |
1332 |
{ INDEX_op_not_i64, { "r", "0" } }, |
1333 |
|
1334 |
{ INDEX_op_ext8s_i32, { "r", "r"} }, |
1335 |
{ INDEX_op_ext16s_i32, { "r", "r"} }, |
1336 |
{ INDEX_op_ext8s_i64, { "r", "r"} }, |
1337 |
{ INDEX_op_ext16s_i64, { "r", "r"} }, |
1338 |
{ INDEX_op_ext32s_i64, { "r", "r"} }, |
1339 |
|
1340 |
{ INDEX_op_qemu_ld8u, { "r", "L" } }, |
1341 |
{ INDEX_op_qemu_ld8s, { "r", "L" } }, |
1342 |
{ INDEX_op_qemu_ld16u, { "r", "L" } }, |
1343 |
{ INDEX_op_qemu_ld16s, { "r", "L" } }, |
1344 |
{ INDEX_op_qemu_ld32u, { "r", "L" } }, |
1345 |
{ INDEX_op_qemu_ld32s, { "r", "L" } }, |
1346 |
{ INDEX_op_qemu_ld64, { "r", "L" } }, |
1347 |
|
1348 |
{ INDEX_op_qemu_st8, { "L", "L" } }, |
1349 |
{ INDEX_op_qemu_st16, { "L", "L" } }, |
1350 |
{ INDEX_op_qemu_st32, { "L", "L" } }, |
1351 |
{ INDEX_op_qemu_st64, { "L", "L", "L" } }, |
1352 |
|
1353 |
{ -1 },
|
1354 |
}; |
1355 |
|
1356 |
void tcg_target_init(TCGContext *s)
|
1357 |
{ |
1358 |
/* fail safe */
|
1359 |
if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1360 |
tcg_abort(); |
1361 |
|
1362 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
1363 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
1364 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1365 |
(1 << TCG_REG_RDI) |
|
1366 |
(1 << TCG_REG_RSI) |
|
1367 |
(1 << TCG_REG_RDX) |
|
1368 |
(1 << TCG_REG_RCX) |
|
1369 |
(1 << TCG_REG_R8) |
|
1370 |
(1 << TCG_REG_R9) |
|
1371 |
(1 << TCG_REG_RAX) |
|
1372 |
(1 << TCG_REG_R10) |
|
1373 |
(1 << TCG_REG_R11));
|
1374 |
|
1375 |
tcg_regset_clear(s->reserved_regs); |
1376 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
1377 |
|
1378 |
tcg_add_target_add_op_defs(x86_64_op_defs); |
1379 |
} |