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# Date Author Comment
96d922a6 11/19/2011 01:22 pm Fabien Chouteau

Improve "ta 0" shutdown

This patch replace the previous implementation with this simplified and
more complete version (no shutdown when psret == 1).

Signed-off-by: Fabien Chouteau <>
Signed-off-by: Blue Swirl <>
6c073553 10/27/2011 12:00 am Richard Henderson

target-sparc: Implement EDGE* instructions.

Signed-off-by: Richard Henderson <>
add545ab 10/27/2011 12:00 am Richard Henderson

target-sparc: Implement ALIGNADDR* inline.

While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not
implemeneted at all. However, this is a very simple operation
so we're better off doing this inline.

Signed-off-by: Richard Henderson <>
793a137a 10/27/2011 12:00 am Richard Henderson

target-sparc: Implement BMASK/BSHUFFLE.

Signed-off-by: Richard Henderson <>
50c796f9 10/27/2011 12:00 am Richard Henderson

target-sparc: Implement FALIGNDATA inline.

This is a relatively simple sequence of shifts.

Signed-off-by: Richard Henderson <>
2dedf314 10/27/2011 12:00 am Richard Henderson

target-sparc: Implement fpack{16,32,fix}.

Signed-off-by: Richard Henderson <>
f888300b 10/26/2011 11:58 pm Richard Henderson

target-sparc: Implement PDIST.

Signed-off-by: Richard Henderson <>
44516772 10/26/2011 11:57 pm Richard Henderson

target-sparc: Do exceptions management fully inside the helpers.

This reduces the size of the individual translation blocks, since
we only emit a single call for each FOP rather than three. In
addition, clear_float_exceptions expands inline to a single byte store....
ac11f776 10/26/2011 11:55 pm Richard Henderson

target-sparc: Extract float128 move to a function.

Signed-off-by: Richard Henderson <>
45c7b743 10/26/2011 11:55 pm Richard Henderson

target-sparc: Undo cpu_fpr rename.

Signed-off-by: Richard Henderson <>
30038fd8 10/26/2011 11:55 pm Richard Henderson

target-sparc: Change fpr representation to doubles.

This allows a more efficient representation for 64-bit hosts.
It should be about the same for 32-bit hosts, as we can still
access the individual pieces of the double.

Signed-off-by: Richard Henderson <>
61f17f6e 10/26/2011 11:55 pm Richard Henderson

target-sparc: Extract common code for floating-point operations.

Signed-off-by: Richard Henderson <>
141ae5c1 10/26/2011 11:50 pm Richard Henderson

target-sparc: Mark fprs dirty in store accessor.

Signed-off-by: Richard Henderson <>
96eda024 10/26/2011 11:50 pm Richard Henderson

target-sparc: Add accessors for double-precision fpr access.

Begin using i64 quantities to manipulate double-precision values.
On a 64-bit host this will, for the moment, generate less efficient
code; on a 32-bit host code quality should be largely unchanged....
03fb8cfc 10/26/2011 11:50 pm Richard Henderson

target-sparc: Pass float64 parameters instead of dt0/1 temporaries.

Signed-off-by: Richard Henderson <>
f027c3b1 10/26/2011 11:50 pm Richard Henderson

target-sparc: Make FPU/VIS helpers const when possible.

This also removes the unused ENV parameter from these helpers.

Signed-off-by: Richard Henderson <>
208ae657 10/26/2011 11:50 pm Richard Henderson

target-sparc: Add accessors for single-precision fpr access.

Load, store, and "create destination". This version attempts to
change the behaviour of the translator as little as possible. We
previously used cpu_tmp32 as the temporary destination, and we...
7a5e4488 10/26/2011 08:18 pm Blue Swirl

Sparc: avoid AREG0 for division op helpers

Make [su]div{,cc} helpers take a parameter for CPUState instead
of relying on global env. Move the functions to helper.c.

Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
79227036 10/26/2011 08:18 pm Blue Swirl

Sparc: avoid AREG0 for softint op helpers and Leon cache control

Make softint op helpers and Leon cache irq manager take a parameter
for CPUState instead of relying on global env. Move the functions
to int{32,64}_helper.c.

Reviewed-by: Richard Henderson <>...
063c3675 10/26/2011 08:18 pm Blue Swirl

Sparc: avoid AREG0 for CWP and PSTATE helpers

Make CWP and PSTATE helpers take a parameter for CPUState instead
of relying on global env. Remove wrapper functions.

Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
f37e2a6b 10/25/2011 10:30 pm Stefan Weil

target-sparc: Fix order of function parameters

The MinGW-w64 gcc complains about wrong parameters for
gen_helper_fpadd16_s and three other functions.

gen_helper_fpadd16_s is declared like this (hidden in lots of macros):

static inline void
gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,...
2ffd9176 10/23/2011 06:09 pm Blue Swirl

Sparc: avoid AREG0 for lazy condition code helpers

Make lazy condition code helpers take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
2e2f4ade 10/23/2011 06:09 pm Blue Swirl

Sparc: avoid AREG0 for float and VIS ops

Make floating point and VIS ops take a parameter for CPUState instead
of relying on global env.

Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
bc265319 10/23/2011 06:08 pm Blue Swirl

Sparc: avoid AREG0 for raise_exception and helper_debug

Make raise_exception() and helper_debug() take a parameter for
CPUState instead of relying on global env. Move the functions
to helper.c.

Reviewed-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
548f66db 08/06/2011 06:08 pm Artyom Tarasenko

Fix handling of conditional branches in delay slot of a conditional branch

Check whether dc->npc is dynamic before using its value for branch.

Signed-off-by: Artyom Tarasenko <>
Signed-off-by: Blue Swirl <>
ccb57e0e 07/30/2011 11:26 am Tsuneo Saito

SPARC64: fix fnor* and fnand*

Fix the problem that result values are not assigned to the destination
registers.

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
638737ad 07/30/2011 11:26 am Tsuneo Saito

SPARC64: implement %fprs dirty bits

Implement %fprs.DU/DL bits.
The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31
and %f32-63 respectively.

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
b7d69dc2 07/20/2011 11:44 pm Tsuneo Saito

SPARC64: add missing break on fmovdcc

"break" is missing on V9 fmovdcc (%icc).

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
afcb7375 07/20/2011 11:44 pm Tsuneo Saito

SPARC64: fix VIS1 SIMD signed compare instructions

The destination registers of SIMD signed compare instructions
(fcmp*<16|32>) are not FP registers but general purpose r registers.
Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.

Signed-off-by: Tsuneo Saito <>...
f838e2c5 07/14/2011 08:30 pm Blue Swirl

Sparc: fix FPU and AM enable checks for translation

Translation used incorrectly CPUState fields directly to check
for FPU enable state and 32 bit address masking on Sparc64.

Fix by using TB flags instead.

Signed-off-by: Blue Swirl <>
5f06b547 07/14/2011 06:36 pm Tsuneo Saito

SPARC64: fp_disabled checks on stfa/stdfa/stqfa

stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
e1ef36c4 07/14/2011 06:36 pm Tsuneo Saito

SPARC64: Implement stfa/stdfa/stqfa instrcutions properly

This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
8872eb4f 07/14/2011 06:35 pm Tsuneo Saito

SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa

ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.

Signed-off-by: Tsuneo Saito <>
Signed-off-by: Blue Swirl <>
8e91ed30 07/02/2011 12:28 am Artyom Tarasenko

fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx

udivx and sdvix don't modify condition flags, so they shall not
overwrite cpu_cc_*

Signed-off-by: Artyom Tarasenko <>
Signed-off-by: Blue Swirl <>
2b41f10e 06/26/2011 09:25 pm Blue Swirl

Remove exec-all.h include directives

Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <>
dcfd14b3 05/22/2011 01:47 pm Blue Swirl

Delete unused tb_invalidate_page_range

tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful....
86f1f2ae 05/14/2011 10:30 am Blue Swirl

sparc64: fix incorrect BPcc target sign extension

Fix wrong number of bits used when sign extending the branch offset of BPcc
instructions.

Reported-by: Artyom Tarasenko <>
Signed-off-by: Blue Swirl <>
a2589e5c 05/14/2011 10:30 am Blue Swirl

sparc64: fix wrpstate and wrtl on delay slot

Use TCG local to work around TCG register flush due to a branch.

Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.

Signed-off-by: Blue Swirl <>
e87b7cb0 04/20/2011 11:33 am Stefan Weil

Remove unused function parameters from gen_pc_load and rename the function

Function gen_pc_load was introduced in commit
d2856f1ad4c259e5766847c49acbb4e390731bd4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c....
4b4a72e5 04/10/2011 01:45 am Stefan Weil

Fix conversions from pointer to tcg_target_long

tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where...
b04d9890 01/24/2011 10:54 pm Fabien Chouteau

SPARC: Emulation of Leon3

Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).

Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager....
4a2ba232 01/24/2011 10:54 pm Fabien Chouteau

SPARC: Add asr17 register support

This register is activated by CPU_FEATURE_ASR17 in the feature field.

Signed-off-by: Fabien Chouteau <>
Signed-off-by: Blue Swirl <>
0fcec41e 12/28/2010 08:44 pm Aurelien Jarno

target-sparc: fix udiv(cc) and sdiv(cc)

Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on
a Debian Etch image. The commit itself is fine, but it triggers a bug
due to wrong computation of flags for udiv(cc) and sdiv(cc).

This patch only compute cc_src2 for the cc version of udiv/sdiv. It...
fb170183 06/02/2010 11:08 pm Igor V. Kovalenko

sparc64: fix umul and smul insns

- truncate and sign or zero extend operands before multiplication
- factor out common code to gen_op_multiply() with parameter to sign/zero extend
- call gen_op_multiply from gen_op_umul and gen_op_smul

Signed-off-by: Igor V. Kovalenko <>...
fe987e23 06/02/2010 11:05 pm Igor V. Kovalenko

sparc64: fix ldxfsr insn

- rearrange code to break from switch when appropriate
- allow deprecated ldfsr insn

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>
1295001c 06/02/2010 11:03 pm Igor V. Kovalenko

sparc64: fix missing address masking v1

- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites...
9fd1ae3a 05/22/2010 03:51 pm Igor V. Kovalenko

sparc64: fix mmu context at trap levels above zero

- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed...
2aae2b8e 05/22/2010 03:48 pm Igor V. Kovalenko

sparc64: fix pstate privilege bits

- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well...
70c48285 05/20/2010 10:58 pm Richard Henderson

target-sparc: Inline some generation of carry for ADDX/SUBX.

Computing carry is trivial for some inputs. By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern)....
275ea265 05/09/2010 06:40 pm Blue Swirl

sparc: lazy C flag calculation

Calculate only the carry flag for ADDX/SUBX instead of full
set of flags.

Thanks to Igor Kovalenko for spotting a bug with an earlier
version.

Signed-off-by: Blue Swirl <>
060718c1 04/26/2010 08:23 pm Richard Henderson

target-sparc: Fix -singlestep.

Single-stepping was not properly updating npc, resulting in some
instructions being executed twice. In addition, we were emitting
dead code at the end of the TB.

Fix both by teaching gen_goto_tb to avoid goto_tb for single-step...
6ad6135d 04/18/2010 05:22 pm Blue Swirl

Fix harmless if statements with empty body, spotted by clang

These clang errors are harmless but worth fixing:
CC ppc-softmmu/usb-ohci.o
/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body]
ohci->ctrl_head, ohci->ctrl_cur);...
42a8aa83 04/17/2010 07:25 pm Richard Henderson

target-sparc: Free instruction temporaries.

Rather than creating new temporaries for constants, use the
ones created in disas_sparc_insn. Remember the temps created
there so that they can be freed at the end of the function.

Profile data collected by TCG while booting sparc-test kernel:...
cca1d527 04/17/2010 07:25 pm Blue Swirl

Sparc: fix PC/NPC during FPU traps

All FPU instructions can trap, so save PC/NPC state before
executing them.

Signed-off-by: Blue Swirl <>
d7da2a10 04/11/2010 10:47 pm Blue Swirl

Sparc: fix exceptions in delay slot

Fix a case where an exception happens with the
instruction in the delay slot.

Recovery of branch condition in the exception handling
code was not converted to TCG. Because the condition
was bogus, wrong NPC could be selected from the two...
1a7ff922 04/08/2010 10:34 pm Paolo Bonzini

remove TARGET_* defines from translate-all.c

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>
bc57c114 02/25/2010 08:26 pm Stefan Weil

target-sparc: fix --enable-debug build for 64 bit host

b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixed
the compilation for 32 bit hosts, but introduced
a new error for 64 bit hosts:

tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.

Signed-off-by: Stefan Weil <>...
b551ec04 02/20/2010 01:09 pm Jay Foad

target-sparc: fix --enable-debug build

Use 32-bit arithmetic for the address offset calculation to fix a
build failure on 32-bit hosts.

Signed-off-by: Jay Foad <>
Signed-off-by: Blue Swirl <>
1fae7b70 01/08/2010 07:14 pm Igor V. Kovalenko

sparc64: use helper_wrpil to check pending irq on write

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>
01b5d4e5 09/23/2009 11:00 pm Igor V. Kovalenko

sparc64-8bit-asi

Sparc64 alternate space load/store helpers expect 8 bit ASI value,
while wrasi implementation sign-extends ASI operand causing
for example 0x80 to appear as 0xFFFFFF80. Resulting value falls
out of switch in helpers and causes obscure load/store faults....
72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
c27e2752 08/22/2009 02:46 pm Blue Swirl

Sparc32/64: fix jmpl followed by branch

Fix a case where 'jmpl' instruction followed by a branch instruction was
handled incorrectly.

Signed-off-by: Blue Swirl <>
cfa90513 08/15/2009 07:52 pm Blue Swirl

Fix desynchronization of condition code state when a memory access traps

Signed-off-by: Blue Swirl <>
8194f35a 08/04/2009 11:22 pm Igor Kovalenko

Sparc64: replace tsptr with helper routine

tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding...
14ed7adc 07/31/2009 09:48 am Igor Kovalenko

sparc64 flush pending conditional evaluations before exposing cpu state

If translation block is interrupted by e.g. mmu exception
we need to compute conditional flags for inclusion into
saved cpu state. Otherwise after return from trap
conditional instructions would use stale psr/xcc data....
8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>
25517f99 06/06/2009 04:54 am Paul Brook

Use correct type for SPARC cpu_cc_op

Signed-off-by: Paul Brook <>
d084469c 05/10/2009 10:43 am Blue Swirl

Convert mulscc

Signed-off-by: Blue Swirl <>
6c78ea32 05/10/2009 10:42 am Blue Swirl

Convert udiv/sdiv

Signed-off-by: Blue Swirl <>
3b2d1e92 05/10/2009 10:38 am Blue Swirl

Convert tagged ops

Signed-off-by: Blue Swirl <>
38482a77 05/10/2009 10:38 am Blue Swirl

Convert logical operations and umul/smul

Signed-off-by: Blue Swirl <>
d4b0d468 05/10/2009 10:38 am Blue Swirl

Convert sub

Signed-off-by: Blue Swirl <>
2ca1d92b 05/10/2009 10:38 am Blue Swirl

Convert subx

Signed-off-by: Blue Swirl <>
789c91ef 05/10/2009 10:19 am Blue Swirl

Convert addx

Signed-off-by: Blue Swirl <>
bdf9f35d 05/10/2009 10:19 am Blue Swirl

Convert add

Signed-off-by: Blue Swirl <>
8393617c 05/10/2009 10:19 am Blue Swirl

Use dynamical computation for condition codes

Signed-off-by: Blue Swirl <>
719f66a7 05/03/2009 09:51 pm Blue Swirl

Optimize cmp x, 0 case

Signed-off-by: Blue Swirl <>
dc1a6971 05/03/2009 09:51 pm Blue Swirl

Reindent

Signed-off-by: Blue Swirl <>
b89e94af 05/02/2009 11:19 pm Blue Swirl

Improve instruction name comments for easier searching

Signed-off-by: Blue Swirl <>
41d72852 05/02/2009 10:14 pm Blue Swirl

Optimize operations with immediate parameters
67526b20 05/02/2009 09:58 pm Blue Swirl

Fix Sparc64 sign extension problems

Signed-off-by: Blue Swirl <>
1b530a6d 04/05/2009 11:08 pm aurel32

Add new command line option -singlestep for tcg single stepping.

This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode....
d78f3995 03/16/2009 06:33 pm blueswir1

Delete some unused macros detected with -Wp,-Wunused-macros use

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
8fec2b8c 01/16/2009 12:36 am aliguori

global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)

These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...
93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...
fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...
c0ce998e 11/26/2008 12:13 am aliguori

Use sys-queue.h for break/watchpoint managment (Jan Kiszka)

This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <>...
a1d1bb31 11/18/2008 10:07 pm aliguori

Refactor and enhance break/watchpoint API (Jan Kiszka)

This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists....
a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2576d836 11/09/2008 09:52 pm blueswir1

Use TCG not op

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5663 c046a42c-6fe2-441c-8c8c-71466251a162
81b5b816 11/09/2008 09:50 pm blueswir1

Use andc, orc, nor and nand
Also fix which argument gets negated in fandnot12 and fornot12

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
527067d8 11/01/2008 03:44 pm blueswir1

Fix TCGv size mismatches

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5593 c046a42c-6fe2-441c-8c8c-71466251a162
b158a785 09/26/2008 09:05 pm blueswir1

Implement UA2005 hypervisor traps

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
9d926598 09/22/2008 10:50 pm blueswir1

Add software and timer interrupt support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
ab508019 09/21/2008 09:43 pm blueswir1

Use the new concat_tl_i64 op for std and stda

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5283 c046a42c-6fe2-441c-8c8c-71466251a162
a7ec4229 09/21/2008 05:49 pm blueswir1

Use the new concat_i32_i64 op for std and stda

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
72ccba79 09/13/2008 08:20 pm blueswir1

Fix mulscc with high bits set in either src1 or src2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162
5068cbd9 09/11/2008 07:01 pm blueswir1

Write zeros to high bits of y, based on patch by Vince Weaver

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
d84763bc 09/10/2008 11:09 pm blueswir1

Convert rest of ops using float32 to TCG, remove FT0 and FT1

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
c5d04e99 09/10/2008 11:00 pm blueswir1

Partially convert float128 conversion ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162