target-arm: Add utility function for checking AA32/64 state of an EL
There are various situations where we need to behave differentlydepending on whether a given exception level is in AArch64 orAArch32 state. The state of the current exception level is stored...
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation...
target-arm: A64: Implement WFI
Implement the WFI instruction for A64; this just involves wiringup the instruction, and adding a gen_a64_set_pc_im() which wasaccidentally omitted from the A64 decoder top loop.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need tocare about whether EL1 is AArch32 or AArch64, we should storethe interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIFin AArch64) in one place consistently regardless of EL1's mode....
target-arm: A64: Implement MSR (immediate) instructions
Implement the MSR (immediate) instructions, which can update thePSTATE SP and DAIF fields.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64CPACR is defined to have a lot of RES0 bits, but sincethe architecture defines that RES0 bits may be implementedas reads-as-written and we know that a v8 CPU will have...
target-arm: Implement AArch64 generic timers
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement AArch64 ID and feature registers
Implement the AArch64-specific ID and feature registers. Althoughmany of these are currently not used by the architecture (and soalways zero for all implementations), we define the full set offields in the ARMCPU struct for symmetry....
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
In AArch64 the breakpoint and watchpoint registers are mandatory, so thekernel always accesses them on bootup. Implement dummy versions, whichread as written but have no actual effect....
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Define a dummy version of the AArch64 OSLAR_EL1 system registerwhich just ignores writes. Linux will always write to this (itis the OS lock used for debugging), but we don't support debug.
target-arm: Get MMU index information correct for A64 code
Emit the correct MMU index information for loads and stores fromA64 code, rather than hardwiring it to "always kernel mode",by storing the exception level in the TB flags, and makecpu_mmu_index() return the right answer when the CPU is in...
target-arm: Implement AArch64 TCR_EL1
Implement the AArch64 TCR_EL1, which is the 64 bit view ofthe AArch32 TTBCR. (The uses of the bits in the register arecompletely different, but in any given situation the CPU willalways interpret them one way or the other. In fact for QEMU EL1...
target-arm: Implement AArch64 VBAR_EL1
Implement the A64 view of the VBAR system register.
target-arm: Implement AArch64 TTBR*
Implement the AArch64 TTBR* registers. For v7 these were already 64 bitsto handle LPAE, but implemented as two separate uint32_t fields.Combine them into a single uint64_t which can be used for all purposes.Since this requires touching every use, take the opportunity to rename...
target-arm: Implement AArch64 MPIDR
Implement the AArch64 MPIDR system register.
target-arm: Implement AArch64 TLB invalidate ops
Implement the AArch64 TLB invalidate operations. This isthe full set of TLBI ops defined for a CPU which doesn'timplement EL2 or EL3.
target-arm: Implement AArch64 dummy MDSCR_EL1
We don't support letting the guest do debug, but Linux prods themonitor debug system control register anyway, so implement a dummyRAZ/WI version.
target-arm: Implement AArch64 memory attribute registers
Implement the AArch64 memory attribute registers. Since QEMU doesn'tmodel caches it does not need to care about memory attributes at all,and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR...
target-arm: Implement AArch64 SCTLR_EL1
Implement the AArch64 view of the system control register SCTLR_EL1.
target-arm: Implement AArch64 CurrentEL sysreg
Implement the CurrentEL sysreg.
target-arm: Implement AArch64 MIDR_EL1
Implement the AArch64 view of the MIDR system register(for AArch64 it is a simple constant, unlike the complicatedmess that TI925 imposes on the 32-bit view).
target-arm: Implement AArch64 cache invalidate/clean ops
Implement all the AArch64 cache invalidate and clean ops(which are all NOPs since QEMU doesn't emulate the cache).The only remaining unimplemented cache op is DC ZVA.
target-arm: Fix raw read and write functions on AArch64 registers
The raw read and write functions were using the ARM_CP_64BIT flag inri->type to determine whether to treat the register's state field asuint32_t or uint64_t; however AArch64 register info structs don't use...
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)visible to AArch64. These are mostly simple 64-bit extensions of theexisting 32 bit system registers and so can share reginfo definitions....
arm: vgic device control api support
Support creating the ARM vgic device through the device control API andsetting the base address for the distributor and cpu interfaces in KVMVMs using this API.
Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be...
target-arm: Load correct access bits from ARMv5 level 2 page table descriptors
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split intofour subpages, each of which can have different access permission settings,which are specified by four two-bit fields in the l2 descriptor. A...
target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops
Correct some obviously nonsensical bit manipulation spotted by Coveritywhen constructing the short-form PAR value for ATS operations.
target-arm: A64: Implement the wide 3-reg-different operations
Implement the wide three-reg-different operations:SADDW, UADDW, SSUBW and USUBW.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Implement narrowing three-reg-diff operations
Implement the narrowing three-reg-diff operations: ADDHN,RADDHN, SUBHN and RSUBHN.
target-arm: A64: Implement unprivileged load/store
Implement the unprivileged load and store instructions.
target-arm: A64: Implement store-exclusive for system mode
System mode store-exclusive use a different code path to usermode ones;implement this missing code, in a similar way to the 32 bit version.
target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
The opcode switch in disas_simd_three_reg_diff() is missing thecustomary comments indicating which cases correspond to whichinstructions. Add them.
target-arm: A64: Add most remaining three-reg-diff widening ops
Add the remainder of the 64x64->128 operations in the three-reg-diffcategory except for PMULL, PMULL2.
target-arm: Drop success/fail return from cpreg read and write functions
All cpreg read and write functions now return 0, so we can clean uptheir prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to...
target-arm: Remove unnecessary code now read/write fns can't fail
Now that cpreg read and write functions can't fail and throw anexception, we can remove the code from the translator that synchronisesthe guest PC in case an exception is thrown.
target-arm: Remove failure status return from read/write_raw_cp_reg
The read_raw_cp_reg and write_raw_cp_reg functions can now neverfail (in fact they should never have failed previously unlessthere was a bug in a reginfo that meant no raw accessor was...
target-arm: Fix incorrect type for value argument to write_raw_cp_reg
The write_raw_cp_reg's value argument should be a uint64_t, sincethat's what all its callers hand it and what all the functions itcalls take. A (harmless) typo meant we were accidentally declaring...
target-arm: Convert generic timer reginfo to accessfn
Convert the reginfo structs for the generic timer registersto use access functions rather than returning EXCP_UDEF fromtheir read handlers. In some cases this allows us to removea read handler completely....
target-arm: Convert miscellaneous reginfo structs to accessfn
Convert the remaining miscellaneous cases of reginfo read/writefunctions returning EXCP_UDEF to use an accessfn instead:TEEHBR, and the ATS address-translation operations.
target-arm: Log bad system register accesses with LOG_UNIMP
Log guest attempts to access unimplemented system registers viathe LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bitinstruction sets). This is particularly useful for debuggingproblems where the guest is trying to use a system register that...
target-arm: Stop underdecoding ARM946 PRBS registers
The ARM946 has 8 PRBS (protection region base and size) registers.Currently we implement these with a CP_ANY reginfo; however thisunderdecodes (since there are 16 possible values of CRm but only8 registers) and we catch the invalid values in the read and...
target-arm: Split cpreg access checks out from read/write functions
Several of the system registers handled via the ARMCPRegInfomechanism have access trap control bits controlling whether theregisters are accessible to lower privilege levels. Replacethe existing mechanism (allowing the read and write functions...
target-arm: Convert performance monitor reginfo to accessfn
Convert the performance monitor reginfo definitions to usean accessfn rather than returning EXCP_UDEF from read andwrite functions. This also allows us to fix a couple of XXXcases where we weren't imposing the access restrictions on...
target-arm: Define names for SCTLR bits
The SCTLR is full of bits for enabling or disabling various things, and sothere are many places in the code which check if certain bits are set.Define some named constants for the SCTLR bits so these checks are easier...
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guardthe use of them in check_ap() so that we don't get incorrect results...
target-arm: Remove unused ARMCPUState sr substruct
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and isa hangover from the original separate system register implementation usedby the SuSE linux-user-mode-only AArch64 target.
target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operationsFADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use thecode which was previously handling only integer pairwise operations,and push the integer-specific decode and handling of unallocated...
target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-sameand scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,FACGT, FMLA and FMLS.
target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*constant to include all the ones currently supported by the kernelheaders we are using.
target-arm: A64: Implement long vector x indexed insns
Implement the 'long' operations in the vector x indexedelement category.
target-arm: A64: Implement SIMD scalar indexed instructions
Implement the SIMD scalar indexed instructions. The encodinghere is nearly identical to the vector indexed grouping, sowe combine the two.
target-arm: A64: Implement scalar three different instructions
Implement the scalar three different instruction group:it only has three instructions in it.
target-arm: A64: Implement SIMD FP compare and set insns
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers orsome new helpers for the 64bit double cases. Most of the code paths are...
target-arm: A64: Implement plain vector SIMD indexed element insns
Implement all the SIMD vector x indexed element instructionsin the subcategory which are not 'long' ops.
exec: Make stl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make ldl_*_phys input an AddressSpace
disas: Implement disassembly output for A64
Use libvixl to implement disassembly output in debuglogs for A64, for use with both AArch64 hosts and targets.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: * added support for target disassembly...
target-arm: A64: Implement 2-register misc compares, ABS, NEG
Implement the simple 2-register-misc operations we can sharewith the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,SQNEG also fall into this category, but aren't implemented inthe scalar-2-register case yet either.)...
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions.
target-arm: A64: Add narrowing 2-reg-misc instructions
Add the narrowing integer instructions in the 2-reg-misc class.
target-arm: A64: Add 2-reg-misc REV* instructions
Add the byte-reverse operations REV64, REV32 and REV16 from thetwo-reg-misc group.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.
target-arm: Add support for AArch32 64bit VCVTB and VCVTT
Add support for the AArch32 floating-point half-precision to double-precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>[PMM: fixed a minor missing-braces style issue]...
target-arm: A64: Implement scalar pairwise ops
Implement the instructions in the scalar pairwise group (C3.6.8).
target-arm: A64: Implement remaining integer scalar-3-same insns
Implement the remaining integer instructions in the scalar-three-reg-samegroup: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,SQDMULH, SQRDMULH.
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Implement the simple 64 bit integer operations from the SIMDscalar 2-register misc group (C3.6.12): the comparisons againstzero, plus ABS and NEG.
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
Add a skeleton decode for the SIMD 2-reg misc group.
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Implement the SIMD 3-reg-same instructions SQADD, UQADD,SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,SQRSHL, UQRSHL; these are all simple calls to existingNeon helpers. We also enable SSHL, USHL, SRSHL and URSHL...
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Implement the SIMD 3-reg-same instructions where the size == 3 caseis reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,...
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Implement the pairwise integer operations in the 3-reg-same SIMD group:ADDP, SMAXP, SMINP, UMAXP and UMINP.
target-arm: A64: Add top level decode for SIMD 3-same group
Add top level decode for the A64 SIMD three regs same group(C3.6.16), splitting it into the pairwise, logical, float andinteger subgroups.
target-arm: A64: Add logic ops from SIMD 3 same group
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,BIT and BIF) from the SIMD 3 register same group (C3.6.16).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add integer ops from SIMD 3-same group
Add some of the integer operations in the SIMD 3-same group:specifically, the comparisons, addition and subtraction.
target-arm: A64: Add simple SIMD 3-same floating point ops
Implement a simple subset of the SIMD 3-same floating pointoperations. This includes a common helper function used for bothscalar and vector ops; FABD is the only currently implementedshared op....
target-arm: A64: Add SIMD shift by immediate
This implements a subset of the AdvSIMD shift operations (namely all thenone saturating or narrowing ones). The actual shift generation codeitself is common for both the scalar and vector cases but wrapped with...
target-arm: A64: Add SIMD three-different multiply accumulate insns
Add support for the multiply-accumulate instructions from theSIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts...
target-arm: A64: Add SIMD three-different ABDL instructions
Implement the absolute-difference instructions in the SIMDthree-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,SABDL2, UABDL, UABDL2.
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Implement the add, sub and compare ops from the SIMD "scalar three same" group.
target-arm: Add set_neon_rmode helper
This helper sets the rounding mode in the standard_fp_status word toallow NEON instructions to modify the rounding mode whilst using thestandard FPSCR values for everything else.
Signed-off-by: Will Newton <will.newton@linaro.org>...
target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTPVRINTM and VRINTZ instructions.
Signed-off-by: Will Newton <will.newton@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTPand VCVTM instructions.
target-arm: Add support for AArch32 FP VRINTR
Add support for the AArch32 floating-point VRINTR instruction.
target-arm: Add support for AArch32 FP VRINTZ
Add support for the AArch32 floating-point VRINTZ instruction.
target-arm: Add support for AArch32 FP VRINTX
Add support for the AArch32 floating-point VRINTX instruction.
target-arm: Add support for AArch32 SIMD VRINTX
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton <will.newton@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Move arm_rmode_to_sf to a shared location.
This function will be needed for AArch32 ARMv8 support, so move it tohelper.c where it can be used by both targets. Also moves the code outof line, but as it is quite a large function I don't believe this...
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTMinstructions.
target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
ARM: Convert MIDR to a property
Convert the MIDR register to a property. This allows boards to later seta custom MIDR value. This has been done in such a way to maintaincompatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>...
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
target-arm: A64: Add SIMD ld/st multiple
This adds support support for the SIMD load/storemultiple category of instructions.
This also brings in a couple of helper functions for manipulatingsections of the SIMD registers:
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions.
target-arm: A64: Add decode skeleton for SIMD data processing insns
Add decode skeleton and function placeholders for all the SIMD dataprocessing instructions. Due to the complexity of this part of thetable the normal extract and switch approach gets very messy very...
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).