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1 | 9fdf0c29 | David Gibson | /*
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2 | 9fdf0c29 | David Gibson | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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3 | 9fdf0c29 | David Gibson | *
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4 | 9fdf0c29 | David Gibson | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 9fdf0c29 | David Gibson | * Copyright (c) 2007 Jocelyn Mayer
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6 | 9fdf0c29 | David Gibson | * Copyright (c) 2010 David Gibson, IBM Corporation.
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7 | 9fdf0c29 | David Gibson | *
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8 | 9fdf0c29 | David Gibson | * Permission is hereby granted, free of charge, to any person obtaining a copy
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9 | 9fdf0c29 | David Gibson | * of this software and associated documentation files (the "Software"), to deal
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10 | 9fdf0c29 | David Gibson | * in the Software without restriction, including without limitation the rights
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11 | 9fdf0c29 | David Gibson | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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12 | 9fdf0c29 | David Gibson | * copies of the Software, and to permit persons to whom the Software is
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13 | 9fdf0c29 | David Gibson | * furnished to do so, subject to the following conditions:
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14 | 9fdf0c29 | David Gibson | *
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15 | 9fdf0c29 | David Gibson | * The above copyright notice and this permission notice shall be included in
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16 | 9fdf0c29 | David Gibson | * all copies or substantial portions of the Software.
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17 | 9fdf0c29 | David Gibson | *
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18 | 9fdf0c29 | David Gibson | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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19 | 9fdf0c29 | David Gibson | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 | 9fdf0c29 | David Gibson | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 | 9fdf0c29 | David Gibson | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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22 | 9fdf0c29 | David Gibson | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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23 | 9fdf0c29 | David Gibson | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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24 | 9fdf0c29 | David Gibson | * THE SOFTWARE.
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25 | 9fdf0c29 | David Gibson | *
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26 | 9fdf0c29 | David Gibson | */
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27 | 9fdf0c29 | David Gibson | #include "sysemu.h" |
28 | 9fdf0c29 | David Gibson | #include "hw.h" |
29 | 9fdf0c29 | David Gibson | #include "elf.h" |
30 | 8d90ad90 | David Gibson | #include "net.h" |
31 | 6e270446 | Ben Herrenschmidt | #include "blockdev.h" |
32 | 9fdf0c29 | David Gibson | |
33 | 9fdf0c29 | David Gibson | #include "hw/boards.h" |
34 | 9fdf0c29 | David Gibson | #include "hw/ppc.h" |
35 | 9fdf0c29 | David Gibson | #include "hw/loader.h" |
36 | 9fdf0c29 | David Gibson | |
37 | 9fdf0c29 | David Gibson | #include "hw/spapr.h" |
38 | 4040ab72 | David Gibson | #include "hw/spapr_vio.h" |
39 | b5cec4c5 | David Gibson | #include "hw/xics.h" |
40 | 9fdf0c29 | David Gibson | |
41 | f61b4bed | Alexander Graf | #include "kvm.h" |
42 | f61b4bed | Alexander Graf | #include "kvm_ppc.h" |
43 | f61b4bed | Alexander Graf | |
44 | 9fdf0c29 | David Gibson | #include <libfdt.h> |
45 | 9fdf0c29 | David Gibson | |
46 | 9fdf0c29 | David Gibson | #define KERNEL_LOAD_ADDR 0x00000000 |
47 | 9fdf0c29 | David Gibson | #define INITRD_LOAD_ADDR 0x02800000 |
48 | 9fdf0c29 | David Gibson | #define FDT_MAX_SIZE 0x10000 |
49 | 39ac8455 | David Gibson | #define RTAS_MAX_SIZE 0x10000 |
50 | a9f8ad8f | David Gibson | #define FW_MAX_SIZE 0x400000 |
51 | a9f8ad8f | David Gibson | #define FW_FILE_NAME "slof.bin" |
52 | a9f8ad8f | David Gibson | |
53 | a9f8ad8f | David Gibson | #define MIN_RAM_SLOF 512UL |
54 | 9fdf0c29 | David Gibson | |
55 | 9fdf0c29 | David Gibson | #define TIMEBASE_FREQ 512000000ULL |
56 | 9fdf0c29 | David Gibson | |
57 | 41019fec | Anton Blanchard | #define MAX_CPUS 256 |
58 | b5cec4c5 | David Gibson | #define XICS_IRQS 1024 |
59 | 9fdf0c29 | David Gibson | |
60 | 0c103f8e | David Gibson | #define PHANDLE_XICP 0x00001111 |
61 | 0c103f8e | David Gibson | |
62 | 9fdf0c29 | David Gibson | sPAPREnvironment *spapr; |
63 | 9fdf0c29 | David Gibson | |
64 | e6c866d4 | David Gibson | qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num) |
65 | e6c866d4 | David Gibson | { |
66 | e6c866d4 | David Gibson | uint32_t irq; |
67 | e6c866d4 | David Gibson | qemu_irq qirq; |
68 | e6c866d4 | David Gibson | |
69 | e6c866d4 | David Gibson | if (hint) {
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70 | e6c866d4 | David Gibson | irq = hint; |
71 | e6c866d4 | David Gibson | /* FIXME: we should probably check for collisions somehow */
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72 | e6c866d4 | David Gibson | } else {
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73 | e6c866d4 | David Gibson | irq = spapr->next_irq++; |
74 | e6c866d4 | David Gibson | } |
75 | e6c866d4 | David Gibson | |
76 | e6c866d4 | David Gibson | qirq = xics_find_qirq(spapr->icp, irq); |
77 | e6c866d4 | David Gibson | if (!qirq) {
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78 | e6c866d4 | David Gibson | return NULL; |
79 | e6c866d4 | David Gibson | } |
80 | e6c866d4 | David Gibson | |
81 | e6c866d4 | David Gibson | if (irq_num) {
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82 | e6c866d4 | David Gibson | *irq_num = irq; |
83 | e6c866d4 | David Gibson | } |
84 | e6c866d4 | David Gibson | |
85 | e6c866d4 | David Gibson | return qirq;
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86 | e6c866d4 | David Gibson | } |
87 | e6c866d4 | David Gibson | |
88 | a3467baa | David Gibson | static void *spapr_create_fdt_skel(const char *cpu_model, |
89 | a3467baa | David Gibson | target_phys_addr_t initrd_base, |
90 | a3467baa | David Gibson | target_phys_addr_t initrd_size, |
91 | a3467baa | David Gibson | const char *boot_device, |
92 | a3467baa | David Gibson | const char *kernel_cmdline, |
93 | a3467baa | David Gibson | long hash_shift)
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94 | 9fdf0c29 | David Gibson | { |
95 | 9fdf0c29 | David Gibson | void *fdt;
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96 | c7a5c0c9 | David Gibson | CPUState *env; |
97 | a3467baa | David Gibson | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) };
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98 | 9fdf0c29 | David Gibson | uint32_t start_prop = cpu_to_be32(initrd_base); |
99 | 9fdf0c29 | David Gibson | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
100 | f43e3525 | David Gibson | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
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101 | ee86dfee | David Gibson | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
102 | a3d0abae | David Gibson | "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
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103 | b5cec4c5 | David Gibson | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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104 | 9fdf0c29 | David Gibson | int i;
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105 | 9fdf0c29 | David Gibson | char *modelname;
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106 | 9fdf0c29 | David Gibson | |
107 | 9fdf0c29 | David Gibson | #define _FDT(exp) \
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108 | 9fdf0c29 | David Gibson | do { \
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109 | 9fdf0c29 | David Gibson | int ret = (exp); \
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110 | 9fdf0c29 | David Gibson | if (ret < 0) { \ |
111 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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112 | 9fdf0c29 | David Gibson | #exp, fdt_strerror(ret)); \
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113 | 9fdf0c29 | David Gibson | exit(1); \
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114 | 9fdf0c29 | David Gibson | } \ |
115 | 9fdf0c29 | David Gibson | } while (0) |
116 | 9fdf0c29 | David Gibson | |
117 | 7267c094 | Anthony Liguori | fdt = g_malloc0(FDT_MAX_SIZE); |
118 | 9fdf0c29 | David Gibson | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
119 | 9fdf0c29 | David Gibson | |
120 | 9fdf0c29 | David Gibson | _FDT((fdt_finish_reservemap(fdt))); |
121 | 9fdf0c29 | David Gibson | |
122 | 9fdf0c29 | David Gibson | /* Root node */
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123 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "")));
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124 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
125 | 5d73dd66 | David Gibson | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
126 | 9fdf0c29 | David Gibson | |
127 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
128 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
129 | 9fdf0c29 | David Gibson | |
130 | 9fdf0c29 | David Gibson | /* /chosen */
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131 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "chosen")));
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132 | 9fdf0c29 | David Gibson | |
133 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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134 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-start",
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135 | 9fdf0c29 | David Gibson | &start_prop, sizeof(start_prop))));
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136 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-end",
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137 | 9fdf0c29 | David Gibson | &end_prop, sizeof(end_prop))));
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138 | a9f8ad8f | David Gibson | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
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139 | 9fdf0c29 | David Gibson | |
140 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
141 | 9fdf0c29 | David Gibson | |
142 | 9fdf0c29 | David Gibson | /* memory node */
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143 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "memory@0")));
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144 | 9fdf0c29 | David Gibson | |
145 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "memory"))); |
146 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "reg",
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147 | 9fdf0c29 | David Gibson | mem_reg_property, sizeof(mem_reg_property))));
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148 | 9fdf0c29 | David Gibson | |
149 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
150 | 9fdf0c29 | David Gibson | |
151 | 9fdf0c29 | David Gibson | /* cpus */
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152 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "cpus")));
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153 | 9fdf0c29 | David Gibson | |
154 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
155 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
156 | 9fdf0c29 | David Gibson | |
157 | 7267c094 | Anthony Liguori | modelname = g_strdup(cpu_model); |
158 | 9fdf0c29 | David Gibson | |
159 | 9fdf0c29 | David Gibson | for (i = 0; i < strlen(modelname); i++) { |
160 | 9fdf0c29 | David Gibson | modelname[i] = toupper(modelname[i]); |
161 | 9fdf0c29 | David Gibson | } |
162 | 9fdf0c29 | David Gibson | |
163 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
164 | c7a5c0c9 | David Gibson | int index = env->cpu_index;
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165 | c7a5c0c9 | David Gibson | uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */ |
166 | 9fdf0c29 | David Gibson | char *nodename;
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167 | 9fdf0c29 | David Gibson | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
168 | 9fdf0c29 | David Gibson | 0xffffffff, 0xffffffff}; |
169 | 0a8b2938 | Alexander Graf | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; |
170 | 0a8b2938 | Alexander Graf | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
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171 | 9fdf0c29 | David Gibson | |
172 | c7a5c0c9 | David Gibson | if (asprintf(&nodename, "%s@%x", modelname, index) < 0) { |
173 | 9fdf0c29 | David Gibson | fprintf(stderr, "Allocation failure\n");
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174 | 9fdf0c29 | David Gibson | exit(1);
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175 | 9fdf0c29 | David Gibson | } |
176 | 9fdf0c29 | David Gibson | |
177 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, nodename))); |
178 | 9fdf0c29 | David Gibson | |
179 | 9fdf0c29 | David Gibson | free(nodename); |
180 | 9fdf0c29 | David Gibson | |
181 | c7a5c0c9 | David Gibson | _FDT((fdt_property_cell(fdt, "reg", index)));
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182 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
183 | 9fdf0c29 | David Gibson | |
184 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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185 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "dcache-block-size",
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186 | 9fdf0c29 | David Gibson | env->dcache_line_size))); |
187 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "icache-block-size",
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188 | 9fdf0c29 | David Gibson | env->icache_line_size))); |
189 | 0a8b2938 | Alexander Graf | _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
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190 | 0a8b2938 | Alexander Graf | _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
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191 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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192 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,pft-size",
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193 | f43e3525 | David Gibson | pft_size_prop, sizeof(pft_size_prop))));
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194 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "status", "okay"))); |
195 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
196 | c7a5c0c9 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index)));
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197 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
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198 | b5cec4c5 | David Gibson | gserver_prop, sizeof(gserver_prop))));
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199 | 9fdf0c29 | David Gibson | |
200 | c7a5c0c9 | David Gibson | if (env->mmu_model & POWERPC_MMU_1TSEG) {
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201 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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202 | 9fdf0c29 | David Gibson | segs, sizeof(segs))));
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203 | 9fdf0c29 | David Gibson | } |
204 | 9fdf0c29 | David Gibson | |
205 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
206 | 9fdf0c29 | David Gibson | } |
207 | 9fdf0c29 | David Gibson | |
208 | 7267c094 | Anthony Liguori | g_free(modelname); |
209 | 9fdf0c29 | David Gibson | |
210 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
211 | 9fdf0c29 | David Gibson | |
212 | f43e3525 | David Gibson | /* RTAS */
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213 | f43e3525 | David Gibson | _FDT((fdt_begin_node(fdt, "rtas")));
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214 | f43e3525 | David Gibson | |
215 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
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216 | f43e3525 | David Gibson | sizeof(hypertas_prop))));
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217 | f43e3525 | David Gibson | |
218 | f43e3525 | David Gibson | _FDT((fdt_end_node(fdt))); |
219 | f43e3525 | David Gibson | |
220 | b5cec4c5 | David Gibson | /* interrupt controller */
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221 | 9dfef5aa | David Gibson | _FDT((fdt_begin_node(fdt, "interrupt-controller")));
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222 | b5cec4c5 | David Gibson | |
223 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "device_type",
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224 | b5cec4c5 | David Gibson | "PowerPC-External-Interrupt-Presentation")));
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225 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
226 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
227 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
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228 | b5cec4c5 | David Gibson | interrupt_server_ranges_prop, |
229 | b5cec4c5 | David Gibson | sizeof(interrupt_server_ranges_prop))));
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230 | 0c103f8e | David Gibson | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); |
231 | 0c103f8e | David Gibson | _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
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232 | 0c103f8e | David Gibson | _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
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233 | b5cec4c5 | David Gibson | |
234 | b5cec4c5 | David Gibson | _FDT((fdt_end_node(fdt))); |
235 | b5cec4c5 | David Gibson | |
236 | 4040ab72 | David Gibson | /* vdevice */
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237 | 4040ab72 | David Gibson | _FDT((fdt_begin_node(fdt, "vdevice")));
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238 | 4040ab72 | David Gibson | |
239 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
240 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
241 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
242 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
243 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
244 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
245 | 4040ab72 | David Gibson | |
246 | 4040ab72 | David Gibson | _FDT((fdt_end_node(fdt))); |
247 | 4040ab72 | David Gibson | |
248 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); /* close root node */
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249 | 9fdf0c29 | David Gibson | _FDT((fdt_finish(fdt))); |
250 | 9fdf0c29 | David Gibson | |
251 | a3467baa | David Gibson | return fdt;
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252 | a3467baa | David Gibson | } |
253 | a3467baa | David Gibson | |
254 | a3467baa | David Gibson | static void spapr_finalize_fdt(sPAPREnvironment *spapr, |
255 | a3467baa | David Gibson | target_phys_addr_t fdt_addr, |
256 | a3467baa | David Gibson | target_phys_addr_t rtas_addr, |
257 | a3467baa | David Gibson | target_phys_addr_t rtas_size) |
258 | a3467baa | David Gibson | { |
259 | a3467baa | David Gibson | int ret;
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260 | a3467baa | David Gibson | void *fdt;
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261 | a3467baa | David Gibson | |
262 | 7267c094 | Anthony Liguori | fdt = g_malloc(FDT_MAX_SIZE); |
263 | a3467baa | David Gibson | |
264 | a3467baa | David Gibson | /* open out the base tree into a temp buffer for the final tweaks */
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265 | a3467baa | David Gibson | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); |
266 | 4040ab72 | David Gibson | |
267 | 4040ab72 | David Gibson | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
268 | 4040ab72 | David Gibson | if (ret < 0) { |
269 | 4040ab72 | David Gibson | fprintf(stderr, "couldn't setup vio devices in fdt\n");
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270 | 4040ab72 | David Gibson | exit(1);
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271 | 4040ab72 | David Gibson | } |
272 | 4040ab72 | David Gibson | |
273 | 39ac8455 | David Gibson | /* RTAS */
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274 | 39ac8455 | David Gibson | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
275 | 39ac8455 | David Gibson | if (ret < 0) { |
276 | 39ac8455 | David Gibson | fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
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277 | 39ac8455 | David Gibson | } |
278 | 39ac8455 | David Gibson | |
279 | 4040ab72 | David Gibson | _FDT((fdt_pack(fdt))); |
280 | 4040ab72 | David Gibson | |
281 | a3467baa | David Gibson | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
282 | 9fdf0c29 | David Gibson | |
283 | 7267c094 | Anthony Liguori | g_free(fdt); |
284 | 9fdf0c29 | David Gibson | } |
285 | 9fdf0c29 | David Gibson | |
286 | 9fdf0c29 | David Gibson | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
287 | 9fdf0c29 | David Gibson | { |
288 | 9fdf0c29 | David Gibson | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
289 | 9fdf0c29 | David Gibson | } |
290 | 9fdf0c29 | David Gibson | |
291 | 9fdf0c29 | David Gibson | static void emulate_spapr_hypercall(CPUState *env) |
292 | 9fdf0c29 | David Gibson | { |
293 | 9fdf0c29 | David Gibson | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); |
294 | 9fdf0c29 | David Gibson | } |
295 | 9fdf0c29 | David Gibson | |
296 | a3467baa | David Gibson | static void spapr_reset(void *opaque) |
297 | a3467baa | David Gibson | { |
298 | a3467baa | David Gibson | sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; |
299 | a3467baa | David Gibson | |
300 | a3467baa | David Gibson | fprintf(stderr, "sPAPR reset\n");
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301 | a3467baa | David Gibson | |
302 | a3467baa | David Gibson | /* flush out the hash table */
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303 | a3467baa | David Gibson | memset(spapr->htab, 0, spapr->htab_size);
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304 | a3467baa | David Gibson | |
305 | a3467baa | David Gibson | /* Load the fdt */
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306 | a3467baa | David Gibson | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, |
307 | a3467baa | David Gibson | spapr->rtas_size); |
308 | a3467baa | David Gibson | |
309 | a3467baa | David Gibson | /* Set up the entry state */
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310 | a3467baa | David Gibson | first_cpu->gpr[3] = spapr->fdt_addr;
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311 | a3467baa | David Gibson | first_cpu->gpr[5] = 0; |
312 | a3467baa | David Gibson | first_cpu->halted = 0;
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313 | a3467baa | David Gibson | first_cpu->nip = spapr->entry_point; |
314 | a3467baa | David Gibson | |
315 | a3467baa | David Gibson | } |
316 | a3467baa | David Gibson | |
317 | 9fdf0c29 | David Gibson | /* pSeries LPAR / sPAPR hardware init */
|
318 | 9fdf0c29 | David Gibson | static void ppc_spapr_init(ram_addr_t ram_size, |
319 | 9fdf0c29 | David Gibson | const char *boot_device, |
320 | 9fdf0c29 | David Gibson | const char *kernel_filename, |
321 | 9fdf0c29 | David Gibson | const char *kernel_cmdline, |
322 | 9fdf0c29 | David Gibson | const char *initrd_filename, |
323 | 9fdf0c29 | David Gibson | const char *cpu_model) |
324 | 9fdf0c29 | David Gibson | { |
325 | c7a5c0c9 | David Gibson | CPUState *env; |
326 | 9fdf0c29 | David Gibson | int i;
|
327 | 9fdf0c29 | David Gibson | ram_addr_t ram_offset; |
328 | a3467baa | David Gibson | uint32_t initrd_base; |
329 | a3467baa | David Gibson | long kernel_size, initrd_size, fw_size;
|
330 | f43e3525 | David Gibson | long pteg_shift = 17; |
331 | 39ac8455 | David Gibson | char *filename;
|
332 | 9fdf0c29 | David Gibson | |
333 | 7267c094 | Anthony Liguori | spapr = g_malloc(sizeof(*spapr));
|
334 | 9fdf0c29 | David Gibson | cpu_ppc_hypercall = emulate_spapr_hypercall; |
335 | 9fdf0c29 | David Gibson | |
336 | 9fdf0c29 | David Gibson | /* We place the device tree just below either the top of RAM, or
|
337 | 9fdf0c29 | David Gibson | * 2GB, so that it can be processed with 32-bit code if
|
338 | 9fdf0c29 | David Gibson | * necessary */
|
339 | a3467baa | David Gibson | spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
|
340 | a3467baa | David Gibson | spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE; |
341 | 9fdf0c29 | David Gibson | |
342 | 9fdf0c29 | David Gibson | /* init CPUs */
|
343 | 9fdf0c29 | David Gibson | if (cpu_model == NULL) { |
344 | 9fdf0c29 | David Gibson | cpu_model = "POWER7";
|
345 | 9fdf0c29 | David Gibson | } |
346 | 9fdf0c29 | David Gibson | for (i = 0; i < smp_cpus; i++) { |
347 | c7a5c0c9 | David Gibson | env = cpu_init(cpu_model); |
348 | 9fdf0c29 | David Gibson | |
349 | 9fdf0c29 | David Gibson | if (!env) {
|
350 | 9fdf0c29 | David Gibson | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
351 | 9fdf0c29 | David Gibson | exit(1);
|
352 | 9fdf0c29 | David Gibson | } |
353 | 9fdf0c29 | David Gibson | /* Set time-base frequency to 512 MHz */
|
354 | 9fdf0c29 | David Gibson | cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
355 | 9fdf0c29 | David Gibson | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); |
356 | 9fdf0c29 | David Gibson | |
357 | 9fdf0c29 | David Gibson | env->hreset_vector = 0x60;
|
358 | 9fdf0c29 | David Gibson | env->hreset_excp_prefix = 0;
|
359 | c7a5c0c9 | David Gibson | env->gpr[3] = env->cpu_index;
|
360 | 9fdf0c29 | David Gibson | } |
361 | 9fdf0c29 | David Gibson | |
362 | 9fdf0c29 | David Gibson | /* allocate RAM */
|
363 | f73a2575 | David Gibson | spapr->ram_limit = ram_size; |
364 | f73a2575 | David Gibson | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit); |
365 | 9fdf0c29 | David Gibson | cpu_register_physical_memory(0, ram_size, ram_offset);
|
366 | 9fdf0c29 | David Gibson | |
367 | f43e3525 | David Gibson | /* allocate hash page table. For now we always make this 16mb,
|
368 | f43e3525 | David Gibson | * later we should probably make it scale to the size of guest
|
369 | f43e3525 | David Gibson | * RAM */
|
370 | a3467baa | David Gibson | spapr->htab_size = 1ULL << (pteg_shift + 7); |
371 | f61b4bed | Alexander Graf | spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size); |
372 | f43e3525 | David Gibson | |
373 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
374 | a3467baa | David Gibson | env->external_htab = spapr->htab; |
375 | c7a5c0c9 | David Gibson | env->htab_base = -1;
|
376 | a3467baa | David Gibson | env->htab_mask = spapr->htab_size - 1;
|
377 | f61b4bed | Alexander Graf | |
378 | f61b4bed | Alexander Graf | /* Tell KVM that we're in PAPR mode */
|
379 | f61b4bed | Alexander Graf | env->spr[SPR_SDR1] = (unsigned long)spapr->htab | |
380 | f61b4bed | Alexander Graf | ((pteg_shift + 7) - 18); |
381 | f61b4bed | Alexander Graf | env->spr[SPR_HIOR] = 0;
|
382 | f61b4bed | Alexander Graf | |
383 | f61b4bed | Alexander Graf | if (kvm_enabled()) {
|
384 | f61b4bed | Alexander Graf | kvmppc_set_papr(env); |
385 | f61b4bed | Alexander Graf | } |
386 | f43e3525 | David Gibson | } |
387 | f43e3525 | David Gibson | |
388 | 39ac8455 | David Gibson | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
|
389 | a3467baa | David Gibson | spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
390 | a3467baa | David Gibson | ram_size - spapr->rtas_addr); |
391 | a3467baa | David Gibson | if (spapr->rtas_size < 0) { |
392 | 39ac8455 | David Gibson | hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
393 | 39ac8455 | David Gibson | exit(1);
|
394 | 39ac8455 | David Gibson | } |
395 | 7267c094 | Anthony Liguori | g_free(filename); |
396 | 39ac8455 | David Gibson | |
397 | b5cec4c5 | David Gibson | /* Set up Interrupt Controller */
|
398 | c7a5c0c9 | David Gibson | spapr->icp = xics_system_init(XICS_IRQS); |
399 | e6c866d4 | David Gibson | spapr->next_irq = 16;
|
400 | b5cec4c5 | David Gibson | |
401 | b5cec4c5 | David Gibson | /* Set up VIO bus */
|
402 | 4040ab72 | David Gibson | spapr->vio_bus = spapr_vio_bus_init(); |
403 | 4040ab72 | David Gibson | |
404 | 277f9acf | Paolo Bonzini | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
405 | 4040ab72 | David Gibson | if (serial_hds[i]) {
|
406 | b4a78527 | David Gibson | spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i, |
407 | 277f9acf | Paolo Bonzini | serial_hds[i]); |
408 | 4040ab72 | David Gibson | } |
409 | 4040ab72 | David Gibson | } |
410 | 9fdf0c29 | David Gibson | |
411 | 277f9acf | Paolo Bonzini | for (i = 0; i < nb_nics; i++) { |
412 | 8d90ad90 | David Gibson | NICInfo *nd = &nd_table[i]; |
413 | 8d90ad90 | David Gibson | |
414 | 8d90ad90 | David Gibson | if (!nd->model) {
|
415 | 7267c094 | Anthony Liguori | nd->model = g_strdup("ibmveth");
|
416 | 8d90ad90 | David Gibson | } |
417 | 8d90ad90 | David Gibson | |
418 | 8d90ad90 | David Gibson | if (strcmp(nd->model, "ibmveth") == 0) { |
419 | 277f9acf | Paolo Bonzini | spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd);
|
420 | 8d90ad90 | David Gibson | } else {
|
421 | 8d90ad90 | David Gibson | fprintf(stderr, "pSeries (sPAPR) platform does not support "
|
422 | 8d90ad90 | David Gibson | "NIC model '%s' (only ibmveth is supported)\n",
|
423 | 8d90ad90 | David Gibson | nd->model); |
424 | 8d90ad90 | David Gibson | exit(1);
|
425 | 8d90ad90 | David Gibson | } |
426 | 8d90ad90 | David Gibson | } |
427 | 8d90ad90 | David Gibson | |
428 | 6e270446 | Ben Herrenschmidt | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
429 | 277f9acf | Paolo Bonzini | spapr_vscsi_create(spapr->vio_bus, 0x2000 + i);
|
430 | 6e270446 | Ben Herrenschmidt | } |
431 | 6e270446 | Ben Herrenschmidt | |
432 | 9fdf0c29 | David Gibson | if (kernel_filename) {
|
433 | 9fdf0c29 | David Gibson | uint64_t lowaddr = 0;
|
434 | 9fdf0c29 | David Gibson | |
435 | 9fdf0c29 | David Gibson | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
436 | 9fdf0c29 | David Gibson | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
437 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
438 | a3467baa | David Gibson | kernel_size = load_image_targphys(kernel_filename, |
439 | a3467baa | David Gibson | KERNEL_LOAD_ADDR, |
440 | a3467baa | David Gibson | ram_size - KERNEL_LOAD_ADDR); |
441 | 9fdf0c29 | David Gibson | } |
442 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
443 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
444 | 9fdf0c29 | David Gibson | kernel_filename); |
445 | 9fdf0c29 | David Gibson | exit(1);
|
446 | 9fdf0c29 | David Gibson | } |
447 | 9fdf0c29 | David Gibson | |
448 | 9fdf0c29 | David Gibson | /* load initrd */
|
449 | 9fdf0c29 | David Gibson | if (initrd_filename) {
|
450 | 9fdf0c29 | David Gibson | initrd_base = INITRD_LOAD_ADDR; |
451 | 9fdf0c29 | David Gibson | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
452 | 9fdf0c29 | David Gibson | ram_size - initrd_base); |
453 | 9fdf0c29 | David Gibson | if (initrd_size < 0) { |
454 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
455 | 9fdf0c29 | David Gibson | initrd_filename); |
456 | 9fdf0c29 | David Gibson | exit(1);
|
457 | 9fdf0c29 | David Gibson | } |
458 | 9fdf0c29 | David Gibson | } else {
|
459 | 9fdf0c29 | David Gibson | initrd_base = 0;
|
460 | 9fdf0c29 | David Gibson | initrd_size = 0;
|
461 | 9fdf0c29 | David Gibson | } |
462 | a3467baa | David Gibson | |
463 | a3467baa | David Gibson | spapr->entry_point = KERNEL_LOAD_ADDR; |
464 | 9fdf0c29 | David Gibson | } else {
|
465 | a9f8ad8f | David Gibson | if (ram_size < (MIN_RAM_SLOF << 20)) { |
466 | a9f8ad8f | David Gibson | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
|
467 | a9f8ad8f | David Gibson | "%ldM guest RAM\n", MIN_RAM_SLOF);
|
468 | a9f8ad8f | David Gibson | exit(1);
|
469 | a9f8ad8f | David Gibson | } |
470 | 68722054 | Nishanth Aravamudan | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME); |
471 | a9f8ad8f | David Gibson | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
|
472 | a9f8ad8f | David Gibson | if (fw_size < 0) { |
473 | a9f8ad8f | David Gibson | hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
|
474 | a9f8ad8f | David Gibson | exit(1);
|
475 | a9f8ad8f | David Gibson | } |
476 | 7267c094 | Anthony Liguori | g_free(filename); |
477 | a3467baa | David Gibson | spapr->entry_point = 0x100;
|
478 | a9f8ad8f | David Gibson | initrd_base = 0;
|
479 | a9f8ad8f | David Gibson | initrd_size = 0;
|
480 | a9f8ad8f | David Gibson | |
481 | a9f8ad8f | David Gibson | /* SLOF will startup the secondary CPUs using RTAS,
|
482 | a9f8ad8f | David Gibson | rather than expecting a kexec() style entry */
|
483 | c7a5c0c9 | David Gibson | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
484 | c7a5c0c9 | David Gibson | env->halted = 1;
|
485 | a9f8ad8f | David Gibson | } |
486 | 9fdf0c29 | David Gibson | } |
487 | 9fdf0c29 | David Gibson | |
488 | 9fdf0c29 | David Gibson | /* Prepare the device tree */
|
489 | a3467baa | David Gibson | spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
490 | a3467baa | David Gibson | initrd_base, initrd_size, |
491 | a3467baa | David Gibson | boot_device, kernel_cmdline, |
492 | a3467baa | David Gibson | pteg_shift + 7);
|
493 | a3467baa | David Gibson | assert(spapr->fdt_skel != NULL);
|
494 | 9fdf0c29 | David Gibson | |
495 | a3467baa | David Gibson | qemu_register_reset(spapr_reset, spapr); |
496 | 9fdf0c29 | David Gibson | } |
497 | 9fdf0c29 | David Gibson | |
498 | 9fdf0c29 | David Gibson | static QEMUMachine spapr_machine = {
|
499 | 9fdf0c29 | David Gibson | .name = "pseries",
|
500 | 9fdf0c29 | David Gibson | .desc = "pSeries Logical Partition (PAPR compliant)",
|
501 | 9fdf0c29 | David Gibson | .init = ppc_spapr_init, |
502 | 9fdf0c29 | David Gibson | .max_cpus = MAX_CPUS, |
503 | 9fdf0c29 | David Gibson | .no_vga = 1,
|
504 | 9fdf0c29 | David Gibson | .no_parallel = 1,
|
505 | 6e270446 | Ben Herrenschmidt | .use_scsi = 1,
|
506 | 9fdf0c29 | David Gibson | }; |
507 | 9fdf0c29 | David Gibson | |
508 | 9fdf0c29 | David Gibson | static void spapr_machine_init(void) |
509 | 9fdf0c29 | David Gibson | { |
510 | 9fdf0c29 | David Gibson | qemu_register_machine(&spapr_machine); |
511 | 9fdf0c29 | David Gibson | } |
512 | 9fdf0c29 | David Gibson | |
513 | 9fdf0c29 | David Gibson | machine_init(spapr_machine_init); |