root / hw / mc146818rtc.c @ 02fa69b6
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | aa28b9bf | Blue Swirl | #include "apic.h" |
29 | 87ecb68b | pbrook | #include "isa.h" |
30 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
31 | 80cabfad | bellard | |
32 | 80cabfad | bellard | //#define DEBUG_CMOS
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33 | aa6f63ff | Blue Swirl | //#define DEBUG_COALESCED
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34 | 80cabfad | bellard | |
35 | ec51e364 | Isaku Yamahata | #ifdef DEBUG_CMOS
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36 | ec51e364 | Isaku Yamahata | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
37 | ec51e364 | Isaku Yamahata | #else
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38 | ec51e364 | Isaku Yamahata | # define CMOS_DPRINTF(format, ...) do { } while (0) |
39 | ec51e364 | Isaku Yamahata | #endif
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40 | ec51e364 | Isaku Yamahata | |
41 | aa6f63ff | Blue Swirl | #ifdef DEBUG_COALESCED
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42 | aa6f63ff | Blue Swirl | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) |
43 | aa6f63ff | Blue Swirl | #else
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44 | aa6f63ff | Blue Swirl | # define DPRINTF_C(format, ...) do { } while (0) |
45 | aa6f63ff | Blue Swirl | #endif
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46 | aa6f63ff | Blue Swirl | |
47 | dd17765b | Gleb Natapov | #define RTC_REINJECT_ON_ACK_COUNT 20 |
48 | ba32edab | Gleb Natapov | |
49 | 80cabfad | bellard | #define RTC_SECONDS 0 |
50 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
51 | 80cabfad | bellard | #define RTC_MINUTES 2 |
52 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
53 | 80cabfad | bellard | #define RTC_HOURS 4 |
54 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
55 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
56 | 80cabfad | bellard | |
57 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
58 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
59 | 80cabfad | bellard | #define RTC_MONTH 8 |
60 | 80cabfad | bellard | #define RTC_YEAR 9 |
61 | 80cabfad | bellard | |
62 | 80cabfad | bellard | #define RTC_REG_A 10 |
63 | 80cabfad | bellard | #define RTC_REG_B 11 |
64 | 80cabfad | bellard | #define RTC_REG_C 12 |
65 | 80cabfad | bellard | #define RTC_REG_D 13 |
66 | 80cabfad | bellard | |
67 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
68 | 80cabfad | bellard | |
69 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
70 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
71 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
72 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
73 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
74 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
75 | c29cd656 | Aurelien Jarno | #define REG_B_24H 0x02 |
76 | dff38e7b | bellard | |
77 | 72716184 | Anthony Liguori | #define REG_C_UF 0x10 |
78 | 72716184 | Anthony Liguori | #define REG_C_IRQF 0x80 |
79 | 72716184 | Anthony Liguori | #define REG_C_PF 0x40 |
80 | 72716184 | Anthony Liguori | #define REG_C_AF 0x20 |
81 | 72716184 | Anthony Liguori | |
82 | 1d914fa0 | Isaku Yamahata | typedef struct RTCState { |
83 | 32e0c826 | Gerd Hoffmann | ISADevice dev; |
84 | dff38e7b | bellard | uint8_t cmos_data[128];
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85 | dff38e7b | bellard | uint8_t cmos_index; |
86 | 43f493af | bellard | struct tm current_tm;
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87 | 32e0c826 | Gerd Hoffmann | int32_t base_year; |
88 | d537cf6c | pbrook | qemu_irq irq; |
89 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
90 | 18c6e2ff | ths | int it_shift;
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91 | dff38e7b | bellard | /* periodic timer */
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92 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
93 | dff38e7b | bellard | int64_t next_periodic_time; |
94 | dff38e7b | bellard | /* second update */
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95 | dff38e7b | bellard | int64_t next_second_time; |
96 | ba32edab | Gleb Natapov | uint16_t irq_reinject_on_ack_count; |
97 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
98 | 73822ec8 | aliguori | uint32_t period; |
99 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
100 | dff38e7b | bellard | QEMUTimer *second_timer; |
101 | dff38e7b | bellard | QEMUTimer *second_timer2; |
102 | 17604dac | Jan Kiszka | Notifier clock_reset_notifier; |
103 | 1d914fa0 | Isaku Yamahata | } RTCState; |
104 | dff38e7b | bellard | |
105 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
106 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
107 | dff38e7b | bellard | |
108 | 93b66569 | aliguori | #ifdef TARGET_I386
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109 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
110 | 93b66569 | aliguori | { |
111 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
112 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
113 | 93b66569 | aliguori | } else {
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114 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
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115 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
116 | 74475455 | Paolo Bonzini | int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
117 | 6875204c | Jan Kiszka | muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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118 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
119 | 93b66569 | aliguori | } |
120 | 93b66569 | aliguori | } |
121 | 93b66569 | aliguori | |
122 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
123 | 93b66569 | aliguori | { |
124 | 93b66569 | aliguori | RTCState *s = opaque; |
125 | 93b66569 | aliguori | |
126 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
127 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
128 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
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129 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: injecting from timer\n");
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130 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
131 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
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132 | 93b66569 | aliguori | s->irq_coalesced--; |
133 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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134 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
135 | 93b66569 | aliguori | } |
136 | 93b66569 | aliguori | } |
137 | 93b66569 | aliguori | |
138 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
139 | 93b66569 | aliguori | } |
140 | 93b66569 | aliguori | #endif
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141 | 93b66569 | aliguori | |
142 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
143 | dff38e7b | bellard | { |
144 | dff38e7b | bellard | int period_code, period;
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145 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
146 | dff38e7b | bellard | |
147 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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148 | 100d9891 | aurel32 | if (period_code != 0 |
149 | 7d932dfd | Jan Kiszka | && ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
150 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
151 | dff38e7b | bellard | if (period_code <= 2) |
152 | dff38e7b | bellard | period_code += 7;
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153 | dff38e7b | bellard | /* period in 32 Khz cycles */
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154 | dff38e7b | bellard | period = 1 << (period_code - 1); |
155 | 73822ec8 | aliguori | #ifdef TARGET_I386
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156 | aa6f63ff | Blue Swirl | if (period != s->period) {
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157 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
158 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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159 | aa6f63ff | Blue Swirl | } |
160 | 73822ec8 | aliguori | s->period = period; |
161 | 73822ec8 | aliguori | #endif
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162 | dff38e7b | bellard | /* compute 32 khz clock */
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163 | 6ee093c9 | Juan Quintela | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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164 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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165 | 6875204c | Jan Kiszka | s->next_periodic_time = |
166 | 6875204c | Jan Kiszka | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
167 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
168 | dff38e7b | bellard | } else {
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169 | 73822ec8 | aliguori | #ifdef TARGET_I386
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170 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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171 | 73822ec8 | aliguori | #endif
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172 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
173 | dff38e7b | bellard | } |
174 | dff38e7b | bellard | } |
175 | dff38e7b | bellard | |
176 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
177 | dff38e7b | bellard | { |
178 | dff38e7b | bellard | RTCState *s = opaque; |
179 | dff38e7b | bellard | |
180 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
181 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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182 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
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183 | 93b66569 | aliguori | #ifdef TARGET_I386
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184 | 93b66569 | aliguori | if(rtc_td_hack) {
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185 | ba32edab | Gleb Natapov | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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186 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count = 0;
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187 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
188 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
189 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
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190 | 93b66569 | aliguori | s->irq_coalesced++; |
191 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
192 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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193 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
194 | 93b66569 | aliguori | } |
195 | 93b66569 | aliguori | } else
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196 | 93b66569 | aliguori | #endif
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197 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
198 | 100d9891 | aurel32 | } |
199 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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200 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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201 | 100d9891 | aurel32 | Must be seen as a pulse. */
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202 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
203 | 100d9891 | aurel32 | } |
204 | dff38e7b | bellard | } |
205 | 80cabfad | bellard | |
206 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
207 | 80cabfad | bellard | { |
208 | b41a2cd1 | bellard | RTCState *s = opaque; |
209 | 80cabfad | bellard | |
210 | 80cabfad | bellard | if ((addr & 1) == 0) { |
211 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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212 | 80cabfad | bellard | } else {
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213 | ec51e364 | Isaku Yamahata | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
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214 | ec51e364 | Isaku Yamahata | s->cmos_index, data); |
215 | dff38e7b | bellard | switch(s->cmos_index) {
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216 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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217 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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218 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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219 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
220 | 80cabfad | bellard | break;
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221 | 80cabfad | bellard | case RTC_SECONDS:
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222 | 80cabfad | bellard | case RTC_MINUTES:
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223 | 80cabfad | bellard | case RTC_HOURS:
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224 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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225 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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226 | 80cabfad | bellard | case RTC_MONTH:
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227 | 80cabfad | bellard | case RTC_YEAR:
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228 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
229 | dff38e7b | bellard | /* if in set mode, do not update the time */
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230 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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231 | dff38e7b | bellard | rtc_set_time(s); |
232 | dff38e7b | bellard | } |
233 | 80cabfad | bellard | break;
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234 | 80cabfad | bellard | case RTC_REG_A:
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235 | dff38e7b | bellard | /* UIP bit is read only */
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236 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
237 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
238 | 74475455 | Paolo Bonzini | rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
239 | dff38e7b | bellard | break;
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240 | 80cabfad | bellard | case RTC_REG_B:
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241 | dff38e7b | bellard | if (data & REG_B_SET) {
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242 | dff38e7b | bellard | /* set mode: reset UIP mode */
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243 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
244 | dff38e7b | bellard | data &= ~REG_B_UIE; |
245 | dff38e7b | bellard | } else {
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246 | dff38e7b | bellard | /* if disabling set mode, update the time */
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247 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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248 | dff38e7b | bellard | rtc_set_time(s); |
249 | dff38e7b | bellard | } |
250 | dff38e7b | bellard | } |
251 | 51e08f3e | Aurelien Jarno | if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
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252 | 51e08f3e | Aurelien Jarno | !(data & REG_B_SET)) { |
253 | 51e08f3e | Aurelien Jarno | /* If the time format has changed and not in set mode,
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254 | 51e08f3e | Aurelien Jarno | update the registers immediately. */
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255 | 51e08f3e | Aurelien Jarno | s->cmos_data[RTC_REG_B] = data; |
256 | 51e08f3e | Aurelien Jarno | rtc_copy_date(s); |
257 | 51e08f3e | Aurelien Jarno | } else {
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258 | 51e08f3e | Aurelien Jarno | s->cmos_data[RTC_REG_B] = data; |
259 | 51e08f3e | Aurelien Jarno | } |
260 | 74475455 | Paolo Bonzini | rtc_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
261 | 80cabfad | bellard | break;
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262 | 80cabfad | bellard | case RTC_REG_C:
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263 | 80cabfad | bellard | case RTC_REG_D:
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264 | 80cabfad | bellard | /* cannot write to them */
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265 | 80cabfad | bellard | break;
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266 | 80cabfad | bellard | default:
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267 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
268 | 80cabfad | bellard | break;
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269 | 80cabfad | bellard | } |
270 | 80cabfad | bellard | } |
271 | 80cabfad | bellard | } |
272 | 80cabfad | bellard | |
273 | abd0c6bd | Paul Brook | static inline int rtc_to_bcd(RTCState *s, int a) |
274 | 80cabfad | bellard | { |
275 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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276 | dff38e7b | bellard | return a;
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277 | dff38e7b | bellard | } else {
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278 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
279 | dff38e7b | bellard | } |
280 | 80cabfad | bellard | } |
281 | 80cabfad | bellard | |
282 | abd0c6bd | Paul Brook | static inline int rtc_from_bcd(RTCState *s, int a) |
283 | 80cabfad | bellard | { |
284 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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285 | dff38e7b | bellard | return a;
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286 | dff38e7b | bellard | } else {
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287 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
288 | dff38e7b | bellard | } |
289 | dff38e7b | bellard | } |
290 | dff38e7b | bellard | |
291 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
292 | dff38e7b | bellard | { |
293 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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294 | dff38e7b | bellard | |
295 | abd0c6bd | Paul Brook | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
296 | abd0c6bd | Paul Brook | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
297 | abd0c6bd | Paul Brook | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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298 | c29cd656 | Aurelien Jarno | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H) &&
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299 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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300 | 43f493af | bellard | tm->tm_hour += 12;
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301 | 43f493af | bellard | } |
302 | abd0c6bd | Paul Brook | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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303 | abd0c6bd | Paul Brook | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
304 | abd0c6bd | Paul Brook | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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305 | abd0c6bd | Paul Brook | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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306 | 80cd3478 | Luiz Capitulino | |
307 | 80cd3478 | Luiz Capitulino | rtc_change_mon_event(tm); |
308 | 43f493af | bellard | } |
309 | 43f493af | bellard | |
310 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
311 | 43f493af | bellard | { |
312 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
313 | 42fc73a1 | aurel32 | int year;
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314 | dff38e7b | bellard | |
315 | abd0c6bd | Paul Brook | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
316 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
317 | c29cd656 | Aurelien Jarno | if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
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318 | 43f493af | bellard | /* 24 hour format */
|
319 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
320 | 43f493af | bellard | } else {
|
321 | 43f493af | bellard | /* 12 hour format */
|
322 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
|
323 | 43f493af | bellard | if (tm->tm_hour >= 12) |
324 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
|
325 | 43f493af | bellard | } |
326 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
327 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
328 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
329 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
|
330 | 42fc73a1 | aurel32 | if (year < 0) |
331 | 42fc73a1 | aurel32 | year += 100;
|
332 | abd0c6bd | Paul Brook | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
333 | 43f493af | bellard | } |
334 | 43f493af | bellard | |
335 | 43f493af | bellard | /* month is between 0 and 11. */
|
336 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
337 | 43f493af | bellard | { |
338 | 5fafdf24 | ths | static const int days_tab[12] = { |
339 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
340 | 43f493af | bellard | }; |
341 | 43f493af | bellard | int d;
|
342 | 43f493af | bellard | if ((unsigned )month >= 12) |
343 | 43f493af | bellard | return 31; |
344 | 43f493af | bellard | d = days_tab[month]; |
345 | 43f493af | bellard | if (month == 1) { |
346 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
347 | 43f493af | bellard | d++; |
348 | 43f493af | bellard | } |
349 | 43f493af | bellard | return d;
|
350 | 43f493af | bellard | } |
351 | 43f493af | bellard | |
352 | 43f493af | bellard | /* update 'tm' to the next second */
|
353 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
354 | 43f493af | bellard | { |
355 | 43f493af | bellard | int days_in_month;
|
356 | 43f493af | bellard | |
357 | 43f493af | bellard | tm->tm_sec++; |
358 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
359 | 43f493af | bellard | tm->tm_sec = 0;
|
360 | 43f493af | bellard | tm->tm_min++; |
361 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
362 | 43f493af | bellard | tm->tm_min = 0;
|
363 | 43f493af | bellard | tm->tm_hour++; |
364 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
365 | 43f493af | bellard | tm->tm_hour = 0;
|
366 | 43f493af | bellard | /* next day */
|
367 | 43f493af | bellard | tm->tm_wday++; |
368 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
369 | 43f493af | bellard | tm->tm_wday = 0;
|
370 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
371 | 43f493af | bellard | tm->tm_year + 1900);
|
372 | 43f493af | bellard | tm->tm_mday++; |
373 | 43f493af | bellard | if (tm->tm_mday < 1) { |
374 | 43f493af | bellard | tm->tm_mday = 1;
|
375 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
376 | 43f493af | bellard | tm->tm_mday = 1;
|
377 | 43f493af | bellard | tm->tm_mon++; |
378 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
379 | 43f493af | bellard | tm->tm_mon = 0;
|
380 | 43f493af | bellard | tm->tm_year++; |
381 | 43f493af | bellard | } |
382 | 43f493af | bellard | } |
383 | 43f493af | bellard | } |
384 | 43f493af | bellard | } |
385 | 43f493af | bellard | } |
386 | dff38e7b | bellard | } |
387 | dff38e7b | bellard | |
388 | 43f493af | bellard | |
389 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
390 | dff38e7b | bellard | { |
391 | dff38e7b | bellard | RTCState *s = opaque; |
392 | 4721c457 | bellard | int64_t delay; |
393 | dff38e7b | bellard | |
394 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
395 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
396 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
397 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
398 | dff38e7b | bellard | } else {
|
399 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
400 | 3b46e624 | ths | |
401 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
402 | dff38e7b | bellard | /* update in progress bit */
|
403 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
404 | dff38e7b | bellard | } |
405 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
406 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
407 | 6ee093c9 | Juan Quintela | delay = (get_ticks_per_sec() * 1) / 100; |
408 | 4721c457 | bellard | if (delay < 1) |
409 | 4721c457 | bellard | delay = 1;
|
410 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
411 | 4721c457 | bellard | s->next_second_time + delay); |
412 | dff38e7b | bellard | } |
413 | dff38e7b | bellard | } |
414 | dff38e7b | bellard | |
415 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
416 | dff38e7b | bellard | { |
417 | dff38e7b | bellard | RTCState *s = opaque; |
418 | dff38e7b | bellard | |
419 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
420 | dff38e7b | bellard | rtc_copy_date(s); |
421 | dff38e7b | bellard | } |
422 | dff38e7b | bellard | |
423 | dff38e7b | bellard | /* check alarm */
|
424 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
425 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
426 | f292787d | Gleb Natapov | rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) && |
427 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
428 | f292787d | Gleb Natapov | rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) && |
429 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
430 | f292787d | Gleb Natapov | rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) { |
431 | dff38e7b | bellard | |
432 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
433 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
434 | dff38e7b | bellard | } |
435 | dff38e7b | bellard | } |
436 | dff38e7b | bellard | |
437 | dff38e7b | bellard | /* update ended interrupt */
|
438 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
439 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
440 | 7d932dfd | Jan Kiszka | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
441 | 7d932dfd | Jan Kiszka | qemu_irq_raise(s->irq); |
442 | dff38e7b | bellard | } |
443 | dff38e7b | bellard | |
444 | dff38e7b | bellard | /* clear update in progress bit */
|
445 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
446 | dff38e7b | bellard | |
447 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
448 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
449 | 80cabfad | bellard | } |
450 | 80cabfad | bellard | |
451 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
452 | 80cabfad | bellard | { |
453 | b41a2cd1 | bellard | RTCState *s = opaque; |
454 | 80cabfad | bellard | int ret;
|
455 | 80cabfad | bellard | if ((addr & 1) == 0) { |
456 | 80cabfad | bellard | return 0xff; |
457 | 80cabfad | bellard | } else {
|
458 | 80cabfad | bellard | switch(s->cmos_index) {
|
459 | 80cabfad | bellard | case RTC_SECONDS:
|
460 | 80cabfad | bellard | case RTC_MINUTES:
|
461 | 80cabfad | bellard | case RTC_HOURS:
|
462 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
463 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
464 | 80cabfad | bellard | case RTC_MONTH:
|
465 | 80cabfad | bellard | case RTC_YEAR:
|
466 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
467 | 80cabfad | bellard | break;
|
468 | 80cabfad | bellard | case RTC_REG_A:
|
469 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
470 | 80cabfad | bellard | break;
|
471 | 80cabfad | bellard | case RTC_REG_C:
|
472 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
473 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
474 | ba32edab | Gleb Natapov | #ifdef TARGET_I386
|
475 | ba32edab | Gleb Natapov | if(s->irq_coalesced &&
|
476 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
477 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count++; |
478 | ba32edab | Gleb Natapov | apic_reset_irq_delivered(); |
479 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: injecting on ack\n");
|
480 | ba32edab | Gleb Natapov | qemu_irq_raise(s->irq); |
481 | aa6f63ff | Blue Swirl | if (apic_get_irq_delivered()) {
|
482 | ba32edab | Gleb Natapov | s->irq_coalesced--; |
483 | aa6f63ff | Blue Swirl | DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
484 | aa6f63ff | Blue Swirl | s->irq_coalesced); |
485 | aa6f63ff | Blue Swirl | } |
486 | ba32edab | Gleb Natapov | break;
|
487 | ba32edab | Gleb Natapov | } |
488 | ba32edab | Gleb Natapov | #endif
|
489 | ba32edab | Gleb Natapov | |
490 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
491 | 80cabfad | bellard | break;
|
492 | 80cabfad | bellard | default:
|
493 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
494 | 80cabfad | bellard | break;
|
495 | 80cabfad | bellard | } |
496 | ec51e364 | Isaku Yamahata | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
497 | ec51e364 | Isaku Yamahata | s->cmos_index, ret); |
498 | 80cabfad | bellard | return ret;
|
499 | 80cabfad | bellard | } |
500 | 80cabfad | bellard | } |
501 | 80cabfad | bellard | |
502 | 1d914fa0 | Isaku Yamahata | void rtc_set_memory(ISADevice *dev, int addr, int val) |
503 | dff38e7b | bellard | { |
504 | 1d914fa0 | Isaku Yamahata | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
505 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
506 | dff38e7b | bellard | s->cmos_data[addr] = val; |
507 | dff38e7b | bellard | } |
508 | dff38e7b | bellard | |
509 | 1d914fa0 | Isaku Yamahata | void rtc_set_date(ISADevice *dev, const struct tm *tm) |
510 | dff38e7b | bellard | { |
511 | 1d914fa0 | Isaku Yamahata | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
512 | 43f493af | bellard | s->current_tm = *tm; |
513 | dff38e7b | bellard | rtc_copy_date(s); |
514 | dff38e7b | bellard | } |
515 | dff38e7b | bellard | |
516 | ea55ffb3 | ths | /* PC cmos mappings */
|
517 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
518 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
519 | ea55ffb3 | ths | |
520 | 1d914fa0 | Isaku Yamahata | static void rtc_set_date_from_host(ISADevice *dev) |
521 | ea55ffb3 | ths | { |
522 | 1d914fa0 | Isaku Yamahata | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
523 | f6503059 | balrog | struct tm tm;
|
524 | ea55ffb3 | ths | int val;
|
525 | ea55ffb3 | ths | |
526 | ea55ffb3 | ths | /* set the CMOS date */
|
527 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
528 | 1d914fa0 | Isaku Yamahata | rtc_set_date(dev, &tm); |
529 | ea55ffb3 | ths | |
530 | abd0c6bd | Paul Brook | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
531 | 1d914fa0 | Isaku Yamahata | rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
532 | 1d914fa0 | Isaku Yamahata | rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); |
533 | ea55ffb3 | ths | } |
534 | ea55ffb3 | ths | |
535 | 6b075b8a | Juan Quintela | static int rtc_post_load(void *opaque, int version_id) |
536 | 80cabfad | bellard | { |
537 | 6b075b8a | Juan Quintela | #ifdef TARGET_I386
|
538 | dff38e7b | bellard | RTCState *s = opaque; |
539 | dff38e7b | bellard | |
540 | 048c74c4 | Juan Quintela | if (version_id >= 2) { |
541 | 048c74c4 | Juan Quintela | if (rtc_td_hack) {
|
542 | 048c74c4 | Juan Quintela | rtc_coalesced_timer_update(s); |
543 | 048c74c4 | Juan Quintela | } |
544 | 048c74c4 | Juan Quintela | } |
545 | 6b075b8a | Juan Quintela | #endif
|
546 | 73822ec8 | aliguori | return 0; |
547 | 73822ec8 | aliguori | } |
548 | 73822ec8 | aliguori | |
549 | 6b075b8a | Juan Quintela | static const VMStateDescription vmstate_rtc = { |
550 | 6b075b8a | Juan Quintela | .name = "mc146818rtc",
|
551 | 6b075b8a | Juan Quintela | .version_id = 2,
|
552 | 6b075b8a | Juan Quintela | .minimum_version_id = 1,
|
553 | 6b075b8a | Juan Quintela | .minimum_version_id_old = 1,
|
554 | 6b075b8a | Juan Quintela | .post_load = rtc_post_load, |
555 | 6b075b8a | Juan Quintela | .fields = (VMStateField []) { |
556 | 6b075b8a | Juan Quintela | VMSTATE_BUFFER(cmos_data, RTCState), |
557 | 6b075b8a | Juan Quintela | VMSTATE_UINT8(cmos_index, RTCState), |
558 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_sec, RTCState), |
559 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_min, RTCState), |
560 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_hour, RTCState), |
561 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_wday, RTCState), |
562 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mday, RTCState), |
563 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mon, RTCState), |
564 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_year, RTCState), |
565 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(periodic_timer, RTCState), |
566 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_periodic_time, RTCState), |
567 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_second_time, RTCState), |
568 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer, RTCState), |
569 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer2, RTCState), |
570 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
571 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(period, RTCState, 2),
|
572 | 6b075b8a | Juan Quintela | VMSTATE_END_OF_LIST() |
573 | 6b075b8a | Juan Quintela | } |
574 | 6b075b8a | Juan Quintela | }; |
575 | 6b075b8a | Juan Quintela | |
576 | 17604dac | Jan Kiszka | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
577 | 17604dac | Jan Kiszka | { |
578 | 17604dac | Jan Kiszka | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); |
579 | 17604dac | Jan Kiszka | int64_t now = *(int64_t *)data; |
580 | 17604dac | Jan Kiszka | |
581 | 17604dac | Jan Kiszka | rtc_set_date_from_host(&s->dev); |
582 | 17604dac | Jan Kiszka | s->next_second_time = now + (get_ticks_per_sec() * 99) / 100; |
583 | 17604dac | Jan Kiszka | qemu_mod_timer(s->second_timer2, s->next_second_time); |
584 | 17604dac | Jan Kiszka | rtc_timer_update(s, now); |
585 | 17604dac | Jan Kiszka | #ifdef TARGET_I386
|
586 | 17604dac | Jan Kiszka | if (rtc_td_hack) {
|
587 | 17604dac | Jan Kiszka | rtc_coalesced_timer_update(s); |
588 | 17604dac | Jan Kiszka | } |
589 | 17604dac | Jan Kiszka | #endif
|
590 | 17604dac | Jan Kiszka | } |
591 | 17604dac | Jan Kiszka | |
592 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
593 | eeb7c03c | Gleb Natapov | { |
594 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
595 | eeb7c03c | Gleb Natapov | |
596 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
597 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
598 | eeb7c03c | Gleb Natapov | |
599 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
600 | eeb7c03c | Gleb Natapov | |
601 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
602 | eeb7c03c | Gleb Natapov | if (rtc_td_hack)
|
603 | eeb7c03c | Gleb Natapov | s->irq_coalesced = 0;
|
604 | eeb7c03c | Gleb Natapov | #endif
|
605 | eeb7c03c | Gleb Natapov | } |
606 | eeb7c03c | Gleb Natapov | |
607 | 32e0c826 | Gerd Hoffmann | static int rtc_initfn(ISADevice *dev) |
608 | dff38e7b | bellard | { |
609 | 32e0c826 | Gerd Hoffmann | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
610 | 32e0c826 | Gerd Hoffmann | int base = 0x70; |
611 | 80cabfad | bellard | |
612 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
613 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
614 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
615 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
616 | 80cabfad | bellard | |
617 | 1d914fa0 | Isaku Yamahata | rtc_set_date_from_host(dev); |
618 | ea55ffb3 | ths | |
619 | 74475455 | Paolo Bonzini | s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); |
620 | 93b66569 | aliguori | #ifdef TARGET_I386
|
621 | 93b66569 | aliguori | if (rtc_td_hack)
|
622 | 6875204c | Jan Kiszka | s->coalesced_timer = |
623 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
624 | 93b66569 | aliguori | #endif
|
625 | 74475455 | Paolo Bonzini | s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s); |
626 | 74475455 | Paolo Bonzini | s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s); |
627 | dff38e7b | bellard | |
628 | 17604dac | Jan Kiszka | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
629 | 17604dac | Jan Kiszka | qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); |
630 | 17604dac | Jan Kiszka | |
631 | 6875204c | Jan Kiszka | s->next_second_time = |
632 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
633 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
634 | dff38e7b | bellard | |
635 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
636 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
637 | dee41d58 | Gleb Natapov | isa_init_ioport_range(dev, base, 2);
|
638 | dff38e7b | bellard | |
639 | dc683910 | Jan Kiszka | qdev_set_legacy_instance_id(&dev->qdev, base, 2);
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640 | a08d4367 | Jan Kiszka | qemu_register_reset(rtc_reset, s); |
641 | 32e0c826 | Gerd Hoffmann | return 0; |
642 | 32e0c826 | Gerd Hoffmann | } |
643 | 32e0c826 | Gerd Hoffmann | |
644 | 7d932dfd | Jan Kiszka | ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
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645 | 32e0c826 | Gerd Hoffmann | { |
646 | 32e0c826 | Gerd Hoffmann | ISADevice *dev; |
647 | 7d932dfd | Jan Kiszka | RTCState *s; |
648 | eeb7c03c | Gleb Natapov | |
649 | 32e0c826 | Gerd Hoffmann | dev = isa_create("mc146818rtc");
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650 | 7d932dfd | Jan Kiszka | s = DO_UPCAST(RTCState, dev, dev); |
651 | 32e0c826 | Gerd Hoffmann | qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
652 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
653 | 7d932dfd | Jan Kiszka | if (intercept_irq) {
|
654 | 7d932dfd | Jan Kiszka | s->irq = intercept_irq; |
655 | 7d932dfd | Jan Kiszka | } else {
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656 | 7d932dfd | Jan Kiszka | isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); |
657 | 7d932dfd | Jan Kiszka | } |
658 | 1d914fa0 | Isaku Yamahata | return dev;
|
659 | 80cabfad | bellard | } |
660 | 80cabfad | bellard | |
661 | 32e0c826 | Gerd Hoffmann | static ISADeviceInfo mc146818rtc_info = {
|
662 | 32e0c826 | Gerd Hoffmann | .qdev.name = "mc146818rtc",
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663 | 32e0c826 | Gerd Hoffmann | .qdev.size = sizeof(RTCState),
|
664 | 32e0c826 | Gerd Hoffmann | .qdev.no_user = 1,
|
665 | dc683910 | Jan Kiszka | .qdev.vmsd = &vmstate_rtc, |
666 | 32e0c826 | Gerd Hoffmann | .init = rtc_initfn, |
667 | 32e0c826 | Gerd Hoffmann | .qdev.props = (Property[]) { |
668 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
669 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
670 | 32e0c826 | Gerd Hoffmann | } |
671 | 32e0c826 | Gerd Hoffmann | }; |
672 | 32e0c826 | Gerd Hoffmann | |
673 | 32e0c826 | Gerd Hoffmann | static void mc146818rtc_register(void) |
674 | 100d9891 | aurel32 | { |
675 | 32e0c826 | Gerd Hoffmann | isa_qdev_register(&mc146818rtc_info); |
676 | 100d9891 | aurel32 | } |
677 | 32e0c826 | Gerd Hoffmann | device_init(mc146818rtc_register) |