target-mips: fix EXTPDP and setting up pos field in the DSPControl reg
This change makes sure that modifications of pos field in the DSPControlregister do not trash other bits in the register. This bug can be triggeredwith the additional test case in mips32-dsp/extpdp.c in this commit....
target-mips: fix incorrect behaviour for EXTP
The mask for EXTP instruction when size=31 has not been correctlycalculated.
The test (mips32-dsp/extp.c) has been extended to include the case thattriggers the issue.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>...
target-mips: fix incorrect behaviour for INSV
Corner case for INSV instruction when size=32 has not been correctlyimplemented. The mask for size should be one bit wider, and preparing thefilter variable should be aware of this case too.
The test for INSV has been extended to include the case that triggers the...
target-mips: fix calculation of overflow for SHLL.PH and SHLL.QB
This change corrects and simplifies how discard is calculated for shiftleft logical vector instructions. It is used to detect overflow and set bit22 in the DSPControl register.
The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases...
target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHR
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format.Otherwise, the results are unpredictable. Once the operands were correctedin the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became...
target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
Fix for rndrashift_short_acc to set correct value to higher 64 bits.This change also corrects conditions when bit 23 of the DSPControl registeris set.
The existing test files have been extended with several examples that...
target-mips: fix DSP overflow macro and affected routines
The previous implementation incorrectly used same macro to detect overflowfor addition and subtraction. This patch makes distinction between thesetwo, and creates separate macros. The affected routines are changed...
target-mips: fix incorrect test for MTHLIP
The pos field in the DSPControl register is not correctly initialized.Per documentation, the result of MTHLIP is unpredictable if the value of thepos field before the execution is greater than 32.
Signed-off-by: Petar Jovanovic <petarj@mips.com>...
target-mips: Fix for helpers for EXTR_* instructions
The change removes some unnecessary and incorrect code for EXTR_S.H.Further, it corrects the mask for shift value in the EXTR_ instructions. It alsoextends the existing tests so they trigger the issues corrected with the change....
target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used inthe MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32these bits must be written as zero, and return zero on read....
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