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root / target-ppc @ 0ef654e3

Name Size
STATUS 10.6 kB
cpu.h 88.4 kB
helper.c 105.5 kB
helper.h 14.8 kB
helper_regs.h 3.3 kB
kvm.c 24.6 kB
kvm_ppc.c 1.1 kB
kvm_ppc.h 2.5 kB
machine.c 5.7 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 653 Bytes
op_helper.c 134.7 kB
translate.c 352.4 kB
translate_init.c 428.8 kB

Latest revisions

# Date Author Comment
a1ef618a 02/02/2012 03:47 am Alexander Graf

PPC: booke: add tlbnps handling

When using MAV 2.0 TLB registers, we have another range of TLB registers
available to read the supported page sizes from.

Add SPR definitions for those and add a helper function that we can use
to receive such a bitmap even when using MAV 1.0....
5935ee07 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Check for min/max TLB entry size

When setting a TLB entry, we need to check if the TLB we're putting it in
actually supports the given size. According to the 2.06 PowerPC ISA, a
value that's out of range can either be redefined to something implementation...
6d3db821 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Implement tlbilx

The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used
to flush TLB entries. It's the recommended way of flushing in virtualized
environments.

So far we got away without implementing it, but Linux for e500mc uses this...
3f162d11 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Check for TLB overrun

Our internal helpers to fetch TLB entries were not able to tell us
that an entry doesn't even exist. Pass an error out if we hit such
a case to not accidently pass beyond the TLB array.

Signed-off-by: Alexander Graf <>
21a0b6ed 02/02/2012 03:47 am Alexander Graf

PPC: booke206: move avail check to tlbwe

We can have TLBs that only support a single page size. This is defined
by the absence of the AVAIL flag in TLBnCFG. If this is the case, we
currently write invalid size info into the TLB, but override it on
internal fault....
0ef654e3 02/02/2012 03:47 am Alexander Graf

PPC: E500: Add some more excp vectors

Our EXCP list is getting outdated. By now, 3 new exception vectors have
been introduced. Update the list so we have everything at one place.

Signed-off-by: Alexander Graf <>
2c9732db 02/02/2012 03:47 am Alexander Graf

PPC: e500mc: add missing IVORs to bitmap

E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE
support too.

Signed-off-by: Alexander Graf <>
53319166 02/02/2012 03:47 am Alexander Graf

PPC: e500: msync is 440 only, e500 has real sync

The e500 CPUs don't use 440's msync which falls on the same opcode IDs,
but instead use the real powerpc sync instruction. This is important,
since the invalid mask differs between the two.

Signed-off-by: Alexander Graf <>
dcb2b9e1 02/02/2012 03:47 am Alexander Graf

PPC: rename msync to msync_4xx

The msync instruction as defined today is only valid on 4xx cores, not
on e500 which also supports msync, but treats it the same way as sync.

Rename it to reflect that it's 4xx only.

Signed-off-by: Alexander Graf <>
ffba8786 02/02/2012 03:47 am Alexander Graf

PPC: booke206: allow NULL raddr in ppcmas_tlb_check

We might want to call the tlb check function without actually caring about
the real address resolution. Check if we really should write the value
back.

Signed-off-by: Alexander Graf <>

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