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target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical(shifted register)".
We store the flags in the same locations as the 32 bit decoder.This is slightly awkward when calculating 64 bit results, but seems...
target-arm: A64: add support for ADR and ADRP
Add support for the instructions described in"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder structure]Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>...
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditionalbranch (register)' instruction category except for ERETand DPRS (which are system mode only).
Signed-off-by: Alexander Graf <agraf@suse.de>...
target-arm: A64: add support for conditional branches
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags]...
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,TBZ and TBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted for new decoder always compare with 0 remove a TCG temporary...
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,CBZ and CBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)]...
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: Improved code generated in the nomatch case as per RTH suggestions]...
target-arm: A64: provide skeleton for a64 insn decoding
Provide a skeleton for a64 instruction decoding in translate-a64.c,by dividing instructions into the classes defined by theARM Architecture Reference Manual(DDI0487A_a) section C3.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>...
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field...
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generatedif a source register is the zero-register XZR, we provide a simple...
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because ithas to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing...
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictlyspeaking represent an architectural register. However it's convenientfor QEMU to use it to hold the various PSTATE architectural bitsin the same format the architecture specifies for SPSR registers...
target-arm: Add AArch64 translation stub
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,registers look vastly different, instruction encoding is completely different,basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the...