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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 35 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 907 Bytes
helper-a64.h 773 Bytes
helper.c 133.3 kB
helper.h 17.4 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 1.9 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 35.8 kB
translate.c 365.8 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
832ffa1c 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for logical (shifted register)

Add support for the instructions described in "C3.5.10 Logical
(shifted register)".

We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems...
15bfe8b6 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for ADR and ADRP

Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana <>...
b001c8c3 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for BR, BLR and RET insns

Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).

Signed-off-by: Alexander Graf <>...
39fb730a 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder structure,
reused arm infrastructure for checking the flags]...
db0f7958 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for 'test and branch' imm

This patch adds emulation for the test and branch insns,
TBZ and TBNZ.

Signed-off-by: Alexander Graf <>
[claudio:
adapted for new decoder
always compare with 0
remove a TCG temporary...
60e53388 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for compare and branch imm

This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.

Signed-off-by: Alexander Graf <>
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)]...
e952d8c7 12/17/2013 09:42 pm Claudio Fontana

target-arm: A64: add support for conditional select

This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.

Signed-off-by: Claudio Fontana <>
[PMM: Improved code generated in the nomatch case as per RTH suggestions]...
ad7ee8a2 12/17/2013 09:42 pm Claudio Fontana

target-arm: A64: provide skeleton for a64 insn decoding

Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.

Signed-off-by: Claudio Fontana <>...
87462e0f 12/17/2013 09:42 pm Claudio Fontana

target-arm: A64: expand decoding skeleton for system instructions

Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field...
11e169de 12/17/2013 09:42 pm Alexander Graf

target-arm: A64: add support for B and BL insns

Implement the B and BL instructions (PC relative branches and calls).

For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple...

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