Statistics
| Branch: | Revision:

root / hw / net @ 17cf2c76

Name Size
Makefile.objs 1.2 kB
cadence_gem.c 41.2 kB
dp8393x.c 26.4 kB
e1000.c 50.1 kB
e1000_regs.h 49.6 kB
eepro100.c 69.2 kB
etraxfs_eth.c 16.7 kB
lan9118.c 39.2 kB
lance.c 5.1 kB
mcf_fec.c 12.3 kB
milkymist-minimac2.c 14 kB
mipsnet.c 7.4 kB
ne2000-isa.c 3.6 kB
ne2000.c 22.8 kB
ne2000.h 1 kB
opencores_eth.c 18.9 kB
pcnet-pci.c 11.2 kB
pcnet.c 54.6 kB
pcnet.h 2.1 kB
rtl8139.c 102 kB
smc91c111.c 22.2 kB
spapr_llan.c 16.8 kB
stellaris_enet.c 13.1 kB
vhost_net.c 8.4 kB
virtio-net.c 48.2 kB
vmware_utils.h 3.5 kB
vmxnet3.c 72.2 kB
vmxnet3.h 23.8 kB
vmxnet_debug.h 4.3 kB
vmxnet_rx_pkt.c 4.1 kB
vmxnet_rx_pkt.h 3.8 kB
vmxnet_tx_pkt.c 15.9 kB
vmxnet_tx_pkt.h 3.2 kB
xen_nic.c 13.8 kB
xgmac.c 14.6 kB
xilinx_axienet.c 28 kB
xilinx_ethlite.c 7.7 kB

Latest revisions

# Date Author Comment
11785f53 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Don't assert against 0 buffer address

This has no real hardware analog and asserting correctness of DMA
addresses is not a perhiperal level problem. Delete.

Signed-off-by: Peter Crosthwaite <>
Message-id: ...
7cfd65e4 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: simplify rx buf descriptor walking

There was a replication of the rx descriptor address walking logic.
Reorder the flow control to remove. This refactoring also obsoletes
the local variables packet_desc_addr and last_desc_addr.

Signed-off-by: Peter Crosthwaite <>...
06c2fe95 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Prefetch rx descriptors ASAP

The real hardware prefetches rx buffer descriptors ASAP and
potentially throws relevant interrupts following the fetch
even in the absence of a received packet.

Reported-by: Deepika Dhamija <>...
63af1e0c 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Implement RX descriptor match mode flags

The various Rx packet address matching mode flags were not being set in
the rx descriptor. Implement.

Reported-by: Deepika Dhamija <>
Signed-off-by: Peter Crosthwaite <>...
a03f7429 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Implement SAR match bit in rx desc

Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match. Implement.

This feature is absent from the Xilinx documentation (UG585) but the
behaviour is tested as accurate on real hardware....
64eb9301 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Implement SAR (de)activation

The Specific address registers can be enabled or disabled by software.
QEMU was assuming they were always enabled. Implement the
disable/enable feature. SARs are disabled by writing to the lower half
register. They are re-enabled by then writing the upper half....
17cf2c76 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Add missing VMSTATE_END_OF_LIST

Signed-off-by: Peter Crosthwaite <>
Message-id:
Signed-off-by: Peter Maydell <>
24e822ea 12/10/2013 03:28 pm Peter Crosthwaite

net/cadence_gem: Implement mac level loopback mode

Cadence GEM has a MAC level loopback mode. Implement. Use the same basic
operation as the already implemented PHY loopback.

Reported-by: Deepika Dhamija <>
Signed-off-by: Peter Crosthwaite <>...
3b2c97f9 12/10/2013 03:28 pm Edgar E. Iglesias

net/cadence_gem: Update DMA rx descriptors as we process them

We were updating the ownership bit of all descriptors if packets
get split and written through several descriptors.

Signed-off-by: Edgar E. Iglesias <>
Signed-off-by: Peter Crosthwaite <>...
cb77e358 12/02/2013 07:04 pm Zhi Yong Wu

virtio-net: fix the indent

Signed-off-by: Zhi Yong Wu <>
Reviewed-by: Fam Zheng <>
Signed-off-by: Michael Tokarev <>

View revisions

Also available in: Atom