root / target-sh4 / cpu.h @ 26ac1ea5
History | View | Annotate | Download (11.1 kB)
1 | fdf9b3e8 | bellard | /*
|
---|---|---|---|
2 | fdf9b3e8 | bellard | * SH4 emulation
|
3 | 5fafdf24 | ths | *
|
4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
|
5 | fdf9b3e8 | bellard | *
|
6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
|
7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
|
9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | fdf9b3e8 | bellard | *
|
11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
|
15 | fdf9b3e8 | bellard | *
|
16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | fdf9b3e8 | bellard | */
|
19 | fdf9b3e8 | bellard | #ifndef _CPU_SH4_H
|
20 | fdf9b3e8 | bellard | #define _CPU_SH4_H
|
21 | fdf9b3e8 | bellard | |
22 | fdf9b3e8 | bellard | #include "config.h" |
23 | 9a78eead | Stefan Weil | #include "qemu-common.h" |
24 | fdf9b3e8 | bellard | |
25 | fdf9b3e8 | bellard | #define TARGET_LONG_BITS 32 |
26 | fdf9b3e8 | bellard | #define TARGET_HAS_ICE 1 |
27 | fdf9b3e8 | bellard | |
28 | 9042c0e2 | ths | #define ELF_MACHINE EM_SH
|
29 | 9042c0e2 | ths | |
30 | 0fd3ca30 | aurel32 | /* CPU Subtypes */
|
31 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750 (1 << 0) |
32 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750S (1 << 1) |
33 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750R (1 << 2) |
34 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751 (1 << 3) |
35 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751R (1 << 4) |
36 | a9c43f8e | aurel32 | #define SH_CPU_SH7785 (1 << 5) |
37 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
|
38 | 0fd3ca30 | aurel32 | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
|
39 | 0fd3ca30 | aurel32 | |
40 | c2764719 | pbrook | #define CPUState struct CPUSH4State |
41 | c2764719 | pbrook | |
42 | fdf9b3e8 | bellard | #include "cpu-defs.h" |
43 | fdf9b3e8 | bellard | |
44 | eda9b09b | bellard | #include "softfloat.h" |
45 | eda9b09b | bellard | |
46 | fdf9b3e8 | bellard | #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
47 | fdf9b3e8 | bellard | |
48 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
49 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
50 | 52705890 | Richard Henderson | |
51 | fdf9b3e8 | bellard | #define SR_MD (1 << 30) |
52 | fdf9b3e8 | bellard | #define SR_RB (1 << 29) |
53 | fdf9b3e8 | bellard | #define SR_BL (1 << 28) |
54 | fdf9b3e8 | bellard | #define SR_FD (1 << 15) |
55 | fdf9b3e8 | bellard | #define SR_M (1 << 9) |
56 | fdf9b3e8 | bellard | #define SR_Q (1 << 8) |
57 | 56cd2b96 | aurel32 | #define SR_I3 (1 << 7) |
58 | 56cd2b96 | aurel32 | #define SR_I2 (1 << 6) |
59 | 56cd2b96 | aurel32 | #define SR_I1 (1 << 5) |
60 | 56cd2b96 | aurel32 | #define SR_I0 (1 << 4) |
61 | fdf9b3e8 | bellard | #define SR_S (1 << 1) |
62 | fdf9b3e8 | bellard | #define SR_T (1 << 0) |
63 | fdf9b3e8 | bellard | |
64 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_MASK (0x003fffff) |
65 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FR (1 << 21) |
66 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_SZ (1 << 20) |
67 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_PR (1 << 19) |
68 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_DN (1 << 18) |
69 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_MASK (0x3f << 12) |
70 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_SHIFT (12) |
71 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_E (1 << 17) |
72 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_V (1 << 16) |
73 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_Z (1 << 15) |
74 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_O (1 << 14) |
75 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_U (1 << 13) |
76 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_CAUSE_I (1 << 12) |
77 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_MASK (0x1f << 7) |
78 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_SHIFT (7) |
79 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_V (1 << 11) |
80 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_Z (1 << 10) |
81 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_O (1 << 9) |
82 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_U (1 << 8) |
83 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_ENABLE_I (1 << 7) |
84 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_MASK (0x1f << 2) |
85 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_SHIFT (2) |
86 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_V (1 << 6) |
87 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_Z (1 << 5) |
88 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_O (1 << 4) |
89 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_U (1 << 3) |
90 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_FLAG_I (1 << 2) |
91 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_RM_MASK (0x03 << 0) |
92 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_RM_NEAREST (0 << 0) |
93 | 26ac1ea5 | Aurelien Jarno | #define FPSCR_RM_ZERO (1 << 0) |
94 | 26ac1ea5 | Aurelien Jarno | |
95 | 823029f9 | ths | #define DELAY_SLOT (1 << 0) |
96 | fdf9b3e8 | bellard | #define DELAY_SLOT_CONDITIONAL (1 << 1) |
97 | 823029f9 | ths | #define DELAY_SLOT_TRUE (1 << 2) |
98 | 823029f9 | ths | #define DELAY_SLOT_CLEARME (1 << 3) |
99 | 823029f9 | ths | /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
|
100 | 823029f9 | ths | * after the delay slot should be taken or not. It is calculated from SR_T.
|
101 | 823029f9 | ths | *
|
102 | 823029f9 | ths | * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
|
103 | 823029f9 | ths | * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
|
104 | 823029f9 | ths | */
|
105 | fdf9b3e8 | bellard | |
106 | fdf9b3e8 | bellard | typedef struct tlb_t { |
107 | fdf9b3e8 | bellard | uint32_t vpn; /* virtual page number */
|
108 | fdf9b3e8 | bellard | uint32_t ppn; /* physical page number */
|
109 | af090497 | Aurelien Jarno | uint32_t size; /* mapped page size in bytes */
|
110 | af090497 | Aurelien Jarno | uint8_t asid; /* address space identifier */
|
111 | af090497 | Aurelien Jarno | uint8_t v:1; /* validity */ |
112 | af090497 | Aurelien Jarno | uint8_t sz:2; /* page size */ |
113 | af090497 | Aurelien Jarno | uint8_t sh:1; /* share status */ |
114 | af090497 | Aurelien Jarno | uint8_t c:1; /* cacheability */ |
115 | af090497 | Aurelien Jarno | uint8_t pr:2; /* protection key */ |
116 | af090497 | Aurelien Jarno | uint8_t d:1; /* dirty */ |
117 | af090497 | Aurelien Jarno | uint8_t wt:1; /* write through */ |
118 | af090497 | Aurelien Jarno | uint8_t sa:3; /* space attribute (PCMCIA) */ |
119 | af090497 | Aurelien Jarno | uint8_t tc:1; /* timing control */ |
120 | fdf9b3e8 | bellard | } tlb_t; |
121 | fdf9b3e8 | bellard | |
122 | fdf9b3e8 | bellard | #define UTLB_SIZE 64 |
123 | fdf9b3e8 | bellard | #define ITLB_SIZE 4 |
124 | fdf9b3e8 | bellard | |
125 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
126 | 6ebbf390 | j_mayer | |
127 | 71968fa6 | aurel32 | enum sh_features {
|
128 | 71968fa6 | aurel32 | SH_FEATURE_SH4A = 1,
|
129 | c2432a42 | aurel32 | SH_FEATURE_BCR3_AND_BCR4 = 2,
|
130 | 71968fa6 | aurel32 | }; |
131 | 71968fa6 | aurel32 | |
132 | 852d481f | edgar_igl | typedef struct memory_content { |
133 | 852d481f | edgar_igl | uint32_t address; |
134 | 852d481f | edgar_igl | uint32_t value; |
135 | 852d481f | edgar_igl | struct memory_content *next;
|
136 | 852d481f | edgar_igl | } memory_content; |
137 | 852d481f | edgar_igl | |
138 | fdf9b3e8 | bellard | typedef struct CPUSH4State { |
139 | 0fd3ca30 | aurel32 | int id; /* CPU model */ |
140 | 0fd3ca30 | aurel32 | |
141 | fdf9b3e8 | bellard | uint32_t flags; /* general execution flags */
|
142 | fdf9b3e8 | bellard | uint32_t gregs[24]; /* general registers */ |
143 | e04ea3dc | ths | float32 fregs[32]; /* floating point registers */ |
144 | fdf9b3e8 | bellard | uint32_t sr; /* status register */
|
145 | fdf9b3e8 | bellard | uint32_t ssr; /* saved status register */
|
146 | fdf9b3e8 | bellard | uint32_t spc; /* saved program counter */
|
147 | fdf9b3e8 | bellard | uint32_t gbr; /* global base register */
|
148 | fdf9b3e8 | bellard | uint32_t vbr; /* vector base register */
|
149 | fdf9b3e8 | bellard | uint32_t sgr; /* saved global register 15 */
|
150 | fdf9b3e8 | bellard | uint32_t dbr; /* debug base register */
|
151 | fdf9b3e8 | bellard | uint32_t pc; /* program counter */
|
152 | fdf9b3e8 | bellard | uint32_t delayed_pc; /* target of delayed jump */
|
153 | fdf9b3e8 | bellard | uint32_t mach; /* multiply and accumulate high */
|
154 | fdf9b3e8 | bellard | uint32_t macl; /* multiply and accumulate low */
|
155 | fdf9b3e8 | bellard | uint32_t pr; /* procedure register */
|
156 | fdf9b3e8 | bellard | uint32_t fpscr; /* floating point status/control register */
|
157 | fdf9b3e8 | bellard | uint32_t fpul; /* floating point communication register */
|
158 | fdf9b3e8 | bellard | |
159 | 17b086f7 | aurel32 | /* float point status register */
|
160 | ea6cf6be | ths | float_status fp_status; |
161 | eda9b09b | bellard | |
162 | 71968fa6 | aurel32 | /* The features that we should emulate. See sh_features above. */
|
163 | 71968fa6 | aurel32 | uint32_t features; |
164 | 71968fa6 | aurel32 | |
165 | fdf9b3e8 | bellard | /* Those belong to the specific unit (SH7750) but are handled here */
|
166 | fdf9b3e8 | bellard | uint32_t mmucr; /* MMU control register */
|
167 | fdf9b3e8 | bellard | uint32_t pteh; /* page table entry high register */
|
168 | fdf9b3e8 | bellard | uint32_t ptel; /* page table entry low register */
|
169 | fdf9b3e8 | bellard | uint32_t ptea; /* page table entry assistance register */
|
170 | fdf9b3e8 | bellard | uint32_t ttb; /* tranlation table base register */
|
171 | fdf9b3e8 | bellard | uint32_t tea; /* TLB exception address register */
|
172 | fdf9b3e8 | bellard | uint32_t tra; /* TRAPA exception register */
|
173 | fdf9b3e8 | bellard | uint32_t expevt; /* exception event register */
|
174 | fdf9b3e8 | bellard | uint32_t intevt; /* interrupt event register */
|
175 | fdf9b3e8 | bellard | |
176 | 0fd3ca30 | aurel32 | uint32_t pvr; /* Processor Version Register */
|
177 | 0fd3ca30 | aurel32 | uint32_t prr; /* Processor Revision Register */
|
178 | 0fd3ca30 | aurel32 | uint32_t cvr; /* Cache Version Register */
|
179 | 0fd3ca30 | aurel32 | |
180 | 66c7c806 | aurel32 | uint32_t ldst; |
181 | 66c7c806 | aurel32 | |
182 | fdf9b3e8 | bellard | CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
|
183 | fdf9b3e8 | bellard | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
|
184 | e96e2044 | ths | void *intc_handle;
|
185 | 833ed386 | aurel32 | int intr_at_halt; /* SR_BL ignored during sleep */ |
186 | 852d481f | edgar_igl | memory_content *movcal_backup; |
187 | 852d481f | edgar_igl | memory_content **movcal_backup_tail; |
188 | fdf9b3e8 | bellard | } CPUSH4State; |
189 | fdf9b3e8 | bellard | |
190 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model); |
191 | fdf9b3e8 | bellard | int cpu_sh4_exec(CPUSH4State * s);
|
192 | 5fafdf24 | ths | int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
193 | 5a7b542b | ths | void *puc);
|
194 | 42083220 | aurel32 | int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, |
195 | 42083220 | aurel32 | int mmu_idx, int is_softmmu); |
196 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
|
197 | 42083220 | aurel32 | void do_interrupt(CPUSH4State * env);
|
198 | 42083220 | aurel32 | |
199 | 9a78eead | Stefan Weil | void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
200 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
201 | e0bcb9ca | Aurelien Jarno | void cpu_sh4_invalidate_tlb(CPUSH4State *s);
|
202 | c0f809c4 | Aurelien Jarno | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
203 | c0f809c4 | Aurelien Jarno | uint32_t mem_value); |
204 | c227f099 | Anthony Liguori | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
205 | 29e179bc | aurel32 | uint32_t mem_value); |
206 | 3c7b48b7 | Paul Brook | #endif
|
207 | fdf9b3e8 | bellard | |
208 | 852d481f | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
|
209 | 852d481f | edgar_igl | |
210 | 0b6d3ae0 | aurel32 | static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls) |
211 | 0b6d3ae0 | aurel32 | { |
212 | 0b6d3ae0 | aurel32 | env->gbr = newtls; |
213 | 0b6d3ae0 | aurel32 | } |
214 | 0b6d3ae0 | aurel32 | |
215 | ef7ec1c1 | aurel32 | void cpu_load_tlb(CPUSH4State * env);
|
216 | ef7ec1c1 | aurel32 | |
217 | fdf9b3e8 | bellard | #include "softfloat.h" |
218 | fdf9b3e8 | bellard | |
219 | 9467d44c | ths | #define cpu_init cpu_sh4_init
|
220 | 9467d44c | ths | #define cpu_exec cpu_sh4_exec
|
221 | 9467d44c | ths | #define cpu_gen_code cpu_sh4_gen_code
|
222 | 9467d44c | ths | #define cpu_signal_handler cpu_sh4_signal_handler
|
223 | 0fd3ca30 | aurel32 | #define cpu_list sh4_cpu_list
|
224 | 9467d44c | ths | |
225 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
226 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
|
227 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
|
228 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
229 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
230 | 6ebbf390 | j_mayer | { |
231 | 6ebbf390 | j_mayer | return (env->sr & SR_MD) == 0 ? 1 : 0; |
232 | 6ebbf390 | j_mayer | } |
233 | 6ebbf390 | j_mayer | |
234 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
|
235 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
236 | 6e68e076 | pbrook | { |
237 | f8ed7070 | pbrook | if (newsp)
|
238 | 6e68e076 | pbrook | env->gregs[15] = newsp;
|
239 | 6e68e076 | pbrook | env->gregs[0] = 0; |
240 | 6e68e076 | pbrook | } |
241 | 6e68e076 | pbrook | #endif
|
242 | 6e68e076 | pbrook | |
243 | fdf9b3e8 | bellard | #include "cpu-all.h" |
244 | fdf9b3e8 | bellard | |
245 | fdf9b3e8 | bellard | /* Memory access type */
|
246 | fdf9b3e8 | bellard | enum {
|
247 | fdf9b3e8 | bellard | /* Privilege */
|
248 | fdf9b3e8 | bellard | ACCESS_PRIV = 0x01,
|
249 | fdf9b3e8 | bellard | /* Direction */
|
250 | fdf9b3e8 | bellard | ACCESS_WRITE = 0x02,
|
251 | fdf9b3e8 | bellard | /* Type of instruction */
|
252 | fdf9b3e8 | bellard | ACCESS_CODE = 0x10,
|
253 | fdf9b3e8 | bellard | ACCESS_INT = 0x20
|
254 | fdf9b3e8 | bellard | }; |
255 | fdf9b3e8 | bellard | |
256 | fdf9b3e8 | bellard | /* MMU control register */
|
257 | fdf9b3e8 | bellard | #define MMUCR 0x1F000010 |
258 | fdf9b3e8 | bellard | #define MMUCR_AT (1<<0) |
259 | e0bcb9ca | Aurelien Jarno | #define MMUCR_TI (1<<2) |
260 | fdf9b3e8 | bellard | #define MMUCR_SV (1<<8) |
261 | ea2b542a | aurel32 | #define MMUCR_URC_BITS (6) |
262 | ea2b542a | aurel32 | #define MMUCR_URC_OFFSET (10) |
263 | ea2b542a | aurel32 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
264 | ea2b542a | aurel32 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
265 | ea2b542a | aurel32 | static inline int cpu_mmucr_urc (uint32_t mmucr) |
266 | ea2b542a | aurel32 | { |
267 | ea2b542a | aurel32 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
|
268 | ea2b542a | aurel32 | } |
269 | ea2b542a | aurel32 | |
270 | ea2b542a | aurel32 | /* PTEH : Page Translation Entry High register */
|
271 | ea2b542a | aurel32 | #define PTEH_ASID_BITS (8) |
272 | ea2b542a | aurel32 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
273 | ea2b542a | aurel32 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
274 | ea2b542a | aurel32 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
|
275 | ea2b542a | aurel32 | #define PTEH_VPN_BITS (22) |
276 | ea2b542a | aurel32 | #define PTEH_VPN_OFFSET (10) |
277 | ea2b542a | aurel32 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
278 | ea2b542a | aurel32 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
279 | ea2b542a | aurel32 | static inline int cpu_pteh_vpn (uint32_t pteh) |
280 | ea2b542a | aurel32 | { |
281 | ea2b542a | aurel32 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
|
282 | ea2b542a | aurel32 | } |
283 | ea2b542a | aurel32 | |
284 | ea2b542a | aurel32 | /* PTEL : Page Translation Entry Low register */
|
285 | ea2b542a | aurel32 | #define PTEL_V (1 << 8) |
286 | ea2b542a | aurel32 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
287 | ea2b542a | aurel32 | #define PTEL_C (1 << 3) |
288 | ea2b542a | aurel32 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
289 | ea2b542a | aurel32 | #define PTEL_D (1 << 2) |
290 | ea2b542a | aurel32 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
291 | ea2b542a | aurel32 | #define PTEL_SH (1 << 1) |
292 | ea2b542a | aurel32 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
293 | ea2b542a | aurel32 | #define PTEL_WT (1 << 0) |
294 | ea2b542a | aurel32 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
|
295 | ea2b542a | aurel32 | |
296 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH_OFFSET (7) |
297 | ea2b542a | aurel32 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
298 | ea2b542a | aurel32 | #define PTEL_SZ_LOW_OFFSET (4) |
299 | ea2b542a | aurel32 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
300 | ea2b542a | aurel32 | static inline int cpu_ptel_sz (uint32_t ptel) |
301 | ea2b542a | aurel32 | { |
302 | ea2b542a | aurel32 | int sz;
|
303 | ea2b542a | aurel32 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
304 | ea2b542a | aurel32 | sz <<= 1;
|
305 | ea2b542a | aurel32 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
306 | ea2b542a | aurel32 | return sz;
|
307 | ea2b542a | aurel32 | } |
308 | ea2b542a | aurel32 | |
309 | ea2b542a | aurel32 | #define PTEL_PPN_BITS (19) |
310 | ea2b542a | aurel32 | #define PTEL_PPN_OFFSET (10) |
311 | ea2b542a | aurel32 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
312 | ea2b542a | aurel32 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
313 | ea2b542a | aurel32 | static inline int cpu_ptel_ppn (uint32_t ptel) |
314 | ea2b542a | aurel32 | { |
315 | ea2b542a | aurel32 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
|
316 | ea2b542a | aurel32 | } |
317 | ea2b542a | aurel32 | |
318 | ea2b542a | aurel32 | #define PTEL_PR_BITS (2) |
319 | ea2b542a | aurel32 | #define PTEL_PR_OFFSET (5) |
320 | ea2b542a | aurel32 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
321 | ea2b542a | aurel32 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
322 | ea2b542a | aurel32 | static inline int cpu_ptel_pr (uint32_t ptel) |
323 | ea2b542a | aurel32 | { |
324 | ea2b542a | aurel32 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
|
325 | ea2b542a | aurel32 | } |
326 | ea2b542a | aurel32 | |
327 | ea2b542a | aurel32 | /* PTEA : Page Translation Entry Assistance register */
|
328 | ea2b542a | aurel32 | #define PTEA_SA_BITS (3) |
329 | ea2b542a | aurel32 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
330 | ea2b542a | aurel32 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
331 | ea2b542a | aurel32 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
|
332 | ea2b542a | aurel32 | #define PTEA_TC (1 << 3) |
333 | ea2b542a | aurel32 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
334 | fdf9b3e8 | bellard | |
335 | 852d481f | edgar_igl | #define TB_FLAG_PENDING_MOVCA (1 << 4) |
336 | 852d481f | edgar_igl | |
337 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
338 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
339 | 6b917547 | aliguori | { |
340 | 6b917547 | aliguori | *pc = env->pc; |
341 | 6b917547 | aliguori | *cs_base = 0;
|
342 | 6b917547 | aliguori | *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL |
343 | 6b917547 | aliguori | | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
|
344 | 6b917547 | aliguori | | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
|
345 | d8299bcc | aurel32 | | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
|
346 | 852d481f | edgar_igl | | (env->sr & SR_FD) /* Bit 15 */
|
347 | 852d481f | edgar_igl | | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ |
348 | 6b917547 | aliguori | } |
349 | 6b917547 | aliguori | |
350 | fdf9b3e8 | bellard | #endif /* _CPU_SH4_H */ |