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# Date Author Comment
b67ea0cd 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement memory protection options

- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).

Cache control attribute bits are not used by this implementation.

Signed-off-by: Max Filippov <>...
553e44f9 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement windowed registers

See ISA, 4.7.1 for details.

Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical...
797d780b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement loop option

See ISA, 4.3.2 for details.

Operations that change LEND SR value invalidate TBs at the old and at
the new LEND. LEND value at TB compilation time is considered constant
and loop instruction is generated based on this value....
1ddeaa5d 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement SIMCALL

Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.

Note that simcalls that accept buffer addresses expect virtual addresses....
b994e91b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement interrupt option

See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
3580ecad 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement shifts (ST1 and RST1 groups)

- ST1: SAR (shift amount special register) manipulation, NSA;
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
40643d7c 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement exceptions

- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
dedc5eae 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement disas_xtensa_insn

Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <>...