Archipelago » qemu

/*

 *  ARM translation

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *  Copyright (c) 2005-2007 CodeSourcery

 *  Copyright (c) 2007 OpenedHand, Ltd.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-log.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

#define ENABLE_ARCH_4T    arm_feature(env, ARM_FEATURE_V4T)

#define ENABLE_ARCH_5     arm_feature(env, ARM_FEATURE_V5)

/* currently all emulated v5 cores are also v5TE, so don't bother */

#define ENABLE_ARCH_5TE   arm_feature(env, ARM_FEATURE_V5)

#define ENABLE_ARCH_5J    0

#define ENABLE_ARCH_6     arm_feature(env, ARM_FEATURE_V6)

#define ENABLE_ARCH_6K   arm_feature(env, ARM_FEATURE_V6K)

#define ENABLE_ARCH_6T2   arm_feature(env, ARM_FEATURE_THUMB2)

#define ENABLE_ARCH_7     arm_feature(env, ARM_FEATURE_V7)

#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)

/* internal defines */

typedef struct DisasContext {

    target_ulong pc;

    int is_jmp;

    /* Nonzero if this instruction has been conditionally skipped.  */

    int condjmp;

    /* The label that will be jumped to when the instruction is skipped.  */

    int condlabel;

    /* Thumb-2 condtional execution bits.  */

    int condexec_mask;

    int condexec_cond;

    struct TranslationBlock *tb;

    int singlestep_enabled;

    int thumb;

    int bswap_code;

#if !defined(CONFIG_USER_ONLY)

    int user;

#endif

    int vfp_enabled;

    int vec_len;

    int vec_stride;

} DisasContext;

static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];

#if defined(CONFIG_USER_ONLY)

#define IS_USER(s) 1

#else

#define IS_USER(s) (s->user)

#endif

/* These instructions trap after executing, so defer them until after the

   conditional executions state has been updated.  */

#define DISAS_WFI 4

#define DISAS_SWI 5

static TCGv_ptr cpu_env;

/* We reuse the same 64-bit temporaries for efficiency.  */

static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;

static TCGv_i32 cpu_R[16];

static TCGv_i32 cpu_exclusive_addr;

static TCGv_i32 cpu_exclusive_val;

static TCGv_i32 cpu_exclusive_high;

#ifdef CONFIG_USER_ONLY

static TCGv_i32 cpu_exclusive_test;

static TCGv_i32 cpu_exclusive_info;

#endif

/* FIXME:  These should be removed.  */

static TCGv cpu_F0s, cpu_F1s;

static TCGv_i64 cpu_F0d, cpu_F1d;

#include "gen-icount.h"

static const char *regnames[] =

    { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",

      "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };

/* initialize TCG globals.  */

void arm_translate_init(void)

{

    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    for (i = 0; i < 16; i++) {

        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                          offsetof(CPUARMState, regs[i]),

                                          regnames[i]);

    }

    cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,

        offsetof(CPUARMState, exclusive_addr), "exclusive_addr");

    cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,

        offsetof(CPUARMState, exclusive_val), "exclusive_val");

    cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,

        offsetof(CPUARMState, exclusive_high), "exclusive_high");

#ifdef CONFIG_USER_ONLY

    cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,

        offsetof(CPUARMState, exclusive_test), "exclusive_test");

    cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,

        offsetof(CPUARMState, exclusive_info), "exclusive_info");

#endif

#define GEN_HELPER 2

#include "helper.h"

}

static inline TCGv load_cpu_offset(int offset)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_ld_i32(tmp, cpu_env, offset);

    return tmp;

}

#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))

static inline void store_cpu_offset(TCGv var, int offset)

{

    tcg_gen_st_i32(var, cpu_env, offset);

    tcg_temp_free_i32(var);

}

#define store_cpu_field(var, name) \

    store_cpu_offset(var, offsetof(CPUARMState, name))

/* Set a variable to the value of a CPU register.  */

static void load_reg_var(DisasContext *s, TCGv var, int reg)

{

    if (reg == 15) {

        uint32_t addr;

        /* normaly, since we updated PC, we need only to add one insn */

        if (s->thumb)

            addr = (long)s->pc + 2;

        else

            addr = (long)s->pc + 4;

        tcg_gen_movi_i32(var, addr);

    } else {

        tcg_gen_mov_i32(var, cpu_R[reg]);

    }

}

/* Create a new temporary and set it to the value of a CPU register.  */

static inline TCGv load_reg(DisasContext *s, int reg)

{

    TCGv tmp = tcg_temp_new_i32();

    load_reg_var(s, tmp, reg);

    return tmp;

}

/* Set a CPU register.  The source must be a temporary and will be

   marked as dead.  */

static void store_reg(DisasContext *s, int reg, TCGv var)

{

    if (reg == 15) {

        tcg_gen_andi_i32(var, var, ~1);

        s->is_jmp = DISAS_JUMP;

    }

    tcg_gen_mov_i32(cpu_R[reg], var);

    tcg_temp_free_i32(var);

}

/* Value extensions.  */

#define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)

#define gen_uxth(var) tcg_gen_ext16u_i32(var, var)

#define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)

#define gen_sxth(var) tcg_gen_ext16s_i32(var, var)

#define gen_sxtb16(var) gen_helper_sxtb16(var, var)

#define gen_uxtb16(var) gen_helper_uxtb16(var, var)

static inline void gen_set_cpsr(TCGv var, uint32_t mask)

{

    TCGv tmp_mask = tcg_const_i32(mask);

    gen_helper_cpsr_write(var, tmp_mask);

    tcg_temp_free_i32(tmp_mask);

}

/* Set NZCV flags from the high 4 bits of var.  */

#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)

static void gen_exception(int excp)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_movi_i32(tmp, excp);

    gen_helper_exception(tmp);

    tcg_temp_free_i32(tmp);

}

static void gen_smul_dual(TCGv a, TCGv b)

{

    TCGv tmp1 = tcg_temp_new_i32();

    TCGv tmp2 = tcg_temp_new_i32();

    tcg_gen_ext16s_i32(tmp1, a);

    tcg_gen_ext16s_i32(tmp2, b);

    tcg_gen_mul_i32(tmp1, tmp1, tmp2);

    tcg_temp_free_i32(tmp2);

    tcg_gen_sari_i32(a, a, 16);

    tcg_gen_sari_i32(b, b, 16);

    tcg_gen_mul_i32(b, b, a);

    tcg_gen_mov_i32(a, tmp1);

    tcg_temp_free_i32(tmp1);

}

/* Byteswap each halfword.  */

static void gen_rev16(TCGv var)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_shri_i32(tmp, var, 8);

    tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);

    tcg_gen_shli_i32(var, var, 8);

    tcg_gen_andi_i32(var, var, 0xff00ff00);

    tcg_gen_or_i32(var, var, tmp);

    tcg_temp_free_i32(tmp);

}

/* Byteswap low halfword and sign extend.  */

static void gen_revsh(TCGv var)

{

    tcg_gen_ext16u_i32(var, var);

    tcg_gen_bswap16_i32(var, var);

    tcg_gen_ext16s_i32(var, var);

}

/* Unsigned bitfield extract.  */

static void gen_ubfx(TCGv var, int shift, uint32_t mask)

{

    if (shift)

        tcg_gen_shri_i32(var, var, shift);

    tcg_gen_andi_i32(var, var, mask);

}

/* Signed bitfield extract.  */

static void gen_sbfx(TCGv var, int shift, int width)

{

    uint32_t signbit;

    if (shift)

        tcg_gen_sari_i32(var, var, shift);

    if (shift + width < 32) {

        signbit = 1u << (width - 1);

        tcg_gen_andi_i32(var, var, (1u << width) - 1);

        tcg_gen_xori_i32(var, var, signbit);

        tcg_gen_subi_i32(var, var, signbit);

    }

}

/* Bitfield insertion.  Insert val into base.  Clobbers base and val.  */

static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)

{

    tcg_gen_andi_i32(val, val, mask);

    tcg_gen_shli_i32(val, val, shift);

    tcg_gen_andi_i32(base, base, ~(mask << shift));

    tcg_gen_or_i32(dest, base, val);

}

/* Return (b << 32) + a. Mark inputs as dead */

static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)

{

    TCGv_i64 tmp64 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp64, b);

    tcg_temp_free_i32(b);

    tcg_gen_shli_i64(tmp64, tmp64, 32);

    tcg_gen_add_i64(a, tmp64, a);

    tcg_temp_free_i64(tmp64);

    return a;

}

/* Return (b << 32) - a. Mark inputs as dead. */

static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)

{

    TCGv_i64 tmp64 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp64, b);

    tcg_temp_free_i32(b);

    tcg_gen_shli_i64(tmp64, tmp64, 32);

    tcg_gen_sub_i64(a, tmp64, a);

    tcg_temp_free_i64(tmp64);

    return a;

}

/* FIXME: Most targets have native widening multiplication.

   It would be good to use that instead of a full wide multiply.  */

/* 32x32->64 multiply.  Marks inputs as dead.  */

static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)

{

    TCGv_i64 tmp1 = tcg_temp_new_i64();

    TCGv_i64 tmp2 = tcg_temp_new_i64();

    tcg_gen_extu_i32_i64(tmp1, a);

    tcg_temp_free_i32(a);

    tcg_gen_extu_i32_i64(tmp2, b);

    tcg_temp_free_i32(b);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_temp_free_i64(tmp2);

    return tmp1;

}

static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)

{

    TCGv_i64 tmp1 = tcg_temp_new_i64();

    TCGv_i64 tmp2 = tcg_temp_new_i64();

    tcg_gen_ext_i32_i64(tmp1, a);

    tcg_temp_free_i32(a);

    tcg_gen_ext_i32_i64(tmp2, b);

    tcg_temp_free_i32(b);

    tcg_gen_mul_i64(tmp1, tmp1, tmp2);

    tcg_temp_free_i64(tmp2);

    return tmp1;

}

/* Swap low and high halfwords.  */

static void gen_swap_half(TCGv var)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_shri_i32(tmp, var, 16);

    tcg_gen_shli_i32(var, var, 16);

    tcg_gen_or_i32(var, var, tmp);

    tcg_temp_free_i32(tmp);

}

/* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.

    tmp = (t0 ^ t1) & 0x8000;

    t0 &= ~0x8000;

    t1 &= ~0x8000;

    t0 = (t0 + t1) ^ tmp;

 */

static void gen_add16(TCGv t0, TCGv t1)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_xor_i32(tmp, t0, t1);

    tcg_gen_andi_i32(tmp, tmp, 0x8000);

    tcg_gen_andi_i32(t0, t0, ~0x8000);

    tcg_gen_andi_i32(t1, t1, ~0x8000);

    tcg_gen_add_i32(t0, t0, t1);

    tcg_gen_xor_i32(t0, t0, tmp);

    tcg_temp_free_i32(tmp);

    tcg_temp_free_i32(t1);

}

#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, CF))

/* Set CF to the top bit of var.  */

static void gen_set_CF_bit31(TCGv var)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_shri_i32(tmp, var, 31);

    gen_set_CF(tmp);

    tcg_temp_free_i32(tmp);

}

/* Set N and Z flags from var.  */

static inline void gen_logic_CC(TCGv var)

{

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, NF));

    tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, ZF));

}

/* T0 += T1 + CF.  */

static void gen_adc(TCGv t0, TCGv t1)

{

    TCGv tmp;

    tcg_gen_add_i32(t0, t0, t1);

    tmp = load_cpu_field(CF);

    tcg_gen_add_i32(t0, t0, tmp);

    tcg_temp_free_i32(tmp);

}

/* dest = T0 + T1 + CF. */

static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)

{

    TCGv tmp;

    tcg_gen_add_i32(dest, t0, t1);

    tmp = load_cpu_field(CF);

    tcg_gen_add_i32(dest, dest, tmp);

    tcg_temp_free_i32(tmp);

}

/* dest = T0 - T1 + CF - 1.  */

static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)

{

    TCGv tmp;

    tcg_gen_sub_i32(dest, t0, t1);

    tmp = load_cpu_field(CF);

    tcg_gen_add_i32(dest, dest, tmp);

    tcg_gen_subi_i32(dest, dest, 1);

    tcg_temp_free_i32(tmp);

}

/* FIXME:  Implement this natively.  */

#define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)

static void shifter_out_im(TCGv var, int shift)

{

    TCGv tmp = tcg_temp_new_i32();

    if (shift == 0) {

        tcg_gen_andi_i32(tmp, var, 1);

    } else {

        tcg_gen_shri_i32(tmp, var, shift);

        if (shift != 31)

            tcg_gen_andi_i32(tmp, tmp, 1);

    }

    gen_set_CF(tmp);

    tcg_temp_free_i32(tmp);

}

/* Shift by immediate.  Includes special handling for shift == 0.  */

static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)

{

    switch (shiftop) {

    case 0: /* LSL */

        if (shift != 0) {

            if (flags)

                shifter_out_im(var, 32 - shift);

            tcg_gen_shli_i32(var, var, shift);

        }

        break;

    case 1: /* LSR */

        if (shift == 0) {

            if (flags) {

                tcg_gen_shri_i32(var, var, 31);

                gen_set_CF(var);

            }

            tcg_gen_movi_i32(var, 0);

        } else {

            if (flags)

                shifter_out_im(var, shift - 1);

            tcg_gen_shri_i32(var, var, shift);

        }

        break;

    case 2: /* ASR */

        if (shift == 0)

            shift = 32;

        if (flags)

            shifter_out_im(var, shift - 1);

        if (shift == 32)

          shift = 31;

        tcg_gen_sari_i32(var, var, shift);

        break;

    case 3: /* ROR/RRX */

        if (shift != 0) {

            if (flags)

                shifter_out_im(var, shift - 1);

            tcg_gen_rotri_i32(var, var, shift); break;

        } else {

            TCGv tmp = load_cpu_field(CF);

            if (flags)

                shifter_out_im(var, 0);

            tcg_gen_shri_i32(var, var, 1);

            tcg_gen_shli_i32(tmp, tmp, 31);

            tcg_gen_or_i32(var, var, tmp);

            tcg_temp_free_i32(tmp);

        }

    }

};

static inline void gen_arm_shift_reg(TCGv var, int shiftop,

                                     TCGv shift, int flags)

{

    if (flags) {

        switch (shiftop) {

        case 0: gen_helper_shl_cc(var, var, shift); break;

        case 1: gen_helper_shr_cc(var, var, shift); break;

        case 2: gen_helper_sar_cc(var, var, shift); break;

        case 3: gen_helper_ror_cc(var, var, shift); break;

        }

    } else {

        switch (shiftop) {

        case 0: gen_helper_shl(var, var, shift); break;

        case 1: gen_helper_shr(var, var, shift); break;

        case 2: gen_helper_sar(var, var, shift); break;

        case 3: tcg_gen_andi_i32(shift, shift, 0x1f);

                tcg_gen_rotr_i32(var, var, shift); break;

        }

    }

    tcg_temp_free_i32(shift);

}

#define PAS_OP(pfx) \

    switch (op2) {  \

    case 0: gen_pas_helper(glue(pfx,add16)); break; \

    case 1: gen_pas_helper(glue(pfx,addsubx)); break; \

    case 2: gen_pas_helper(glue(pfx,subaddx)); break; \

    case 3: gen_pas_helper(glue(pfx,sub16)); break; \

    case 4: gen_pas_helper(glue(pfx,add8)); break; \

    case 7: gen_pas_helper(glue(pfx,sub8)); break; \

    }

static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

{

    TCGv_ptr tmp;

    switch (op1) {

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

    case 1:

        tmp = tcg_temp_new_ptr();

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));

        PAS_OP(s)

        tcg_temp_free_ptr(tmp);

        break;

    case 5:

        tmp = tcg_temp_new_ptr();

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));

        PAS_OP(u)

        tcg_temp_free_ptr(tmp);

        break;

#undef gen_pas_helper

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

    case 2:

        PAS_OP(q);

        break;

    case 3:

        PAS_OP(sh);

        break;

    case 6:

        PAS_OP(uq);

        break;

    case 7:

        PAS_OP(uh);

        break;

#undef gen_pas_helper

    }

}

#undef PAS_OP

/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings.  */

#define PAS_OP(pfx) \

    switch (op1) {  \

    case 0: gen_pas_helper(glue(pfx,add8)); break; \

    case 1: gen_pas_helper(glue(pfx,add16)); break; \

    case 2: gen_pas_helper(glue(pfx,addsubx)); break; \

    case 4: gen_pas_helper(glue(pfx,sub8)); break; \

    case 5: gen_pas_helper(glue(pfx,sub16)); break; \

    case 6: gen_pas_helper(glue(pfx,subaddx)); break; \

    }

static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)

{

    TCGv_ptr tmp;

    switch (op2) {

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)

    case 0:

        tmp = tcg_temp_new_ptr();

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));

        PAS_OP(s)

        tcg_temp_free_ptr(tmp);

        break;

    case 4:

        tmp = tcg_temp_new_ptr();

        tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));

        PAS_OP(u)

        tcg_temp_free_ptr(tmp);

        break;

#undef gen_pas_helper

#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)

    case 1:

        PAS_OP(q);

        break;

    case 2:

        PAS_OP(sh);

        break;

    case 5:

        PAS_OP(uq);

        break;

    case 6:

        PAS_OP(uh);

        break;

#undef gen_pas_helper

    }

}

#undef PAS_OP

static void gen_test_cc(int cc, int label)

{

    TCGv tmp;

    TCGv tmp2;

    int inv;

    switch (cc) {

    case 0: /* eq: Z */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 1: /* ne: !Z */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        break;

    case 2: /* cs: C */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        break;

    case 3: /* cc: !C */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 4: /* mi: N */

        tmp = load_cpu_field(NF);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 5: /* pl: !N */

        tmp = load_cpu_field(NF);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 6: /* vs: V */

        tmp = load_cpu_field(VF);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 7: /* vc: !V */

        tmp = load_cpu_field(VF);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 8: /* hi: C && !Z */

        inv = gen_new_label();

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

        tcg_temp_free_i32(tmp);

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);

        gen_set_label(inv);

        break;

    case 9: /* ls: !C || Z */

        tmp = load_cpu_field(CF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        tcg_temp_free_i32(tmp);

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        break;

    case 10: /* ge: N == V -> N ^ V == 0 */

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        tcg_temp_free_i32(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        break;

    case 11: /* lt: N != V -> N ^ V != 0 */

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        tcg_temp_free_i32(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    case 12: /* gt: !Z && N == V */

        inv = gen_new_label();

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);

        tcg_temp_free_i32(tmp);

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        tcg_temp_free_i32(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);

        gen_set_label(inv);

        break;

    case 13: /* le: Z || N != V */

        tmp = load_cpu_field(ZF);

        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);

        tcg_temp_free_i32(tmp);

        tmp = load_cpu_field(VF);

        tmp2 = load_cpu_field(NF);

        tcg_gen_xor_i32(tmp, tmp, tmp2);

        tcg_temp_free_i32(tmp2);

        tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);

        break;

    default:

        fprintf(stderr, "Bad condition code 0x%x\n", cc);

        abort();

    }

    tcg_temp_free_i32(tmp);

}

static const uint8_t table_logic_cc[16] = {

    1, /* and */

    1, /* xor */

    0, /* sub */

    0, /* rsb */

    0, /* add */

    0, /* adc */

    0, /* sbc */

    0, /* rsc */

    1, /* andl */

    1, /* xorl */

    0, /* cmp */

    0, /* cmn */

    1, /* orr */

    1, /* mov */

    1, /* bic */

    1, /* mvn */

};

/* Set PC and Thumb state from an immediate address.  */

static inline void gen_bx_im(DisasContext *s, uint32_t addr)

{

    TCGv tmp;

    s->is_jmp = DISAS_UPDATE;

    if (s->thumb != (addr & 1)) {

        tmp = tcg_temp_new_i32();

        tcg_gen_movi_i32(tmp, addr & 1);

        tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));

        tcg_temp_free_i32(tmp);

    }

    tcg_gen_movi_i32(cpu_R[15], addr & ~1);

}

/* Set PC and Thumb state from var.  var is marked as dead.  */

static inline void gen_bx(DisasContext *s, TCGv var)

{

    s->is_jmp = DISAS_UPDATE;

    tcg_gen_andi_i32(cpu_R[15], var, ~1);

    tcg_gen_andi_i32(var, var, 1);

    store_cpu_field(var, thumb);

}

/* Variant of store_reg which uses branch&exchange logic when storing

   to r15 in ARM architecture v7 and above. The source must be a temporary

   and will be marked as dead. */

static inline void store_reg_bx(CPUARMState *env, DisasContext *s,

                                int reg, TCGv var)

{

    if (reg == 15 && ENABLE_ARCH_7) {

        gen_bx(s, var);

    } else {

        store_reg(s, reg, var);

    }

}

/* Variant of store_reg which uses branch&exchange logic when storing

 * to r15 in ARM architecture v5T and above. This is used for storing

 * the results of a LDR/LDM/POP into r15, and corresponds to the cases

 * in the ARM ARM which use the LoadWritePC() pseudocode function. */

static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,

                                int reg, TCGv var)

{

    if (reg == 15 && ENABLE_ARCH_5) {

        gen_bx(s, var);

    } else {

        store_reg(s, reg, var);

    }

}

static inline TCGv gen_ld8s(TCGv addr, int index)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_qemu_ld8s(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld8u(TCGv addr, int index)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_qemu_ld8u(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld16s(TCGv addr, int index)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_qemu_ld16s(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld16u(TCGv addr, int index)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_qemu_ld16u(tmp, addr, index);

    return tmp;

}

static inline TCGv gen_ld32(TCGv addr, int index)

{

    TCGv tmp = tcg_temp_new_i32();

    tcg_gen_qemu_ld32u(tmp, addr, index);

    return tmp;

}

static inline TCGv_i64 gen_ld64(TCGv addr, int index)

{

    TCGv_i64 tmp = tcg_temp_new_i64();

    tcg_gen_qemu_ld64(tmp, addr, index);

    return tmp;

}

static inline void gen_st8(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st8(val, addr, index);

    tcg_temp_free_i32(val);

}

static inline void gen_st16(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st16(val, addr, index);

    tcg_temp_free_i32(val);

}

static inline void gen_st32(TCGv val, TCGv addr, int index)

{

    tcg_gen_qemu_st32(val, addr, index);

    tcg_temp_free_i32(val);

}

static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)

{

    tcg_gen_qemu_st64(val, addr, index);

    tcg_temp_free_i64(val);

}

static inline void gen_set_pc_im(uint32_t val)

{

    tcg_gen_movi_i32(cpu_R[15], val);

}

/* Force a TB lookup after an instruction that changes the CPU state.  */

static inline void gen_lookup_tb(DisasContext *s)

{

    tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);

    s->is_jmp = DISAS_UPDATE;

}

static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,

                                       TCGv var)

{

    int val, rm, shift, shiftop;

    TCGv offset;

    if (!(insn & (1 << 25))) {

        /* immediate */

        val = insn & 0xfff;

        if (!(insn & (1 << 23)))

            val = -val;

        if (val != 0)

            tcg_gen_addi_i32(var, var, val);

    } else {

        /* shift/register */

        rm = (insn) & 0xf;

        shift = (insn >> 7) & 0x1f;

        shiftop = (insn >> 5) & 3;

        offset = load_reg(s, rm);

        gen_arm_shift_im(offset, shiftop, shift, 0);

        if (!(insn & (1 << 23)))

            tcg_gen_sub_i32(var, var, offset);

        else

            tcg_gen_add_i32(var, var, offset);

        tcg_temp_free_i32(offset);

    }

}

static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,

                                        int extra, TCGv var)

{

    int val, rm;

    TCGv offset;

    if (insn & (1 << 22)) {

        /* immediate */

        val = (insn & 0xf) | ((insn >> 4) & 0xf0);

        if (!(insn & (1 << 23)))

            val = -val;

        val += extra;

        if (val != 0)

            tcg_gen_addi_i32(var, var, val);

    } else {

        /* register */

        if (extra)

            tcg_gen_addi_i32(var, var, extra);

        rm = (insn) & 0xf;

        offset = load_reg(s, rm);

        if (!(insn & (1 << 23)))

            tcg_gen_sub_i32(var, var, offset);