hw: arm_gic_kvm: Add KVM VGIC save/restore logic
Save and restore the ARM KVM VGIC state from the kernel. We rely onQEMU to marshal the GICState data structure and therefore simplysynchronize the kernel state with the QEMU emulated state in bothdirections....
arm: vgic device control api support
Support creating the ARM vgic device through the device control API andsetting the base address for the distributor and cpu interfaces in KVMVMs using this API.
Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be...
hw/intc/arm_gic: Fix GIC_SET_LEVEL
The GIC_SET_LEVEL macro unfortunately overwrote the entire levelbitmask instead of just or'ing on the necessary bits, causing activelevel PPIs on a core to clear PPIs on other cores.
Cc: qemu-stable@nongnu.orgReported-by: Rob Herring <rob.herring@linaro.org>...
hw/intc/exynos4210_combiner: Don't overrun output_irq array in init
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;use the correct constant in the loop initializing our outputsysbus IRQs so that we don't overrun the output_irq[] array....
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140220' into staging
target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as...
hw/intc/arm_gic: Fix NVIC assertion failure
Commit 40d225009ef accidentally changed the behaviour ofgic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,so this meant we hit an assertion: gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed....
qdev: Remove hex8/32/64 property types
Replace them with uint8/32/64.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>Reviewed-by: Eric Blake <eblake@redhat.com>Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
exec: Make cpu_physical_memory_write_rom input an AS
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
arm_gic: Support setting/getting binary point reg
Add a binary_point field to the gic emulation structure and supportsetting/getting this register now when we have it. We don't actuallysupport interrupt grouping yet, oh well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
arm_gic: Add GICC_APRn state to the GICState
The GICC_APRn registers are not currently supported by the ARM GIC v2.0emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRSbased on the maximum number of preemption levels. This patch also adds...
arm_gic: Fix GIC pending behavior
The existing implementation of the pending behavior in gic_set_irq,gic_complete_irq, and the distributor pending set/clear registers doesnot follow the semantics of the GICv2.0 specs, but may implement the11MPCore support. Therefore, maintain the existing semantics for...
arm_gic: Keep track of SGI sources
Right now the arm gic emulation doesn't keep track of the source of anSGI (which apparently Linux guests don't use, or they're fine withassuming CPU 0 always).
Add the necessary matrix on the GICState structure and maintain the data...
arm_gic: Introduce define for GIC_NR_SGIS
Instead of hardcoding 16 various places in the code, use a define tomake it more clear what is going on.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
Fix two bugs that would allow changing the state of SGIs through theICPENDR and ISPENDRs.
Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging
QOM infrastructure fixes and device conversions
arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
TRIGGER can really mean mean anything (e.g. was it triggered, is itlevel-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER tomake the code comprehensible without looking up the data structure....
hw: arm_gic: Introduce gic_set_priority function
To make the code slightly cleaner to look at and make the save/restorecode easier to understand, introduce this function to set the priority ofinterrupts.
apic: Cleanup for QOM'ification
Do some cleanup, including:1. Remove DO_UPCAST() for APICCommonState2. Change DeviceState pointers from 'd' to 'dev', better to understand3. Rename 'register_types' to specifically 'apic_common_register_types'
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>...
apic: QOM'ify APIC
Convert 'init' function to QOM's 'realize' for apic, kvm/apic andxen/xen_apic.
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
icc_bus: QOM'ify ICC
For consistency, QOM'ify APIC's parent bus.
ioapic: Cleanup for QOM'ification
ioapic: QOM'ify ioapic
Convert 'init' function to QOM's 'realize' for ioapic and kvm-ioapic.Change variable 'ioapic_no' from static to global. Then we can dropthe 'instance_no' function argument.
hw: cannot_instantiate_with_device_add_yet due to pointer props
Pointer properties can be set only by code, not by device_add. Adevice with a pointer property can work with device_add only when theproperty may remain null.
This is the case for property "interrupt_vector" of device...
apic: Document why cannot_instantiate_with_device_add_yet
Signed-off-by: Markus Armbruster <armbru@redhat.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <afaerber@suse.de>
isa: Clean up use of cannot_instantiate_with_device_add_yet
Drop it when there's no obvious reason why device_add could not work.Else keep and document why.
qdev: Replace no_user by cannot_instantiate_with_device_add_yet
In an ideal world, machines can be built by wiring devices togetherwith configuration, not code. Unfortunately, that's not the world welive in right now. We still have quite a few devices that need to be...
sysbus: Set cannot_instantiate_with_device_add_yet
device_add plugs devices into suitable bus. For "real" buses, thatactually connects the device. For sysbus, the connections need to bemade separately, and device_add can't do that. The device would be...
spapr-rtas: replace return code constants with macros
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: Alexander Graf <agraf@suse.de>
hw/intc: add allwinner A10 interrupt controller
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com...
realview_gic: Convert to QOM realize
Embed GICState and replace SysBus initfn with realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <afaerber@suse.de>
realview_gic: Prepare for QOM embedding
Move state struct, type constant and cast macro to a new header.
arm_gic: Extract headers hw/intc/arm_gic{,_common}.h
Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h.
xics: convert init() to realize()
This fixes XICS according new QOM rules.
This converts ICS's init() callbacks to realize().
This converts legacy qdev_init_nofail() to property_set(realized).
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Reviewed-by: Andreas Färber <afaerber@suse.de>...
xics: add missing const specifiers to TypeInfo
This adds missing const specifiers to ICS and ICP TypeInfo's.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
xics: split to xics and xics-common
The upcoming XICS-KVM support will use bits of emulated XICS code.So this introduces new level of hierarchy - "xics-common" class. Bothemulated XICS and XICS-KVM will inherit from it and override classcallbacks when required....
xics: add cpu_setup callback
This adds a cpu_setup callback to the XICS device class (as XICS-KVMwill do it different), xics_cpu_setup() will call it if it is set.
xics-kvm: Support for in-kernel XICS interrupt controller
Recent (host) kernels support emulating the PAPR defined "XICS" interruptcontroller system within KVM. This patch allows qemu to initialize andconfigure the in-kernel XICS, and keep its state in sync with qemu's XICS...
xics: Implement H_IPOLL
This adds support for the H_IPOLL hypercall which the guestuses to poll for a pending interrupt. This hypercall ismandatory for PAPR+ and there is no way for the guest todetect whether it is supported or not so just add it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>...
xics: Implement H_XIRR_X
This implements H_XIRR_X hypercall in addition to H_XIRR asit is mandatory for PAPR+ and there is no way for the guest todetect whether it is supported or not so just add it.
As the Partition Adjunct Option is not supported at the moment,...
xics-kvm: enable irqfd for MSI
This enables IRQFD support for sPAPR. The feature decreases the latencyof interrupt handling.
To enable IRQFD for MSI, this sets kvm_gsi_direct_mapping to true whichenables direct MSI mapping.
To enable IRQFD for LSI (level triggered INTx interrupts), a PCI host bus...
xics: move reset and cpu_setup
This simple change makes following patches nicer.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Acked-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
xics: replace fprintf with error_report
This replaces old-style fprintf with new style error_report.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Reviewed-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
xics: add pre_save/post_load dispatchers
The upcoming support of in-kernel XICS will redefine migration callbacksfor both ICS and ICP so classes and callback pointers are added.
QOM device refactorings
xics: move registration of global state to realize()
Registration of global state belongs into realize so move it there.
qom: Pass available size to object_initialize()
To be passed on to object_initialize_with_type().
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (virtio-ccw)Signed-off-by: Andreas Färber <afaerber@suse.de>
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
ioapic: QOM cast cleanup
Signed-off-by: Andreas Färber <afaerber@suse.de>
omap_intc: QOM'ify omap-intc and omap2-intc
Create a new abstract base type and let omap-intc and omap2-intc inheritfrom it. Introduce a type constant and use QOM casts.
pl190: Rename pl190_state to PL190State
pl190: QOM cast cleanup
puv3_intc: QOM cast cleanup
realview_gic: QOM cast cleanup
slavio_intctl: QOM cast cleanup
xilinx_intc: QOM cast cleanup
arm_gic: QOM cast cleanup
etraxfs_pic: QOM cast cleanup
exynos4210_combiner: QOM cast cleanup
exynos4210_gic: QOM cast cleanup for exynos4210.gic
exynos4210_gic: QOM cast cleanup for exynos4210.irq_gate
grlib_irqmp: QOM cast cleanup
lm32_pic: QOM cast cleanup
imx_avic: QOM cast cleanup
Introduce type constant, use QOM casts and prepare SysBus initfn for QOMrealize by resolving SysBusDevice vs. DeviceState "dev" name conflict.
Acked-by: Peter Chubb <peter.chubb@nicta.com.au>Signed-off-by: Andreas Färber <afaerber@suse.de>
xics: rename types to be sane and follow coding style
Basically, in HW the layout of the interrupt network is:
- One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the...
ioapic: Use QOM realize for ioapic
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>[AF: Tweaked error message]Signed-off-by: Andreas Färber <afaerber@suse.de>
pseries: move interrupt controllers to hw/intc/
intc/arm_gic: Build arm_gic only once
Since current_cpu is CPUState it no longer needs CPUArchState.
intc/openpic: Build openpic only once
Since current_cpu is CPUState it no longer depends on CPUPPCState.
Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h becausehw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU.
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
cpu: Replace cpu_single_env with CPUState current_cpu
Move it to qom/cpu.h.
hw/i*: pass owner to memory_region_init* functions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
memory: add owner argument to initialization functions
intc/openpic: Convert to QOM realize
Split qdev initfn into instance_init and realize functions.Change one occurrence of "klass" while at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
intc/openpic_kvm: Fix QOM and build issues
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
openpic: factor out some common defines into openpic.h
...for use by the KVM in-kernel irqchip stub.
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
kvm/openpic: in-kernel mpic support
Enables support for the in-kernel MPIC that thas been merged into theKVM next branch. This includes irqfd/KVM_IRQ_LINE support from AlexGraf (along with some other improvements).
Note from Alex regarding kvm_irqchip_create():...
intc/openpic: QOM'ify
Introduce type constant and cast macro.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Alexander Graf <agraf@suse.de>
intc/xilinx_intc: Handle level interrupt retriggering
Acking a level sensitive interrupt should have no effect if theinterrupt pin is still asserted. The current implementation requiresand edge condition to occur for setting a level sensitive IRQ, which...
intc/xilinx_intc: Inhibit write to ISR when HIE
When the Hardware Interrupt Enable (HIE) bit is set, software cannotchange ISR. Add write guard accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
intc/xilinx_intc: Dont lower IRQ when HIE cleared
This is a little strange. It is lowering the parent IRQ pin on inputwhen HIE is cleared. There is no such behaviour in the real hardware.
ISR changes based on interrupt pin state are already guarded on HIE...
intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pinis lowered. This is incorrect. Only software can clear ISR bits (viaIAR or direct write to ISR with !MER).
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu
intc/xilinx_intc: Use qemu_set_irq
Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). Nofunctional change, just reduces verbosity.
Cc: qemu-trivial@nongnu.org
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
isa: QOM'ify ISADevice
Rename its parent field and use DEVICE where necessary.
i8259: QOM'ify some more
Introduce type constant.
Prepares for PIC realizefn.
i8259: Convert PICCommonState to use QOM realizefn
Instead of having the parent provide PICCommonClass::init,let the children override DeviceClass::realize themselves.This pushes the responsibility of saving and calling the parent'srealizefn to the children....
isa: Use realizefn for ISADevice
Drop ISADeviceClass::init and the resulting no-op initfn and letchildren implement their own realizefn. Adapt error handling.Split off an instance_init where sensible.
apic: rename apic specific bitopts
apic has its own version of bitops, with thedifference that it works on u32 and not long.Add apic_ prefix to avoid namespace clashes.
We should look into reusing standard bitops long-term,but that's not entirely trivial....
Remove Sun4c, Sun4d and a few CPUs
Sun4c and Sun4d architectures and related CPUs are not fully implemented(especially Sun4c MMU) and there has been no interest for them.
Likewise, a few CPUs (Cypress, Ross etc) are only half implemented.
Remove the machines and CPUs, they can be re-added if needed later....
remove double semicolons
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
target-i386: Move APIC to ICC bus
It allows APIC to be hotplugged.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Replace MSI_SPACE_SIZE with APIC_SPACE_SIZE
Put APIC_SPACE_SIZE in a public header so that it can bereused elsewhere later.
i8259: QOM cleanups
Eliminate DO_UPCAST() for PICCommonState. Prepares for ISA realizefn.
Also give the i8259_common type registration functions unique nameswhile at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
ioapic: Replace FROM_SYSBUS() with QOM type cast
arm: fix location of some include files
The recent rearrangement of include files had some minor errors: devices.h is not ARM specific and should not be in arm/ arm.h should be in arm/
Move these two headers to correct this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
Typo, spelling and grammatical fixes
Minor fixes to documentation and code comments.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
hw: move interrupt controllers to hw/intc/, configure with default-configs/
hw: move private headers to hw/ subdirectories.
Many headers are used only in a single directory. These can bekept in hw/.
hw: move target-independent files to subdirectories
This patch tackles all files that are compiled once, movingthem to subdirectories of hw/.
hw: make subdirectories for devices
Prepare the new directory structure.