target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add SIMD ld/st multiple
This adds support support for the SIMD load/storemultiple category of instructions.
This also brings in a couple of helper functions for manipulatingsections of the SIMD registers:
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions.
target-arm: A64: Add decode skeleton for SIMD data processing insns
Add decode skeleton and function placeholders for all the SIMD dataprocessing instructions. Due to the complexity of this part of thetable the normal extract and switch approach gets very messy very...
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).
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