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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.5 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 4.3 kB
helper-a64.h 1.4 kB
helper.c 142.1 kB
helper.h 18.7 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.4 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 175.7 kB
translate.c 366.1 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
f3f8c4f4 01/31/2014 04:47 pm Alex Bennée

target-arm: A64: Add SIMD modified immediate group

This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <>
[AJB: new decode struct, minor bug fixes, optimisation]...
360a6f2d 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD scalar copy instructions

Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
7c51048f 01/31/2014 04:47 pm Michael Matz

target-arm: A64: Add SIMD TBL/TBLX

Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz <>
[PMM: rewritten to do more of the decode in translate-a64.c,
and to do only one 64 bit pass at a time in the helper]...
5fa5469c 01/31/2014 04:47 pm Michael Matz

target-arm: A64: Add SIMD ZIP/UZP/TRN

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz <>
[PMM: use new do_vec_get/set etc functions and generally update to new
codebase standards; refactor to pull per-element loop outside switch]...
4a0ff1ce 01/31/2014 04:47 pm Michael Matz

target-arm: A64: Add SIMD across-lanes instructions

Add support for the SIMD "across lanes" instruction group (C3.6.4).

Signed-off-by: Michael Matz <>
[PMM: Updated to current codebase, added fp min/max ops,
added unallocated encoding checks]...
67bb9389 01/31/2014 04:47 pm Alex Bennée

target-arm: A64: Add SIMD copy operations

This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).

Signed-off-by: Alex Bennée <>
Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
72430bf5 01/31/2014 04:47 pm Alex Bennée

target-arm: A64: Add SIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:

  • do_vec_get - fetch value from a slice of a vector register...
df54e47d 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD ld/st single

Implement the SIMD ld/st single structure instructions.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
384b26fb 01/31/2014 04:47 pm Alex Bennée

target-arm: A64: Add decode skeleton for SIMD data processing insns

Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very...
5c73747f 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD EXT

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>

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