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/*
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 *  MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
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 *
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 *  Copyright (c) 2005 Fabrice Bellard
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 *  Copyright (c) 2008 Intel Corporation  <andrew.zaborowski@intel.com>
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#if SHIFT == 0
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#define Reg MMXReg
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#define XMM_ONLY(...)
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#define B(n) MMX_B(n)
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#define W(n) MMX_W(n)
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#define L(n) MMX_L(n)
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#define Q(n) q
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#define SUFFIX _mmx
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#else
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#define Reg XMMReg
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#define XMM_ONLY(...) __VA_ARGS__
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#define B(n) XMM_B(n)
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#define W(n) XMM_W(n)
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#define L(n) XMM_L(n)
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#define Q(n) XMM_Q(n)
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#define SUFFIX _xmm
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#endif
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void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->W(0) >>= shift;
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        d->W(1) >>= shift;
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        d->W(2) >>= shift;
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        d->W(3) >>= shift;
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#if SHIFT == 1
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        d->W(4) >>= shift;
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        d->W(5) >>= shift;
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        d->W(6) >>= shift;
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        d->W(7) >>= shift;
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#endif
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    }
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}
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void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        shift = 15;
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    } else {
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        shift = s->B(0);
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    }
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    d->W(0) = (int16_t)d->W(0) >> shift;
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    d->W(1) = (int16_t)d->W(1) >> shift;
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    d->W(2) = (int16_t)d->W(2) >> shift;
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    d->W(3) = (int16_t)d->W(3) >> shift;
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#if SHIFT == 1
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    d->W(4) = (int16_t)d->W(4) >> shift;
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    d->W(5) = (int16_t)d->W(5) >> shift;
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    d->W(6) = (int16_t)d->W(6) >> shift;
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    d->W(7) = (int16_t)d->W(7) >> shift;
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#endif
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}
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void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 15) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->W(0) <<= shift;
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        d->W(1) <<= shift;
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        d->W(2) <<= shift;
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        d->W(3) <<= shift;
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#if SHIFT == 1
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        d->W(4) <<= shift;
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        d->W(5) <<= shift;
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        d->W(6) <<= shift;
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        d->W(7) <<= shift;
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#endif
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    }
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}
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void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->L(0) >>= shift;
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        d->L(1) >>= shift;
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#if SHIFT == 1
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        d->L(2) >>= shift;
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        d->L(3) >>= shift;
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#endif
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    }
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}
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void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        shift = 31;
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    } else {
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        shift = s->B(0);
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    }
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    d->L(0) = (int32_t)d->L(0) >> shift;
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    d->L(1) = (int32_t)d->L(1) >> shift;
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#if SHIFT == 1
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    d->L(2) = (int32_t)d->L(2) >> shift;
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    d->L(3) = (int32_t)d->L(3) >> shift;
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#endif
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}
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void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 31) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->L(0) <<= shift;
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        d->L(1) <<= shift;
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#if SHIFT == 1
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        d->L(2) <<= shift;
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        d->L(3) <<= shift;
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#endif
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    }
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}
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void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 63) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->Q(0) >>= shift;
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#if SHIFT == 1
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        d->Q(1) >>= shift;
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#endif
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    }
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}
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void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift;
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    if (s->Q(0) > 63) {
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        d->Q(0) = 0;
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#if SHIFT == 1
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        d->Q(1) = 0;
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#endif
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    } else {
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        shift = s->B(0);
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        d->Q(0) <<= shift;
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#if SHIFT == 1
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        d->Q(1) <<= shift;
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#endif
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    }
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}
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#if SHIFT == 1
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void glue(helper_psrldq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift, i;
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    shift = s->L(0);
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    if (shift > 16)
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        shift = 16;
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    for(i = 0; i < 16 - shift; i++)
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        d->B(i) = d->B(i + shift);
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    for(i = 16 - shift; i < 16; i++)
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        d->B(i) = 0;
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}
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void glue(helper_pslldq, SUFFIX)(Reg *d, Reg *s)
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{
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    int shift, i;
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    shift = s->L(0);
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    if (shift > 16)
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        shift = 16;
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    for(i = 15; i >= shift; i--)
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        d->B(i) = d->B(i - shift);
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    for(i = 0; i < shift; i++)
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        d->B(i) = 0;
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}
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#endif
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#define SSE_HELPER_B(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->B(0) = F(d->B(0), s->B(0));\
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    d->B(1) = F(d->B(1), s->B(1));\
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    d->B(2) = F(d->B(2), s->B(2));\
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    d->B(3) = F(d->B(3), s->B(3));\
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    d->B(4) = F(d->B(4), s->B(4));\
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    d->B(5) = F(d->B(5), s->B(5));\
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    d->B(6) = F(d->B(6), s->B(6));\
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    d->B(7) = F(d->B(7), s->B(7));\
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    XMM_ONLY(\
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    d->B(8) = F(d->B(8), s->B(8));\
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    d->B(9) = F(d->B(9), s->B(9));\
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    d->B(10) = F(d->B(10), s->B(10));\
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    d->B(11) = F(d->B(11), s->B(11));\
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    d->B(12) = F(d->B(12), s->B(12));\
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    d->B(13) = F(d->B(13), s->B(13));\
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    d->B(14) = F(d->B(14), s->B(14));\
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    d->B(15) = F(d->B(15), s->B(15));\
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    )\
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}
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#define SSE_HELPER_W(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->W(0) = F(d->W(0), s->W(0));\
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    d->W(1) = F(d->W(1), s->W(1));\
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    d->W(2) = F(d->W(2), s->W(2));\
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    d->W(3) = F(d->W(3), s->W(3));\
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    XMM_ONLY(\
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    d->W(4) = F(d->W(4), s->W(4));\
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    d->W(5) = F(d->W(5), s->W(5));\
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    d->W(6) = F(d->W(6), s->W(6));\
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    d->W(7) = F(d->W(7), s->W(7));\
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    )\
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}
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#define SSE_HELPER_L(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->L(0) = F(d->L(0), s->L(0));\
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    d->L(1) = F(d->L(1), s->L(1));\
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    XMM_ONLY(\
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    d->L(2) = F(d->L(2), s->L(2));\
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    d->L(3) = F(d->L(3), s->L(3));\
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    )\
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}
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#define SSE_HELPER_Q(name, F)\
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void glue(name, SUFFIX) (Reg *d, Reg *s)\
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{\
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    d->Q(0) = F(d->Q(0), s->Q(0));\
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    XMM_ONLY(\
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    d->Q(1) = F(d->Q(1), s->Q(1));\
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    )\
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}
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#if SHIFT == 0
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static inline int satub(int x)
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{
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    if (x < 0)
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        return 0;
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    else if (x > 255)
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        return 255;
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    else
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        return x;
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}
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static inline int satuw(int x)
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{
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    if (x < 0)
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        return 0;
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    else if (x > 65535)
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        return 65535;
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    else
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        return x;
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}
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static inline int satsb(int x)
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{
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    if (x < -128)
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        return -128;
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    else if (x > 127)
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        return 127;
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    else
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        return x;
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}
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static inline int satsw(int x)
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{
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    if (x < -32768)
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        return -32768;
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    else if (x > 32767)
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        return 32767;
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    else
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        return x;
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}
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#define FADD(a, b) ((a) + (b))
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#define FADDUB(a, b) satub((a) + (b))
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#define FADDUW(a, b) satuw((a) + (b))
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#define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
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#define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
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#define FSUB(a, b) ((a) - (b))
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#define FSUBUB(a, b) satub((a) - (b))
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#define FSUBUW(a, b) satuw((a) - (b))
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#define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
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#define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
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#define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
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#define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
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#define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
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#define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
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#define FAND(a, b) (a) & (b)
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#define FANDN(a, b) ((~(a)) & (b))
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#define FOR(a, b) (a) | (b)
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#define FXOR(a, b) (a) ^ (b)
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#define FCMPGTB(a, b) (int8_t)(a) > (int8_t)(b) ? -1 : 0
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#define FCMPGTW(a, b) (int16_t)(a) > (int16_t)(b) ? -1 : 0
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#define FCMPGTL(a, b) (int32_t)(a) > (int32_t)(b) ? -1 : 0
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#define FCMPEQ(a, b) (a) == (b) ? -1 : 0
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#define FMULLW(a, b) (a) * (b)
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#define FMULHRW(a, b) ((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16
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#define FMULHUW(a, b) (a) * (b) >> 16
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#define FMULHW(a, b) (int16_t)(a) * (int16_t)(b) >> 16
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#define FAVG(a, b) ((a) + (b) + 1) >> 1
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#endif
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SSE_HELPER_B(helper_paddb, FADD)
362 5af45186 bellard
SSE_HELPER_W(helper_paddw, FADD)
363 5af45186 bellard
SSE_HELPER_L(helper_paddl, FADD)
364 5af45186 bellard
SSE_HELPER_Q(helper_paddq, FADD)
365 664e0f19 bellard
366 5af45186 bellard
SSE_HELPER_B(helper_psubb, FSUB)
367 5af45186 bellard
SSE_HELPER_W(helper_psubw, FSUB)
368 5af45186 bellard
SSE_HELPER_L(helper_psubl, FSUB)
369 5af45186 bellard
SSE_HELPER_Q(helper_psubq, FSUB)
370 664e0f19 bellard
371 5af45186 bellard
SSE_HELPER_B(helper_paddusb, FADDUB)
372 5af45186 bellard
SSE_HELPER_B(helper_paddsb, FADDSB)
373 5af45186 bellard
SSE_HELPER_B(helper_psubusb, FSUBUB)
374 5af45186 bellard
SSE_HELPER_B(helper_psubsb, FSUBSB)
375 664e0f19 bellard
376 5af45186 bellard
SSE_HELPER_W(helper_paddusw, FADDUW)
377 5af45186 bellard
SSE_HELPER_W(helper_paddsw, FADDSW)
378 5af45186 bellard
SSE_HELPER_W(helper_psubusw, FSUBUW)
379 5af45186 bellard
SSE_HELPER_W(helper_psubsw, FSUBSW)
380 664e0f19 bellard
381 5af45186 bellard
SSE_HELPER_B(helper_pminub, FMINUB)
382 5af45186 bellard
SSE_HELPER_B(helper_pmaxub, FMAXUB)
383 664e0f19 bellard
384 5af45186 bellard
SSE_HELPER_W(helper_pminsw, FMINSW)
385 5af45186 bellard
SSE_HELPER_W(helper_pmaxsw, FMAXSW)
386 664e0f19 bellard
387 5af45186 bellard
SSE_HELPER_Q(helper_pand, FAND)
388 5af45186 bellard
SSE_HELPER_Q(helper_pandn, FANDN)
389 5af45186 bellard
SSE_HELPER_Q(helper_por, FOR)
390 5af45186 bellard
SSE_HELPER_Q(helper_pxor, FXOR)
391 664e0f19 bellard
392 5af45186 bellard
SSE_HELPER_B(helper_pcmpgtb, FCMPGTB)
393 5af45186 bellard
SSE_HELPER_W(helper_pcmpgtw, FCMPGTW)
394 5af45186 bellard
SSE_HELPER_L(helper_pcmpgtl, FCMPGTL)
395 664e0f19 bellard
396 5af45186 bellard
SSE_HELPER_B(helper_pcmpeqb, FCMPEQ)
397 5af45186 bellard
SSE_HELPER_W(helper_pcmpeqw, FCMPEQ)
398 5af45186 bellard
SSE_HELPER_L(helper_pcmpeql, FCMPEQ)
399 664e0f19 bellard
400 5af45186 bellard
SSE_HELPER_W(helper_pmullw, FMULLW)
401 a35f3ec7 aurel32
#if SHIFT == 0
402 5af45186 bellard
SSE_HELPER_W(helper_pmulhrw, FMULHRW)
403 a35f3ec7 aurel32
#endif
404 5af45186 bellard
SSE_HELPER_W(helper_pmulhuw, FMULHUW)
405 5af45186 bellard
SSE_HELPER_W(helper_pmulhw, FMULHW)
406 664e0f19 bellard
407 5af45186 bellard
SSE_HELPER_B(helper_pavgb, FAVG)
408 5af45186 bellard
SSE_HELPER_W(helper_pavgw, FAVG)
409 664e0f19 bellard
410 5af45186 bellard
void glue(helper_pmuludq, SUFFIX) (Reg *d, Reg *s)
411 664e0f19 bellard
{
412 664e0f19 bellard
    d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0);
413 664e0f19 bellard
#if SHIFT == 1
414 664e0f19 bellard
    d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2);
415 664e0f19 bellard
#endif
416 664e0f19 bellard
}
417 664e0f19 bellard
418 5af45186 bellard
void glue(helper_pmaddwd, SUFFIX) (Reg *d, Reg *s)
419 664e0f19 bellard
{
420 664e0f19 bellard
    int i;
421 664e0f19 bellard
422 664e0f19 bellard
    for(i = 0; i < (2 << SHIFT); i++) {
423 664e0f19 bellard
        d->L(i) = (int16_t)s->W(2*i) * (int16_t)d->W(2*i) +
424 664e0f19 bellard
            (int16_t)s->W(2*i+1) * (int16_t)d->W(2*i+1);
425 664e0f19 bellard
    }
426 664e0f19 bellard
}
427 664e0f19 bellard
428 664e0f19 bellard
#if SHIFT == 0
429 664e0f19 bellard
static inline int abs1(int a)
430 664e0f19 bellard
{
431 664e0f19 bellard
    if (a < 0)
432 664e0f19 bellard
        return -a;
433 664e0f19 bellard
    else
434 664e0f19 bellard
        return a;
435 664e0f19 bellard
}
436 664e0f19 bellard
#endif
437 5af45186 bellard
void glue(helper_psadbw, SUFFIX) (Reg *d, Reg *s)
438 664e0f19 bellard
{
439 664e0f19 bellard
    unsigned int val;
440 664e0f19 bellard
441 664e0f19 bellard
    val = 0;
442 664e0f19 bellard
    val += abs1(d->B(0) - s->B(0));
443 664e0f19 bellard
    val += abs1(d->B(1) - s->B(1));
444 664e0f19 bellard
    val += abs1(d->B(2) - s->B(2));
445 664e0f19 bellard
    val += abs1(d->B(3) - s->B(3));
446 664e0f19 bellard
    val += abs1(d->B(4) - s->B(4));
447 664e0f19 bellard
    val += abs1(d->B(5) - s->B(5));
448 664e0f19 bellard
    val += abs1(d->B(6) - s->B(6));
449 664e0f19 bellard
    val += abs1(d->B(7) - s->B(7));
450 664e0f19 bellard
    d->Q(0) = val;
451 664e0f19 bellard
#if SHIFT == 1
452 664e0f19 bellard
    val = 0;
453 664e0f19 bellard
    val += abs1(d->B(8) - s->B(8));
454 664e0f19 bellard
    val += abs1(d->B(9) - s->B(9));
455 664e0f19 bellard
    val += abs1(d->B(10) - s->B(10));
456 664e0f19 bellard
    val += abs1(d->B(11) - s->B(11));
457 664e0f19 bellard
    val += abs1(d->B(12) - s->B(12));
458 664e0f19 bellard
    val += abs1(d->B(13) - s->B(13));
459 664e0f19 bellard
    val += abs1(d->B(14) - s->B(14));
460 664e0f19 bellard
    val += abs1(d->B(15) - s->B(15));
461 664e0f19 bellard
    d->Q(1) = val;
462 664e0f19 bellard
#endif
463 664e0f19 bellard
}
464 664e0f19 bellard
465 b8b6a50b bellard
void glue(helper_maskmov, SUFFIX) (Reg *d, Reg *s, target_ulong a0)
466 664e0f19 bellard
{
467 664e0f19 bellard
    int i;
468 664e0f19 bellard
    for(i = 0; i < (8 << SHIFT); i++) {
469 664e0f19 bellard
        if (s->B(i) & 0x80)
470 b8b6a50b bellard
            stb(a0 + i, d->B(i));
471 664e0f19 bellard
    }
472 664e0f19 bellard
}
473 664e0f19 bellard
474 5af45186 bellard
void glue(helper_movl_mm_T0, SUFFIX) (Reg *d, uint32_t val)
475 664e0f19 bellard
{
476 5af45186 bellard
    d->L(0) = val;
477 664e0f19 bellard
    d->L(1) = 0;
478 664e0f19 bellard
#if SHIFT == 1
479 664e0f19 bellard
    d->Q(1) = 0;
480 664e0f19 bellard
#endif
481 664e0f19 bellard
}
482 664e0f19 bellard
483 dabd98dd bellard
#ifdef TARGET_X86_64
484 5af45186 bellard
void glue(helper_movq_mm_T0, SUFFIX) (Reg *d, uint64_t val)
485 dabd98dd bellard
{
486 5af45186 bellard
    d->Q(0) = val;
487 dabd98dd bellard
#if SHIFT == 1
488 dabd98dd bellard
    d->Q(1) = 0;
489 dabd98dd bellard
#endif
490 dabd98dd bellard
}
491 dabd98dd bellard
#endif
492 dabd98dd bellard
493 664e0f19 bellard
#if SHIFT == 0
494 5af45186 bellard
void glue(helper_pshufw, SUFFIX) (Reg *d, Reg *s, int order)
495 664e0f19 bellard
{
496 5af45186 bellard
    Reg r;
497 664e0f19 bellard
    r.W(0) = s->W(order & 3);
498 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
499 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
500 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
501 664e0f19 bellard
    *d = r;
502 664e0f19 bellard
}
503 664e0f19 bellard
#else
504 5af45186 bellard
void helper_shufps(Reg *d, Reg *s, int order)
505 d52cf7a6 bellard
{
506 5af45186 bellard
    Reg r;
507 d52cf7a6 bellard
    r.L(0) = d->L(order & 3);
508 d52cf7a6 bellard
    r.L(1) = d->L((order >> 2) & 3);
509 d52cf7a6 bellard
    r.L(2) = s->L((order >> 4) & 3);
510 d52cf7a6 bellard
    r.L(3) = s->L((order >> 6) & 3);
511 d52cf7a6 bellard
    *d = r;
512 d52cf7a6 bellard
}
513 d52cf7a6 bellard
514 5af45186 bellard
void helper_shufpd(Reg *d, Reg *s, int order)
515 664e0f19 bellard
{
516 5af45186 bellard
    Reg r;
517 d52cf7a6 bellard
    r.Q(0) = d->Q(order & 1);
518 664e0f19 bellard
    r.Q(1) = s->Q((order >> 1) & 1);
519 664e0f19 bellard
    *d = r;
520 664e0f19 bellard
}
521 664e0f19 bellard
522 5af45186 bellard
void glue(helper_pshufd, SUFFIX) (Reg *d, Reg *s, int order)
523 664e0f19 bellard
{
524 5af45186 bellard
    Reg r;
525 664e0f19 bellard
    r.L(0) = s->L(order & 3);
526 664e0f19 bellard
    r.L(1) = s->L((order >> 2) & 3);
527 664e0f19 bellard
    r.L(2) = s->L((order >> 4) & 3);
528 664e0f19 bellard
    r.L(3) = s->L((order >> 6) & 3);
529 664e0f19 bellard
    *d = r;
530 664e0f19 bellard
}
531 664e0f19 bellard
532 5af45186 bellard
void glue(helper_pshuflw, SUFFIX) (Reg *d, Reg *s, int order)
533 664e0f19 bellard
{
534 5af45186 bellard
    Reg r;
535 664e0f19 bellard
    r.W(0) = s->W(order & 3);
536 664e0f19 bellard
    r.W(1) = s->W((order >> 2) & 3);
537 664e0f19 bellard
    r.W(2) = s->W((order >> 4) & 3);
538 664e0f19 bellard
    r.W(3) = s->W((order >> 6) & 3);
539 664e0f19 bellard
    r.Q(1) = s->Q(1);
540 664e0f19 bellard
    *d = r;
541 664e0f19 bellard
}
542 664e0f19 bellard
543 5af45186 bellard
void glue(helper_pshufhw, SUFFIX) (Reg *d, Reg *s, int order)
544 664e0f19 bellard
{
545 5af45186 bellard
    Reg r;
546 664e0f19 bellard
    r.Q(0) = s->Q(0);
547 664e0f19 bellard
    r.W(4) = s->W(4 + (order & 3));
548 664e0f19 bellard
    r.W(5) = s->W(4 + ((order >> 2) & 3));
549 664e0f19 bellard
    r.W(6) = s->W(4 + ((order >> 4) & 3));
550 664e0f19 bellard
    r.W(7) = s->W(4 + ((order >> 6) & 3));
551 664e0f19 bellard
    *d = r;
552 664e0f19 bellard
}
553 664e0f19 bellard
#endif
554 664e0f19 bellard
555 664e0f19 bellard
#if SHIFT == 1
556 664e0f19 bellard
/* FPU ops */
557 664e0f19 bellard
/* XXX: not accurate */
558 664e0f19 bellard
559 5af45186 bellard
#define SSE_HELPER_S(name, F)\
560 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
561 664e0f19 bellard
{\
562 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
563 7a0e1f41 bellard
    d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
564 7a0e1f41 bellard
    d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
565 7a0e1f41 bellard
    d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
566 664e0f19 bellard
}\
567 664e0f19 bellard
\
568 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
569 664e0f19 bellard
{\
570 7a0e1f41 bellard
    d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
571 664e0f19 bellard
}\
572 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
573 664e0f19 bellard
{\
574 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
575 7a0e1f41 bellard
    d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
576 664e0f19 bellard
}\
577 664e0f19 bellard
\
578 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
579 664e0f19 bellard
{\
580 7a0e1f41 bellard
    d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
581 664e0f19 bellard
}
582 664e0f19 bellard
583 7a0e1f41 bellard
#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
584 7a0e1f41 bellard
#define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status)
585 7a0e1f41 bellard
#define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status)
586 7a0e1f41 bellard
#define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status)
587 7a0e1f41 bellard
#define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status)
588 664e0f19 bellard
589 a4d1f142 Aurelien Jarno
/* Note that the choice of comparison op here is important to get the
590 a4d1f142 Aurelien Jarno
 * special cases right: for min and max Intel specifies that (-0,0),
591 a4d1f142 Aurelien Jarno
 * (NaN, anything) and (anything, NaN) return the second argument.
592 a4d1f142 Aurelien Jarno
 */
593 a4d1f142 Aurelien Jarno
#define FPU_MIN(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? (a) : (b)
594 a4d1f142 Aurelien Jarno
#define FPU_MAX(size, a, b) float ## size ## _lt(b, a, &env->sse_status) ? (a) : (b)
595 a4d1f142 Aurelien Jarno
596 5af45186 bellard
SSE_HELPER_S(add, FPU_ADD)
597 5af45186 bellard
SSE_HELPER_S(sub, FPU_SUB)
598 5af45186 bellard
SSE_HELPER_S(mul, FPU_MUL)
599 5af45186 bellard
SSE_HELPER_S(div, FPU_DIV)
600 5af45186 bellard
SSE_HELPER_S(min, FPU_MIN)
601 5af45186 bellard
SSE_HELPER_S(max, FPU_MAX)
602 5af45186 bellard
SSE_HELPER_S(sqrt, FPU_SQRT)
603 664e0f19 bellard
604 664e0f19 bellard
605 664e0f19 bellard
/* float to float conversions */
606 5af45186 bellard
void helper_cvtps2pd(Reg *d, Reg *s)
607 664e0f19 bellard
{
608 8422b113 bellard
    float32 s0, s1;
609 664e0f19 bellard
    s0 = s->XMM_S(0);
610 664e0f19 bellard
    s1 = s->XMM_S(1);
611 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
612 7a0e1f41 bellard
    d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
613 664e0f19 bellard
}
614 664e0f19 bellard
615 5af45186 bellard
void helper_cvtpd2ps(Reg *d, Reg *s)
616 664e0f19 bellard
{
617 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
618 7a0e1f41 bellard
    d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status);
619 664e0f19 bellard
    d->Q(1) = 0;
620 664e0f19 bellard
}
621 664e0f19 bellard
622 5af45186 bellard
void helper_cvtss2sd(Reg *d, Reg *s)
623 664e0f19 bellard
{
624 7a0e1f41 bellard
    d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status);
625 664e0f19 bellard
}
626 664e0f19 bellard
627 5af45186 bellard
void helper_cvtsd2ss(Reg *d, Reg *s)
628 664e0f19 bellard
{
629 7a0e1f41 bellard
    d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
630 664e0f19 bellard
}
631 664e0f19 bellard
632 664e0f19 bellard
/* integer to float */
633 5af45186 bellard
void helper_cvtdq2ps(Reg *d, Reg *s)
634 664e0f19 bellard
{
635 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status);
636 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status);
637 7a0e1f41 bellard
    d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status);
638 7a0e1f41 bellard
    d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status);
639 664e0f19 bellard
}
640 664e0f19 bellard
641 5af45186 bellard
void helper_cvtdq2pd(Reg *d, Reg *s)
642 664e0f19 bellard
{
643 664e0f19 bellard
    int32_t l0, l1;
644 664e0f19 bellard
    l0 = (int32_t)s->XMM_L(0);
645 664e0f19 bellard
    l1 = (int32_t)s->XMM_L(1);
646 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
647 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
648 664e0f19 bellard
}
649 664e0f19 bellard
650 5af45186 bellard
void helper_cvtpi2ps(XMMReg *d, MMXReg *s)
651 664e0f19 bellard
{
652 7a0e1f41 bellard
    d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
653 7a0e1f41 bellard
    d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
654 664e0f19 bellard
}
655 664e0f19 bellard
656 5af45186 bellard
void helper_cvtpi2pd(XMMReg *d, MMXReg *s)
657 664e0f19 bellard
{
658 7a0e1f41 bellard
    d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
659 7a0e1f41 bellard
    d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
660 664e0f19 bellard
}
661 664e0f19 bellard
662 5af45186 bellard
void helper_cvtsi2ss(XMMReg *d, uint32_t val)
663 664e0f19 bellard
{
664 5af45186 bellard
    d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
665 664e0f19 bellard
}
666 664e0f19 bellard
667 5af45186 bellard
void helper_cvtsi2sd(XMMReg *d, uint32_t val)
668 664e0f19 bellard
{
669 5af45186 bellard
    d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
670 664e0f19 bellard
}
671 664e0f19 bellard
672 664e0f19 bellard
#ifdef TARGET_X86_64
673 5af45186 bellard
void helper_cvtsq2ss(XMMReg *d, uint64_t val)
674 664e0f19 bellard
{
675 5af45186 bellard
    d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
676 664e0f19 bellard
}
677 664e0f19 bellard
678 5af45186 bellard
void helper_cvtsq2sd(XMMReg *d, uint64_t val)
679 664e0f19 bellard
{
680 5af45186 bellard
    d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
681 664e0f19 bellard
}
682 664e0f19 bellard
#endif
683 664e0f19 bellard
684 664e0f19 bellard
/* float to integer */
685 5af45186 bellard
void helper_cvtps2dq(XMMReg *d, XMMReg *s)
686 664e0f19 bellard
{
687 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
688 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
689 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status);
690 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
691 664e0f19 bellard
}
692 664e0f19 bellard
693 5af45186 bellard
void helper_cvtpd2dq(XMMReg *d, XMMReg *s)
694 664e0f19 bellard
{
695 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
696 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
697 664e0f19 bellard
    d->XMM_Q(1) = 0;
698 664e0f19 bellard
}
699 664e0f19 bellard
700 5af45186 bellard
void helper_cvtps2pi(MMXReg *d, XMMReg *s)
701 664e0f19 bellard
{
702 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
703 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
704 664e0f19 bellard
}
705 664e0f19 bellard
706 5af45186 bellard
void helper_cvtpd2pi(MMXReg *d, XMMReg *s)
707 664e0f19 bellard
{
708 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
709 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
710 664e0f19 bellard
}
711 664e0f19 bellard
712 5af45186 bellard
int32_t helper_cvtss2si(XMMReg *s)
713 664e0f19 bellard
{
714 5af45186 bellard
    return float32_to_int32(s->XMM_S(0), &env->sse_status);
715 664e0f19 bellard
}
716 664e0f19 bellard
717 5af45186 bellard
int32_t helper_cvtsd2si(XMMReg *s)
718 664e0f19 bellard
{
719 5af45186 bellard
    return float64_to_int32(s->XMM_D(0), &env->sse_status);
720 664e0f19 bellard
}
721 664e0f19 bellard
722 664e0f19 bellard
#ifdef TARGET_X86_64
723 5af45186 bellard
int64_t helper_cvtss2sq(XMMReg *s)
724 664e0f19 bellard
{
725 5af45186 bellard
    return float32_to_int64(s->XMM_S(0), &env->sse_status);
726 664e0f19 bellard
}
727 664e0f19 bellard
728 5af45186 bellard
int64_t helper_cvtsd2sq(XMMReg *s)
729 664e0f19 bellard
{
730 5af45186 bellard
    return float64_to_int64(s->XMM_D(0), &env->sse_status);
731 664e0f19 bellard
}
732 664e0f19 bellard
#endif
733 664e0f19 bellard
734 664e0f19 bellard
/* float to integer truncated */
735 5af45186 bellard
void helper_cvttps2dq(XMMReg *d, XMMReg *s)
736 664e0f19 bellard
{
737 7a0e1f41 bellard
    d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
738 7a0e1f41 bellard
    d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
739 7a0e1f41 bellard
    d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status);
740 7a0e1f41 bellard
    d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
741 664e0f19 bellard
}
742 664e0f19 bellard
743 5af45186 bellard
void helper_cvttpd2dq(XMMReg *d, XMMReg *s)
744 664e0f19 bellard
{
745 7a0e1f41 bellard
    d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
746 7a0e1f41 bellard
    d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
747 664e0f19 bellard
    d->XMM_Q(1) = 0;
748 664e0f19 bellard
}
749 664e0f19 bellard
750 5af45186 bellard
void helper_cvttps2pi(MMXReg *d, XMMReg *s)
751 664e0f19 bellard
{
752 7a0e1f41 bellard
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
753 7a0e1f41 bellard
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
754 664e0f19 bellard
}
755 664e0f19 bellard
756 5af45186 bellard
void helper_cvttpd2pi(MMXReg *d, XMMReg *s)
757 664e0f19 bellard
{
758 7a0e1f41 bellard
    d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
759 7a0e1f41 bellard
    d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
760 664e0f19 bellard
}
761 664e0f19 bellard
762 5af45186 bellard
int32_t helper_cvttss2si(XMMReg *s)
763 664e0f19 bellard
{
764 5af45186 bellard
    return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
765 664e0f19 bellard
}
766 664e0f19 bellard
767 5af45186 bellard
int32_t helper_cvttsd2si(XMMReg *s)
768 664e0f19 bellard
{
769 5af45186 bellard
    return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
770 664e0f19 bellard
}
771 664e0f19 bellard
772 664e0f19 bellard
#ifdef TARGET_X86_64
773 5af45186 bellard
int64_t helper_cvttss2sq(XMMReg *s)
774 664e0f19 bellard
{
775 5af45186 bellard
    return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
776 664e0f19 bellard
}
777 664e0f19 bellard
778 5af45186 bellard
int64_t helper_cvttsd2sq(XMMReg *s)
779 664e0f19 bellard
{
780 5af45186 bellard
    return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
781 664e0f19 bellard
}
782 664e0f19 bellard
#endif
783 664e0f19 bellard
784 5af45186 bellard
void helper_rsqrtps(XMMReg *d, XMMReg *s)
785 664e0f19 bellard
{
786 c2ef9a83 Aurelien Jarno
    d->XMM_S(0) = float32_div(float32_one,
787 c2ef9a83 Aurelien Jarno
                              float32_sqrt(s->XMM_S(0), &env->sse_status),
788 c2ef9a83 Aurelien Jarno
                              &env->sse_status);
789 c2ef9a83 Aurelien Jarno
    d->XMM_S(1) = float32_div(float32_one,
790 c2ef9a83 Aurelien Jarno
                              float32_sqrt(s->XMM_S(1), &env->sse_status),
791 c2ef9a83 Aurelien Jarno
                              &env->sse_status);
792 c2ef9a83 Aurelien Jarno
    d->XMM_S(2) = float32_div(float32_one,
793 c2ef9a83 Aurelien Jarno
                              float32_sqrt(s->XMM_S(2), &env->sse_status),
794 c2ef9a83 Aurelien Jarno
                              &env->sse_status);
795 c2ef9a83 Aurelien Jarno
    d->XMM_S(3) = float32_div(float32_one,
796 c2ef9a83 Aurelien Jarno
                              float32_sqrt(s->XMM_S(3), &env->sse_status),
797 c2ef9a83 Aurelien Jarno
                              &env->sse_status);
798 664e0f19 bellard
}
799 664e0f19 bellard
800 5af45186 bellard
void helper_rsqrtss(XMMReg *d, XMMReg *s)
801 664e0f19 bellard
{
802 c2ef9a83 Aurelien Jarno
    d->XMM_S(0) = float32_div(float32_one,
803 c2ef9a83 Aurelien Jarno
                              float32_sqrt(s->XMM_S(0), &env->sse_status),
804 c2ef9a83 Aurelien Jarno
                              &env->sse_status);
805 664e0f19 bellard
}
806 664e0f19 bellard
807 5af45186 bellard
void helper_rcpps(XMMReg *d, XMMReg *s)
808 664e0f19 bellard
{
809 c2ef9a83 Aurelien Jarno
    d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
810 c2ef9a83 Aurelien Jarno
    d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status);
811 c2ef9a83 Aurelien Jarno
    d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status);
812 c2ef9a83 Aurelien Jarno
    d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status);
813 664e0f19 bellard
}
814 664e0f19 bellard
815 5af45186 bellard
void helper_rcpss(XMMReg *d, XMMReg *s)
816 664e0f19 bellard
{
817 c2ef9a83 Aurelien Jarno
    d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
818 664e0f19 bellard
}
819 664e0f19 bellard
820 d9f4bb27 Andre Przywara
static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
821 d9f4bb27 Andre Przywara
{
822 d9f4bb27 Andre Przywara
    uint64_t mask;
823 d9f4bb27 Andre Przywara
824 d9f4bb27 Andre Przywara
    if (len == 0) {
825 d9f4bb27 Andre Przywara
        mask = ~0LL;
826 d9f4bb27 Andre Przywara
    } else {
827 d9f4bb27 Andre Przywara
        mask = (1ULL << len) - 1;
828 d9f4bb27 Andre Przywara
    }
829 d9f4bb27 Andre Przywara
    return (src >> shift) & mask;
830 d9f4bb27 Andre Przywara
}
831 d9f4bb27 Andre Przywara
832 d9f4bb27 Andre Przywara
void helper_extrq_r(XMMReg *d, XMMReg *s)
833 d9f4bb27 Andre Przywara
{
834 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0));
835 d9f4bb27 Andre Przywara
}
836 d9f4bb27 Andre Przywara
837 d9f4bb27 Andre Przywara
void helper_extrq_i(XMMReg *d, int index, int length)
838 d9f4bb27 Andre Przywara
{
839 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length);
840 d9f4bb27 Andre Przywara
}
841 d9f4bb27 Andre Przywara
842 d9f4bb27 Andre Przywara
static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
843 d9f4bb27 Andre Przywara
{
844 d9f4bb27 Andre Przywara
    uint64_t mask;
845 d9f4bb27 Andre Przywara
846 d9f4bb27 Andre Przywara
    if (len == 0) {
847 d9f4bb27 Andre Przywara
        mask = ~0ULL;
848 d9f4bb27 Andre Przywara
    } else {
849 d9f4bb27 Andre Przywara
        mask = (1ULL << len) - 1;
850 d9f4bb27 Andre Przywara
    }
851 d9f4bb27 Andre Przywara
    return (src & ~(mask << shift)) | ((src & mask) << shift);
852 d9f4bb27 Andre Przywara
}
853 d9f4bb27 Andre Przywara
854 d9f4bb27 Andre Przywara
void helper_insertq_r(XMMReg *d, XMMReg *s)
855 d9f4bb27 Andre Przywara
{
856 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8));
857 d9f4bb27 Andre Przywara
}
858 d9f4bb27 Andre Przywara
859 d9f4bb27 Andre Przywara
void helper_insertq_i(XMMReg *d, int index, int length)
860 d9f4bb27 Andre Przywara
{
861 d9f4bb27 Andre Przywara
    d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length);
862 d9f4bb27 Andre Przywara
}
863 d9f4bb27 Andre Przywara
864 5af45186 bellard
void helper_haddps(XMMReg *d, XMMReg *s)
865 664e0f19 bellard
{
866 664e0f19 bellard
    XMMReg r;
867 5c6562c2 Max Reitz
    r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
868 5c6562c2 Max Reitz
    r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
869 5c6562c2 Max Reitz
    r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
870 5c6562c2 Max Reitz
    r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
871 664e0f19 bellard
    *d = r;
872 664e0f19 bellard
}
873 664e0f19 bellard
874 5af45186 bellard
void helper_haddpd(XMMReg *d, XMMReg *s)
875 664e0f19 bellard
{
876 664e0f19 bellard
    XMMReg r;
877 5c6562c2 Max Reitz
    r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
878 5c6562c2 Max Reitz
    r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
879 664e0f19 bellard
    *d = r;
880 664e0f19 bellard
}
881 664e0f19 bellard
882 5af45186 bellard
void helper_hsubps(XMMReg *d, XMMReg *s)
883 664e0f19 bellard
{
884 664e0f19 bellard
    XMMReg r;
885 5c6562c2 Max Reitz
    r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
886 5c6562c2 Max Reitz
    r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
887 5c6562c2 Max Reitz
    r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
888 5c6562c2 Max Reitz
    r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
889 664e0f19 bellard
    *d = r;
890 664e0f19 bellard
}
891 664e0f19 bellard
892 5af45186 bellard
void helper_hsubpd(XMMReg *d, XMMReg *s)
893 664e0f19 bellard
{
894 664e0f19 bellard
    XMMReg r;
895 5c6562c2 Max Reitz
    r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
896 5c6562c2 Max Reitz
    r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
897 664e0f19 bellard
    *d = r;
898 664e0f19 bellard
}
899 664e0f19 bellard
900 5af45186 bellard
void helper_addsubps(XMMReg *d, XMMReg *s)
901 664e0f19 bellard
{
902 5c6562c2 Max Reitz
    d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status);
903 5c6562c2 Max Reitz
    d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status);
904 5c6562c2 Max Reitz
    d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status);
905 5c6562c2 Max Reitz
    d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status);
906 664e0f19 bellard
}
907 664e0f19 bellard
908 5af45186 bellard
void helper_addsubpd(XMMReg *d, XMMReg *s)
909 664e0f19 bellard
{
910 5c6562c2 Max Reitz
    d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status);
911 5c6562c2 Max Reitz
    d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status);
912 664e0f19 bellard
}
913 664e0f19 bellard
914 664e0f19 bellard
/* XXX: unordered */
915 5af45186 bellard
#define SSE_HELPER_CMP(name, F)\
916 5af45186 bellard
void helper_ ## name ## ps (Reg *d, Reg *s)\
917 664e0f19 bellard
{\
918 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
919 8422b113 bellard
    d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1));\
920 8422b113 bellard
    d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2));\
921 8422b113 bellard
    d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3));\
922 664e0f19 bellard
}\
923 664e0f19 bellard
\
924 5af45186 bellard
void helper_ ## name ## ss (Reg *d, Reg *s)\
925 664e0f19 bellard
{\
926 8422b113 bellard
    d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0));\
927 664e0f19 bellard
}\
928 5af45186 bellard
void helper_ ## name ## pd (Reg *d, Reg *s)\
929 664e0f19 bellard
{\
930 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
931 8422b113 bellard
    d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1));\
932 664e0f19 bellard
}\
933 664e0f19 bellard
\
934 5af45186 bellard
void helper_ ## name ## sd (Reg *d, Reg *s)\
935 664e0f19 bellard
{\
936 8422b113 bellard
    d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0));\
937 664e0f19 bellard
}
938 664e0f19 bellard
939 211315fb Aurelien Jarno
#define FPU_CMPEQ(size, a, b) float ## size ## _eq_quiet(a, b, &env->sse_status) ? -1 : 0
940 8422b113 bellard
#define FPU_CMPLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0
941 8422b113 bellard
#define FPU_CMPLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? -1 : 0
942 e0b29ce1 Aurelien Jarno
#define FPU_CMPUNORD(size, a, b) float ## size ## _unordered_quiet(a, b, &env->sse_status) ? - 1 : 0
943 211315fb Aurelien Jarno
#define FPU_CMPNEQ(size, a, b) float ## size ## _eq_quiet(a, b, &env->sse_status) ? 0 : -1
944 8422b113 bellard
#define FPU_CMPNLT(size, a, b) float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1
945 8422b113 bellard
#define FPU_CMPNLE(size, a, b) float ## size ## _le(a, b, &env->sse_status) ? 0 : -1
946 e0b29ce1 Aurelien Jarno
#define FPU_CMPORD(size, a, b) float ## size ## _unordered_quiet(a, b, &env->sse_status) ? 0 : -1
947 664e0f19 bellard
948 5af45186 bellard
SSE_HELPER_CMP(cmpeq, FPU_CMPEQ)
949 5af45186 bellard
SSE_HELPER_CMP(cmplt, FPU_CMPLT)
950 5af45186 bellard
SSE_HELPER_CMP(cmple, FPU_CMPLE)
951 5af45186 bellard
SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD)
952 5af45186 bellard
SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ)
953 5af45186 bellard
SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT)
954 5af45186 bellard
SSE_HELPER_CMP(cmpnle, FPU_CMPNLE)
955 5af45186 bellard
SSE_HELPER_CMP(cmpord, FPU_CMPORD)
956 664e0f19 bellard
957 1e6eec8b Blue Swirl
static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
958 43fb823b bellard
959 5af45186 bellard
void helper_ucomiss(Reg *d, Reg *s)
960 664e0f19 bellard
{
961 43fb823b bellard
    int ret;
962 8422b113 bellard
    float32 s0, s1;
963 664e0f19 bellard
964 664e0f19 bellard
    s0 = d->XMM_S(0);
965 664e0f19 bellard
    s1 = s->XMM_S(0);
966 43fb823b bellard
    ret = float32_compare_quiet(s0, s1, &env->sse_status);
967 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
968 664e0f19 bellard
}
969 664e0f19 bellard
970 5af45186 bellard
void helper_comiss(Reg *d, Reg *s)
971 664e0f19 bellard
{
972 43fb823b bellard
    int ret;
973 8422b113 bellard
    float32 s0, s1;
974 664e0f19 bellard
975 664e0f19 bellard
    s0 = d->XMM_S(0);
976 664e0f19 bellard
    s1 = s->XMM_S(0);
977 43fb823b bellard
    ret = float32_compare(s0, s1, &env->sse_status);
978 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
979 664e0f19 bellard
}
980 664e0f19 bellard
981 5af45186 bellard
void helper_ucomisd(Reg *d, Reg *s)
982 664e0f19 bellard
{
983 43fb823b bellard
    int ret;
984 8422b113 bellard
    float64 d0, d1;
985 664e0f19 bellard
986 664e0f19 bellard
    d0 = d->XMM_D(0);
987 664e0f19 bellard
    d1 = s->XMM_D(0);
988 43fb823b bellard
    ret = float64_compare_quiet(d0, d1, &env->sse_status);
989 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
990 664e0f19 bellard
}
991 664e0f19 bellard
992 5af45186 bellard
void helper_comisd(Reg *d, Reg *s)
993 664e0f19 bellard
{
994 43fb823b bellard
    int ret;
995 8422b113 bellard
    float64 d0, d1;
996 664e0f19 bellard
997 664e0f19 bellard
    d0 = d->XMM_D(0);
998 664e0f19 bellard
    d1 = s->XMM_D(0);
999 43fb823b bellard
    ret = float64_compare(d0, d1, &env->sse_status);
1000 43fb823b bellard
    CC_SRC = comis_eflags[ret + 1];
1001 664e0f19 bellard
}
1002 664e0f19 bellard
1003 5af45186 bellard
uint32_t helper_movmskps(Reg *s)
1004 664e0f19 bellard
{
1005 664e0f19 bellard
    int b0, b1, b2, b3;
1006 664e0f19 bellard
    b0 = s->XMM_L(0) >> 31;
1007 664e0f19 bellard
    b1 = s->XMM_L(1) >> 31;
1008 664e0f19 bellard
    b2 = s->XMM_L(2) >> 31;
1009 664e0f19 bellard
    b3 = s->XMM_L(3) >> 31;
1010 5af45186 bellard
    return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
1011 664e0f19 bellard
}
1012 664e0f19 bellard
1013 5af45186 bellard
uint32_t helper_movmskpd(Reg *s)
1014 664e0f19 bellard
{
1015 664e0f19 bellard
    int b0, b1;
1016 664e0f19 bellard
    b0 = s->XMM_L(1) >> 31;
1017 664e0f19 bellard
    b1 = s->XMM_L(3) >> 31;
1018 5af45186 bellard
    return b0 | (b1 << 1);
1019 664e0f19 bellard
}
1020 664e0f19 bellard
1021 664e0f19 bellard
#endif
1022 664e0f19 bellard
1023 5af45186 bellard
uint32_t glue(helper_pmovmskb, SUFFIX)(Reg *s)
1024 5af45186 bellard
{
1025 5af45186 bellard
    uint32_t val;
1026 5af45186 bellard
    val = 0;
1027 30913bae aurel32
    val |= (s->B(0) >> 7);
1028 30913bae aurel32
    val |= (s->B(1) >> 6) & 0x02;
1029 30913bae aurel32
    val |= (s->B(2) >> 5) & 0x04;
1030 30913bae aurel32
    val |= (s->B(3) >> 4) & 0x08;
1031 30913bae aurel32
    val |= (s->B(4) >> 3) & 0x10;
1032 30913bae aurel32
    val |= (s->B(5) >> 2) & 0x20;
1033 30913bae aurel32
    val |= (s->B(6) >> 1) & 0x40;
1034 30913bae aurel32
    val |= (s->B(7)) & 0x80;
1035 664e0f19 bellard
#if SHIFT == 1
1036 30913bae aurel32
    val |= (s->B(8) << 1) & 0x0100;
1037 30913bae aurel32
    val |= (s->B(9) << 2) & 0x0200;
1038 30913bae aurel32
    val |= (s->B(10) << 3) & 0x0400;
1039 30913bae aurel32
    val |= (s->B(11) << 4) & 0x0800;
1040 30913bae aurel32
    val |= (s->B(12) << 5) & 0x1000;
1041 30913bae aurel32
    val |= (s->B(13) << 6) & 0x2000;
1042 30913bae aurel32
    val |= (s->B(14) << 7) & 0x4000;
1043 30913bae aurel32
    val |= (s->B(15) << 8) & 0x8000;
1044 664e0f19 bellard
#endif
1045 5af45186 bellard
    return val;
1046 664e0f19 bellard
}
1047 664e0f19 bellard
1048 5af45186 bellard
void glue(helper_packsswb, SUFFIX) (Reg *d, Reg *s)
1049 664e0f19 bellard
{
1050 5af45186 bellard
    Reg r;
1051 664e0f19 bellard
1052 664e0f19 bellard
    r.B(0) = satsb((int16_t)d->W(0));
1053 664e0f19 bellard
    r.B(1) = satsb((int16_t)d->W(1));
1054 664e0f19 bellard
    r.B(2) = satsb((int16_t)d->W(2));
1055 664e0f19 bellard
    r.B(3) = satsb((int16_t)d->W(3));
1056 664e0f19 bellard
#if SHIFT == 1
1057 664e0f19 bellard
    r.B(4) = satsb((int16_t)d->W(4));
1058 664e0f19 bellard
    r.B(5) = satsb((int16_t)d->W(5));
1059 664e0f19 bellard
    r.B(6) = satsb((int16_t)d->W(6));
1060 664e0f19 bellard
    r.B(7) = satsb((int16_t)d->W(7));
1061 664e0f19 bellard
#endif
1062 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0));
1063 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1));
1064 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2));
1065 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3));
1066 664e0f19 bellard
#if SHIFT == 1
1067 664e0f19 bellard
    r.B(12) = satsb((int16_t)s->W(4));
1068 664e0f19 bellard
    r.B(13) = satsb((int16_t)s->W(5));
1069 664e0f19 bellard
    r.B(14) = satsb((int16_t)s->W(6));
1070 664e0f19 bellard
    r.B(15) = satsb((int16_t)s->W(7));
1071 664e0f19 bellard
#endif
1072 664e0f19 bellard
    *d = r;
1073 664e0f19 bellard
}
1074 664e0f19 bellard
1075 5af45186 bellard
void glue(helper_packuswb, SUFFIX) (Reg *d, Reg *s)
1076 664e0f19 bellard
{
1077 5af45186 bellard
    Reg r;
1078 664e0f19 bellard
1079 664e0f19 bellard
    r.B(0) = satub((int16_t)d->W(0));
1080 664e0f19 bellard
    r.B(1) = satub((int16_t)d->W(1));
1081 664e0f19 bellard
    r.B(2) = satub((int16_t)d->W(2));
1082 664e0f19 bellard
    r.B(3) = satub((int16_t)d->W(3));
1083 664e0f19 bellard
#if SHIFT == 1
1084 664e0f19 bellard
    r.B(4) = satub((int16_t)d->W(4));
1085 664e0f19 bellard
    r.B(5) = satub((int16_t)d->W(5));
1086 664e0f19 bellard
    r.B(6) = satub((int16_t)d->W(6));
1087 664e0f19 bellard
    r.B(7) = satub((int16_t)d->W(7));
1088 664e0f19 bellard
#endif
1089 664e0f19 bellard
    r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0));
1090 664e0f19 bellard
    r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1));
1091 664e0f19 bellard
    r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2));
1092 664e0f19 bellard
    r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3));
1093 664e0f19 bellard
#if SHIFT == 1
1094 664e0f19 bellard
    r.B(12) = satub((int16_t)s->W(4));
1095 664e0f19 bellard
    r.B(13) = satub((int16_t)s->W(5));
1096 664e0f19 bellard
    r.B(14) = satub((int16_t)s->W(6));
1097 664e0f19 bellard
    r.B(15) = satub((int16_t)s->W(7));
1098 664e0f19 bellard
#endif
1099 664e0f19 bellard
    *d = r;
1100 664e0f19 bellard
}
1101 664e0f19 bellard
1102 5af45186 bellard
void glue(helper_packssdw, SUFFIX) (Reg *d, Reg *s)
1103 664e0f19 bellard
{
1104 5af45186 bellard
    Reg r;
1105 664e0f19 bellard
1106 664e0f19 bellard
    r.W(0) = satsw(d->L(0));
1107 664e0f19 bellard
    r.W(1) = satsw(d->L(1));
1108 664e0f19 bellard
#if SHIFT == 1
1109 664e0f19 bellard
    r.W(2) = satsw(d->L(2));
1110 664e0f19 bellard
    r.W(3) = satsw(d->L(3));
1111 664e0f19 bellard
#endif
1112 664e0f19 bellard
    r.W((2 << SHIFT) + 0) = satsw(s->L(0));
1113 664e0f19 bellard
    r.W((2 << SHIFT) + 1) = satsw(s->L(1));
1114 664e0f19 bellard
#if SHIFT == 1
1115 664e0f19 bellard
    r.W(6) = satsw(s->L(2));
1116 664e0f19 bellard
    r.W(7) = satsw(s->L(3));
1117 664e0f19 bellard
#endif
1118 664e0f19 bellard
    *d = r;
1119 664e0f19 bellard
}
1120 664e0f19 bellard
1121 664e0f19 bellard
#define UNPCK_OP(base_name, base)                               \
1122 664e0f19 bellard
                                                                \
1123 5af45186 bellard
void glue(helper_punpck ## base_name ## bw, SUFFIX) (Reg *d, Reg *s)   \
1124 664e0f19 bellard
{                                                               \
1125 5af45186 bellard
    Reg r;                                              \
1126 664e0f19 bellard
                                                                \
1127 664e0f19 bellard
    r.B(0) = d->B((base << (SHIFT + 2)) + 0);                   \
1128 664e0f19 bellard
    r.B(1) = s->B((base << (SHIFT + 2)) + 0);                   \
1129 664e0f19 bellard
    r.B(2) = d->B((base << (SHIFT + 2)) + 1);                   \
1130 664e0f19 bellard
    r.B(3) = s->B((base << (SHIFT + 2)) + 1);                   \
1131 664e0f19 bellard
    r.B(4) = d->B((base << (SHIFT + 2)) + 2);                   \
1132 664e0f19 bellard
    r.B(5) = s->B((base << (SHIFT + 2)) + 2);                   \
1133 664e0f19 bellard
    r.B(6) = d->B((base << (SHIFT + 2)) + 3);                   \
1134 664e0f19 bellard
    r.B(7) = s->B((base << (SHIFT + 2)) + 3);                   \
1135 664e0f19 bellard
XMM_ONLY(                                                       \
1136 664e0f19 bellard
    r.B(8) = d->B((base << (SHIFT + 2)) + 4);                   \
1137 664e0f19 bellard
    r.B(9) = s->B((base << (SHIFT + 2)) + 4);                   \
1138 664e0f19 bellard
    r.B(10) = d->B((base << (SHIFT + 2)) + 5);                  \
1139 664e0f19 bellard
    r.B(11) = s->B((base << (SHIFT + 2)) + 5);                  \
1140 664e0f19 bellard
    r.B(12) = d->B((base << (SHIFT + 2)) + 6);                  \
1141 664e0f19 bellard
    r.B(13) = s->B((base << (SHIFT + 2)) + 6);                  \
1142 664e0f19 bellard
    r.B(14) = d->B((base << (SHIFT + 2)) + 7);                  \
1143 664e0f19 bellard
    r.B(15) = s->B((base << (SHIFT + 2)) + 7);                  \
1144 664e0f19 bellard
)                                                               \
1145 664e0f19 bellard
    *d = r;                                                     \
1146 664e0f19 bellard
}                                                               \
1147 664e0f19 bellard
                                                                \
1148 5af45186 bellard
void glue(helper_punpck ## base_name ## wd, SUFFIX) (Reg *d, Reg *s)   \
1149 664e0f19 bellard
{                                                               \
1150 5af45186 bellard
    Reg r;                                              \
1151 664e0f19 bellard
                                                                \
1152 664e0f19 bellard
    r.W(0) = d->W((base << (SHIFT + 1)) + 0);                   \
1153 664e0f19 bellard
    r.W(1) = s->W((base << (SHIFT + 1)) + 0);                   \
1154 664e0f19 bellard
    r.W(2) = d->W((base << (SHIFT + 1)) + 1);                   \
1155 664e0f19 bellard
    r.W(3) = s->W((base << (SHIFT + 1)) + 1);                   \
1156 664e0f19 bellard
XMM_ONLY(                                                       \
1157 664e0f19 bellard
    r.W(4) = d->W((base << (SHIFT + 1)) + 2);                   \
1158 664e0f19 bellard
    r.W(5) = s->W((base << (SHIFT + 1)) + 2);                   \
1159 664e0f19 bellard
    r.W(6) = d->W((base << (SHIFT + 1)) + 3);                   \
1160 664e0f19 bellard
    r.W(7) = s->W((base << (SHIFT + 1)) + 3);                   \
1161 664e0f19 bellard
)                                                               \
1162 664e0f19 bellard
    *d = r;                                                     \
1163 664e0f19 bellard
}                                                               \
1164 664e0f19 bellard
                                                                \
1165 5af45186 bellard
void glue(helper_punpck ## base_name ## dq, SUFFIX) (Reg *d, Reg *s)   \
1166 664e0f19 bellard
{                                                               \
1167 5af45186 bellard
    Reg r;                                              \
1168 664e0f19 bellard
                                                                \
1169 664e0f19 bellard
    r.L(0) = d->L((base << SHIFT) + 0);                         \
1170 664e0f19 bellard
    r.L(1) = s->L((base << SHIFT) + 0);                         \
1171 664e0f19 bellard
XMM_ONLY(                                                       \
1172 664e0f19 bellard
    r.L(2) = d->L((base << SHIFT) + 1);                         \
1173 664e0f19 bellard
    r.L(3) = s->L((base << SHIFT) + 1);                         \
1174 664e0f19 bellard
)                                                               \
1175 664e0f19 bellard
    *d = r;                                                     \
1176 664e0f19 bellard
}                                                               \
1177 664e0f19 bellard
                                                                \
1178 664e0f19 bellard
XMM_ONLY(                                                       \
1179 5af45186 bellard
void glue(helper_punpck ## base_name ## qdq, SUFFIX) (Reg *d, Reg *s)  \
1180 664e0f19 bellard
{                                                               \
1181 5af45186 bellard
    Reg r;                                              \
1182 664e0f19 bellard
                                                                \
1183 664e0f19 bellard
    r.Q(0) = d->Q(base);                                        \
1184 664e0f19 bellard
    r.Q(1) = s->Q(base);                                        \
1185 664e0f19 bellard
    *d = r;                                                     \
1186 664e0f19 bellard
}                                                               \
1187 664e0f19 bellard
)
1188 664e0f19 bellard
1189 664e0f19 bellard
UNPCK_OP(l, 0)
1190 664e0f19 bellard
UNPCK_OP(h, 1)
1191 664e0f19 bellard
1192 a35f3ec7 aurel32
/* 3DNow! float ops */
1193 a35f3ec7 aurel32
#if SHIFT == 0
1194 5af45186 bellard
void helper_pi2fd(MMXReg *d, MMXReg *s)
1195 a35f3ec7 aurel32
{
1196 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status);
1197 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status);
1198 a35f3ec7 aurel32
}
1199 a35f3ec7 aurel32
1200 5af45186 bellard
void helper_pi2fw(MMXReg *d, MMXReg *s)
1201 a35f3ec7 aurel32
{
1202 a35f3ec7 aurel32
    d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status);
1203 a35f3ec7 aurel32
    d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status);
1204 a35f3ec7 aurel32
}
1205 a35f3ec7 aurel32
1206 5af45186 bellard
void helper_pf2id(MMXReg *d, MMXReg *s)
1207 a35f3ec7 aurel32
{
1208 a35f3ec7 aurel32
    d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status);
1209 a35f3ec7 aurel32
    d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status);
1210 a35f3ec7 aurel32
}
1211 a35f3ec7 aurel32
1212 5af45186 bellard
void helper_pf2iw(MMXReg *d, MMXReg *s)
1213 a35f3ec7 aurel32
{
1214 a35f3ec7 aurel32
    d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status));
1215 a35f3ec7 aurel32
    d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status));
1216 a35f3ec7 aurel32
}
1217 a35f3ec7 aurel32
1218 5af45186 bellard
void helper_pfacc(MMXReg *d, MMXReg *s)
1219 a35f3ec7 aurel32
{
1220 a35f3ec7 aurel32
    MMXReg r;
1221 a35f3ec7 aurel32
    r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1222 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1223 a35f3ec7 aurel32
    *d = r;
1224 a35f3ec7 aurel32
}
1225 a35f3ec7 aurel32
1226 5af45186 bellard
void helper_pfadd(MMXReg *d, MMXReg *s)
1227 a35f3ec7 aurel32
{
1228 a35f3ec7 aurel32
    d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1229 a35f3ec7 aurel32
    d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1230 a35f3ec7 aurel32
}
1231 a35f3ec7 aurel32
1232 5af45186 bellard
void helper_pfcmpeq(MMXReg *d, MMXReg *s)
1233 a35f3ec7 aurel32
{
1234 211315fb Aurelien Jarno
    d->MMX_L(0) = float32_eq_quiet(d->MMX_S(0), s->MMX_S(0), &env->mmx_status) ? -1 : 0;
1235 211315fb Aurelien Jarno
    d->MMX_L(1) = float32_eq_quiet(d->MMX_S(1), s->MMX_S(1), &env->mmx_status) ? -1 : 0;
1236 a35f3ec7 aurel32
}
1237 a35f3ec7 aurel32
1238 5af45186 bellard
void helper_pfcmpge(MMXReg *d, MMXReg *s)
1239 a35f3ec7 aurel32
{
1240 a35f3ec7 aurel32
    d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1241 a35f3ec7 aurel32
    d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1242 a35f3ec7 aurel32
}
1243 a35f3ec7 aurel32
1244 5af45186 bellard
void helper_pfcmpgt(MMXReg *d, MMXReg *s)
1245 a35f3ec7 aurel32
{
1246 a35f3ec7 aurel32
    d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status) ? -1 : 0;
1247 a35f3ec7 aurel32
    d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status) ? -1 : 0;
1248 a35f3ec7 aurel32
}
1249 a35f3ec7 aurel32
1250 5af45186 bellard
void helper_pfmax(MMXReg *d, MMXReg *s)
1251 a35f3ec7 aurel32
{
1252 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status))
1253 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1254 a35f3ec7 aurel32
    if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status))
1255 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1256 a35f3ec7 aurel32
}
1257 a35f3ec7 aurel32
1258 5af45186 bellard
void helper_pfmin(MMXReg *d, MMXReg *s)
1259 a35f3ec7 aurel32
{
1260 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status))
1261 a35f3ec7 aurel32
        d->MMX_S(0) = s->MMX_S(0);
1262 a35f3ec7 aurel32
    if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status))
1263 a35f3ec7 aurel32
        d->MMX_S(1) = s->MMX_S(1);
1264 a35f3ec7 aurel32
}
1265 a35f3ec7 aurel32
1266 5af45186 bellard
void helper_pfmul(MMXReg *d, MMXReg *s)
1267 a35f3ec7 aurel32
{
1268 a35f3ec7 aurel32
    d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1269 a35f3ec7 aurel32
    d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1270 a35f3ec7 aurel32
}
1271 a35f3ec7 aurel32
1272 5af45186 bellard
void helper_pfnacc(MMXReg *d, MMXReg *s)
1273 a35f3ec7 aurel32
{
1274 a35f3ec7 aurel32
    MMXReg r;
1275 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1276 a35f3ec7 aurel32
    r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1277 a35f3ec7 aurel32
    *d = r;
1278 a35f3ec7 aurel32
}
1279 a35f3ec7 aurel32
1280 5af45186 bellard
void helper_pfpnacc(MMXReg *d, MMXReg *s)
1281 a35f3ec7 aurel32
{
1282 a35f3ec7 aurel32
    MMXReg r;
1283 a35f3ec7 aurel32
    r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1284 a35f3ec7 aurel32
    r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1285 a35f3ec7 aurel32
    *d = r;
1286 a35f3ec7 aurel32
}
1287 a35f3ec7 aurel32
1288 5af45186 bellard
void helper_pfrcp(MMXReg *d, MMXReg *s)
1289 a35f3ec7 aurel32
{
1290 c2ef9a83 Aurelien Jarno
    d->MMX_S(0) = float32_div(float32_one, s->MMX_S(0), &env->mmx_status);
1291 a35f3ec7 aurel32
    d->MMX_S(1) = d->MMX_S(0);
1292 a35f3ec7 aurel32
}
1293 a35f3ec7 aurel32
1294 5af45186 bellard
void helper_pfrsqrt(MMXReg *d, MMXReg *s)
1295 a35f3ec7 aurel32
{
1296 a35f3ec7 aurel32
    d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff;
1297 c2ef9a83 Aurelien Jarno
    d->MMX_S(1) = float32_div(float32_one,
1298 c2ef9a83 Aurelien Jarno
                              float32_sqrt(d->MMX_S(1), &env->mmx_status),
1299 c2ef9a83 Aurelien Jarno
                              &env->mmx_status);
1300 a35f3ec7 aurel32
    d->MMX_L(1) |= s->MMX_L(0) & 0x80000000;
1301 a35f3ec7 aurel32
    d->MMX_L(0) = d->MMX_L(1);
1302 a35f3ec7 aurel32
}
1303 a35f3ec7 aurel32
1304 5af45186 bellard
void helper_pfsub(MMXReg *d, MMXReg *s)
1305 a35f3ec7 aurel32
{
1306 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1307 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1308 a35f3ec7 aurel32
}
1309 a35f3ec7 aurel32
1310 5af45186 bellard
void helper_pfsubr(MMXReg *d, MMXReg *s)
1311 a35f3ec7 aurel32
{
1312 a35f3ec7 aurel32
    d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status);
1313 a35f3ec7 aurel32
    d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status);
1314 a35f3ec7 aurel32
}
1315 a35f3ec7 aurel32
1316 5af45186 bellard
void helper_pswapd(MMXReg *d, MMXReg *s)
1317 a35f3ec7 aurel32
{
1318 a35f3ec7 aurel32
    MMXReg r;
1319 a35f3ec7 aurel32
    r.MMX_L(0) = s->MMX_L(1);
1320 a35f3ec7 aurel32
    r.MMX_L(1) = s->MMX_L(0);
1321 a35f3ec7 aurel32
    *d = r;
1322 a35f3ec7 aurel32
}
1323 a35f3ec7 aurel32
#endif
1324 a35f3ec7 aurel32
1325 4242b1bd balrog
/* SSSE3 op helpers */
1326 4242b1bd balrog
void glue(helper_pshufb, SUFFIX) (Reg *d, Reg *s)
1327 4242b1bd balrog
{
1328 4242b1bd balrog
    int i;
1329 4242b1bd balrog
    Reg r;
1330 4242b1bd balrog
1331 4242b1bd balrog
    for (i = 0; i < (8 << SHIFT); i++)
1332 4242b1bd balrog
        r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1)));
1333 4242b1bd balrog
1334 4242b1bd balrog
    *d = r;
1335 4242b1bd balrog
}
1336 4242b1bd balrog
1337 4242b1bd balrog
void glue(helper_phaddw, SUFFIX) (Reg *d, Reg *s)
1338 4242b1bd balrog
{
1339 4242b1bd balrog
    d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1);
1340 4242b1bd balrog
    d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3);
1341 4242b1bd balrog
    XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5));
1342 4242b1bd balrog
    XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7));
1343 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1);
1344 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3);
1345 4242b1bd balrog
    XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5));
1346 4242b1bd balrog
    XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7));
1347 4242b1bd balrog
}
1348 4242b1bd balrog
1349 4242b1bd balrog
void glue(helper_phaddd, SUFFIX) (Reg *d, Reg *s)
1350 4242b1bd balrog
{
1351 4242b1bd balrog
    d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1);
1352 4242b1bd balrog
    XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3));
1353 4242b1bd balrog
    d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1);
1354 4242b1bd balrog
    XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3));
1355 4242b1bd balrog
}
1356 4242b1bd balrog
1357 4242b1bd balrog
void glue(helper_phaddsw, SUFFIX) (Reg *d, Reg *s)
1358 4242b1bd balrog
{
1359 4242b1bd balrog
    d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1));
1360 4242b1bd balrog
    d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3));
1361 4242b1bd balrog
    XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5)));
1362 4242b1bd balrog
    XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7)));
1363 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1));
1364 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3));
1365 4242b1bd balrog
    XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5)));
1366 4242b1bd balrog
    XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7)));
1367 4242b1bd balrog
}
1368 4242b1bd balrog
1369 4242b1bd balrog
void glue(helper_pmaddubsw, SUFFIX) (Reg *d, Reg *s)
1370 4242b1bd balrog
{
1371 4242b1bd balrog
    d->W(0) = satsw((int8_t)s->B( 0) * (uint8_t)d->B( 0) +
1372 4242b1bd balrog
                    (int8_t)s->B( 1) * (uint8_t)d->B( 1));
1373 4242b1bd balrog
    d->W(1) = satsw((int8_t)s->B( 2) * (uint8_t)d->B( 2) +
1374 4242b1bd balrog
                    (int8_t)s->B( 3) * (uint8_t)d->B( 3));
1375 4242b1bd balrog
    d->W(2) = satsw((int8_t)s->B( 4) * (uint8_t)d->B( 4) +
1376 4242b1bd balrog
                    (int8_t)s->B( 5) * (uint8_t)d->B( 5));
1377 4242b1bd balrog
    d->W(3) = satsw((int8_t)s->B( 6) * (uint8_t)d->B( 6) +
1378 4242b1bd balrog
                    (int8_t)s->B( 7) * (uint8_t)d->B( 7));
1379 4242b1bd balrog
#if SHIFT == 1
1380 4242b1bd balrog
    d->W(4) = satsw((int8_t)s->B( 8) * (uint8_t)d->B( 8) +
1381 4242b1bd balrog
                    (int8_t)s->B( 9) * (uint8_t)d->B( 9));
1382 4242b1bd balrog
    d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) +
1383 4242b1bd balrog
                    (int8_t)s->B(11) * (uint8_t)d->B(11));
1384 4242b1bd balrog
    d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) +
1385 4242b1bd balrog
                    (int8_t)s->B(13) * (uint8_t)d->B(13));
1386 4242b1bd balrog
    d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) +
1387 4242b1bd balrog
                    (int8_t)s->B(15) * (uint8_t)d->B(15));
1388 4242b1bd balrog
#endif
1389 4242b1bd balrog
}
1390 4242b1bd balrog
1391 4242b1bd balrog
void glue(helper_phsubw, SUFFIX) (Reg *d, Reg *s)
1392 4242b1bd balrog
{
1393 4242b1bd balrog
    d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1);
1394 4242b1bd balrog
    d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3);
1395 4242b1bd balrog
    XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5));
1396 4242b1bd balrog
    XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7));
1397 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1);
1398 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3);
1399 4242b1bd balrog
    XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5));
1400 4242b1bd balrog
    XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7));
1401 4242b1bd balrog
}
1402 4242b1bd balrog
1403 4242b1bd balrog
void glue(helper_phsubd, SUFFIX) (Reg *d, Reg *s)
1404 4242b1bd balrog
{
1405 4242b1bd balrog
    d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1);
1406 4242b1bd balrog
    XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3));
1407 4242b1bd balrog
    d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1);
1408 4242b1bd balrog
    XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3));
1409 4242b1bd balrog
}
1410 4242b1bd balrog
1411 4242b1bd balrog
void glue(helper_phsubsw, SUFFIX) (Reg *d, Reg *s)
1412 4242b1bd balrog
{
1413 4242b1bd balrog
    d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1));
1414 4242b1bd balrog
    d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3));
1415 4242b1bd balrog
    XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5)));
1416 4242b1bd balrog
    XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7)));
1417 4242b1bd balrog
    d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1));
1418 4242b1bd balrog
    d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3));
1419 4242b1bd balrog
    XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5)));
1420 4242b1bd balrog
    XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7)));
1421 4242b1bd balrog
}
1422 4242b1bd balrog
1423 4242b1bd balrog
#define FABSB(_, x) x > INT8_MAX  ? -(int8_t ) x : x
1424 4242b1bd balrog
#define FABSW(_, x) x > INT16_MAX ? -(int16_t) x : x
1425 4242b1bd balrog
#define FABSL(_, x) x > INT32_MAX ? -(int32_t) x : x
1426 4242b1bd balrog
SSE_HELPER_B(helper_pabsb, FABSB)
1427 4242b1bd balrog
SSE_HELPER_W(helper_pabsw, FABSW)
1428 4242b1bd balrog
SSE_HELPER_L(helper_pabsd, FABSL)
1429 4242b1bd balrog
1430 4242b1bd balrog
#define FMULHRSW(d, s) ((int16_t) d * (int16_t) s + 0x4000) >> 15
1431 4242b1bd balrog
SSE_HELPER_W(helper_pmulhrsw, FMULHRSW)
1432 4242b1bd balrog
1433 4242b1bd balrog
#define FSIGNB(d, s) s <= INT8_MAX  ? s ? d : 0 : -(int8_t ) d
1434 4242b1bd balrog
#define FSIGNW(d, s) s <= INT16_MAX ? s ? d : 0 : -(int16_t) d
1435 4242b1bd balrog
#define FSIGNL(d, s) s <= INT32_MAX ? s ? d : 0 : -(int32_t) d
1436 4242b1bd balrog
SSE_HELPER_B(helper_psignb, FSIGNB)
1437 4242b1bd balrog
SSE_HELPER_W(helper_psignw, FSIGNW)
1438 4242b1bd balrog
SSE_HELPER_L(helper_psignd, FSIGNL)
1439 4242b1bd balrog
1440 4242b1bd balrog
void glue(helper_palignr, SUFFIX) (Reg *d, Reg *s, int32_t shift)
1441 4242b1bd balrog
{
1442 4242b1bd balrog
    Reg r;
1443 4242b1bd balrog
1444 4242b1bd balrog
    /* XXX could be checked during translation */
1445 4242b1bd balrog
    if (shift >= (16 << SHIFT)) {
1446 4242b1bd balrog
        r.Q(0) = 0;
1447 4242b1bd balrog
        XMM_ONLY(r.Q(1) = 0);
1448 4242b1bd balrog
    } else {
1449 4242b1bd balrog
        shift <<= 3;
1450 4242b1bd balrog
#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
1451 4242b1bd balrog
#if SHIFT == 0
1452 4242b1bd balrog
        r.Q(0) = SHR(s->Q(0), shift -   0) |
1453 4242b1bd balrog
                 SHR(d->Q(0), shift -  64);
1454 4242b1bd balrog
#else
1455 4242b1bd balrog
        r.Q(0) = SHR(s->Q(0), shift -   0) |
1456 4242b1bd balrog
                 SHR(s->Q(1), shift -  64) |
1457 4242b1bd balrog
                 SHR(d->Q(0), shift - 128) |
1458 4242b1bd balrog
                 SHR(d->Q(1), shift - 192);
1459 4242b1bd balrog
        r.Q(1) = SHR(s->Q(0), shift +  64) |
1460 4242b1bd balrog
                 SHR(s->Q(1), shift -   0) |
1461 4242b1bd balrog
                 SHR(d->Q(0), shift -  64) |
1462 4242b1bd balrog
                 SHR(d->Q(1), shift - 128);
1463 4242b1bd balrog
#endif
1464 4242b1bd balrog
#undef SHR
1465 4242b1bd balrog
    }
1466 4242b1bd balrog
1467 4242b1bd balrog
    *d = r;
1468 4242b1bd balrog
}
1469 4242b1bd balrog
1470 222a3336 balrog
#define XMM0 env->xmm_regs[0]
1471 222a3336 balrog
1472 222a3336 balrog
#if SHIFT == 1
1473 222a3336 balrog
#define SSE_HELPER_V(name, elem, num, F)\
1474 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s)\
1475 222a3336 balrog
{\
1476 222a3336 balrog
    d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0));\
1477 222a3336 balrog
    d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1));\
1478 222a3336 balrog
    if (num > 2) {\
1479 222a3336 balrog
        d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2));\
1480 222a3336 balrog
        d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3));\
1481 222a3336 balrog
        if (num > 4) {\
1482 222a3336 balrog
            d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4));\
1483 222a3336 balrog
            d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5));\
1484 222a3336 balrog
            d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6));\
1485 222a3336 balrog
            d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7));\
1486 222a3336 balrog
            if (num > 8) {\
1487 222a3336 balrog
                d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8));\
1488 222a3336 balrog
                d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9));\
1489 222a3336 balrog
                d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10));\
1490 222a3336 balrog
                d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11));\
1491 222a3336 balrog
                d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12));\
1492 222a3336 balrog
                d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13));\
1493 222a3336 balrog
                d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14));\
1494 222a3336 balrog
                d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15));\
1495 222a3336 balrog
            }\
1496 222a3336 balrog
        }\
1497 222a3336 balrog
    }\
1498 222a3336 balrog
}
1499 222a3336 balrog
1500 222a3336 balrog
#define SSE_HELPER_I(name, elem, num, F)\
1501 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s, uint32_t imm)\
1502 222a3336 balrog
{\
1503 222a3336 balrog
    d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1));\
1504 222a3336 balrog
    d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1));\
1505 222a3336 balrog
    if (num > 2) {\
1506 222a3336 balrog
        d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1));\
1507 222a3336 balrog
        d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1));\
1508 222a3336 balrog
        if (num > 4) {\
1509 222a3336 balrog
            d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1));\
1510 222a3336 balrog
            d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1));\
1511 222a3336 balrog
            d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1));\
1512 222a3336 balrog
            d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1));\
1513 222a3336 balrog
            if (num > 8) {\
1514 222a3336 balrog
                d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1));\
1515 222a3336 balrog
                d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1));\
1516 222a3336 balrog
                d->elem(10) = F(d->elem(10), s->elem(10), ((imm >> 10) & 1));\
1517 222a3336 balrog
                d->elem(11) = F(d->elem(11), s->elem(11), ((imm >> 11) & 1));\
1518 222a3336 balrog
                d->elem(12) = F(d->elem(12), s->elem(12), ((imm >> 12) & 1));\
1519 222a3336 balrog
                d->elem(13) = F(d->elem(13), s->elem(13), ((imm >> 13) & 1));\
1520 222a3336 balrog
                d->elem(14) = F(d->elem(14), s->elem(14), ((imm >> 14) & 1));\
1521 222a3336 balrog
                d->elem(15) = F(d->elem(15), s->elem(15), ((imm >> 15) & 1));\
1522 222a3336 balrog
            }\
1523 222a3336 balrog
        }\
1524 222a3336 balrog
    }\
1525 222a3336 balrog
}
1526 222a3336 balrog
1527 222a3336 balrog
/* SSE4.1 op helpers */
1528 222a3336 balrog
#define FBLENDVB(d, s, m) (m & 0x80) ? s : d
1529 222a3336 balrog
#define FBLENDVPS(d, s, m) (m & 0x80000000) ? s : d
1530 000cacf6 balrog
#define FBLENDVPD(d, s, m) (m & 0x8000000000000000LL) ? s : d
1531 222a3336 balrog
SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB)
1532 222a3336 balrog
SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS)
1533 222a3336 balrog
SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD)
1534 222a3336 balrog
1535 222a3336 balrog
void glue(helper_ptest, SUFFIX) (Reg *d, Reg *s)
1536 222a3336 balrog
{
1537 222a3336 balrog
    uint64_t zf = (s->Q(0) &  d->Q(0)) | (s->Q(1) &  d->Q(1));
1538 222a3336 balrog
    uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1));
1539 222a3336 balrog
1540 222a3336 balrog
    CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C);
1541 222a3336 balrog
}
1542 222a3336 balrog
1543 222a3336 balrog
#define SSE_HELPER_F(name, elem, num, F)\
1544 222a3336 balrog
void glue(name, SUFFIX) (Reg *d, Reg *s)\
1545 222a3336 balrog
{\
1546 222a3336 balrog
    d->elem(0) = F(0);\
1547 222a3336 balrog
    d->elem(1) = F(1);\
1548 dcfd12b8 balrog
    if (num > 2) {\
1549 dcfd12b8 balrog
        d->elem(2) = F(2);\
1550 dcfd12b8 balrog
        d->elem(3) = F(3);\
1551 dcfd12b8 balrog
        if (num > 4) {\
1552 dcfd12b8 balrog
            d->elem(4) = F(4);\
1553 dcfd12b8 balrog
            d->elem(5) = F(5);\
1554 222a3336 balrog
            d->elem(6) = F(6);\
1555 222a3336 balrog
            d->elem(7) = F(7);\
1556 222a3336 balrog
        }\
1557 222a3336 balrog
    }\
1558 222a3336 balrog
}
1559 222a3336 balrog
1560 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B)
1561 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B)
1562 222a3336 balrog
SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B)
1563 222a3336 balrog
SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W)
1564 222a3336 balrog
SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W)
1565 222a3336 balrog
SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L)
1566 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B)
1567 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B)
1568 222a3336 balrog
SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B)
1569 222a3336 balrog
SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W)
1570 222a3336 balrog
SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W)
1571 222a3336 balrog
SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L)
1572 222a3336 balrog
1573 222a3336 balrog
void glue(helper_pmuldq, SUFFIX) (Reg *d, Reg *s)
1574 222a3336 balrog
{
1575 222a3336 balrog
    d->Q(0) = (int64_t) (int32_t) d->L(0) * (int32_t) s->L(0);
1576 222a3336 balrog
    d->Q(1) = (int64_t) (int32_t) d->L(2) * (int32_t) s->L(2);
1577 222a3336 balrog
}
1578 222a3336 balrog
1579 222a3336 balrog
#define FCMPEQQ(d, s) d == s ? -1 : 0
1580 222a3336 balrog
SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ)
1581 222a3336 balrog
1582 222a3336 balrog
void glue(helper_packusdw, SUFFIX) (Reg *d, Reg *s)
1583 222a3336 balrog
{
1584 222a3336 balrog
    d->W(0) = satuw((int32_t) d->L(0));
1585 222a3336 balrog
    d->W(1) = satuw((int32_t) d->L(1));
1586 222a3336 balrog
    d->W(2) = satuw((int32_t) d->L(2));
1587 222a3336 balrog
    d->W(3) = satuw((int32_t) d->L(3));
1588 222a3336 balrog
    d->W(4) = satuw((int32_t) s->L(0));
1589 222a3336 balrog
    d->W(5) = satuw((int32_t) s->L(1));
1590 222a3336 balrog
    d->W(6) = satuw((int32_t) s->L(2));
1591 222a3336 balrog
    d->W(7) = satuw((int32_t) s->L(3));
1592 222a3336 balrog
}
1593 222a3336 balrog
1594 222a3336 balrog
#define FMINSB(d, s) MIN((int8_t) d, (int8_t) s)
1595 222a3336 balrog
#define FMINSD(d, s) MIN((int32_t) d, (int32_t) s)
1596 222a3336 balrog
#define FMAXSB(d, s) MAX((int8_t) d, (int8_t) s)
1597 222a3336 balrog
#define FMAXSD(d, s) MAX((int32_t) d, (int32_t) s)
1598 222a3336 balrog
SSE_HELPER_B(helper_pminsb, FMINSB)
1599 222a3336 balrog
SSE_HELPER_L(helper_pminsd, FMINSD)
1600 222a3336 balrog
SSE_HELPER_W(helper_pminuw, MIN)
1601 222a3336 balrog
SSE_HELPER_L(helper_pminud, MIN)
1602 222a3336 balrog
SSE_HELPER_B(helper_pmaxsb, FMAXSB)
1603 222a3336 balrog
SSE_HELPER_L(helper_pmaxsd, FMAXSD)
1604 222a3336 balrog
SSE_HELPER_W(helper_pmaxuw, MAX)
1605 222a3336 balrog
SSE_HELPER_L(helper_pmaxud, MAX)
1606 222a3336 balrog
1607 222a3336 balrog
#define FMULLD(d, s) (int32_t) d * (int32_t) s
1608 222a3336 balrog
SSE_HELPER_L(helper_pmulld, FMULLD)
1609 222a3336 balrog
1610 222a3336 balrog
void glue(helper_phminposuw, SUFFIX) (Reg *d, Reg *s)
1611 222a3336 balrog
{
1612 222a3336 balrog
    int idx = 0;
1613 222a3336 balrog
1614 222a3336 balrog
    if (s->W(1) < s->W(idx))
1615 222a3336 balrog
        idx = 1;
1616 222a3336 balrog
    if (s->W(2) < s->W(idx))
1617 222a3336 balrog
        idx = 2;
1618 222a3336 balrog
    if (s->W(3) < s->W(idx))
1619 222a3336 balrog
        idx = 3;
1620 222a3336 balrog
    if (s->W(4) < s->W(idx))
1621 222a3336 balrog
        idx = 4;
1622 222a3336 balrog
    if (s->W(5) < s->W(idx))
1623 222a3336 balrog
        idx = 5;
1624 222a3336 balrog
    if (s->W(6) < s->W(idx))
1625 222a3336 balrog
        idx = 6;
1626 222a3336 balrog
    if (s->W(7) < s->W(idx))
1627 222a3336 balrog
        idx = 7;
1628 222a3336 balrog
1629 222a3336 balrog
    d->Q(1) = 0;
1630 222a3336 balrog
    d->L(1) = 0;
1631 222a3336 balrog
    d->W(1) = idx;
1632 222a3336 balrog
    d->W(0) = s->W(idx);
1633 222a3336 balrog
}
1634 222a3336 balrog
1635 222a3336 balrog
void glue(helper_roundps, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1636 222a3336 balrog
{
1637 222a3336 balrog
    signed char prev_rounding_mode;
1638 222a3336 balrog
1639 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1640 222a3336 balrog
    if (!(mode & (1 << 2)))
1641 222a3336 balrog
        switch (mode & 3) {
1642 222a3336 balrog
        case 0:
1643 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1644 222a3336 balrog
            break;
1645 222a3336 balrog
        case 1:
1646 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1647 222a3336 balrog
            break;
1648 222a3336 balrog
        case 2:
1649 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1650 222a3336 balrog
            break;
1651 222a3336 balrog
        case 3:
1652 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1653 222a3336 balrog
            break;
1654 222a3336 balrog
        }
1655 222a3336 balrog
1656 adc71666 Aurelien Jarno
    d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
1657 adc71666 Aurelien Jarno
    d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status);
1658 adc71666 Aurelien Jarno
    d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status);
1659 adc71666 Aurelien Jarno
    d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status);
1660 222a3336 balrog
1661 222a3336 balrog
#if 0 /* TODO */
1662 222a3336 balrog
    if (mode & (1 << 3))
1663 222a3336 balrog
        set_float_exception_flags(
1664 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1665 222a3336 balrog
                        ~float_flag_inexact,
1666 222a3336 balrog
                        &env->sse_status);
1667 222a3336 balrog
#endif
1668 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1669 222a3336 balrog
}
1670 222a3336 balrog
1671 222a3336 balrog
void glue(helper_roundpd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1672 222a3336 balrog
{
1673 222a3336 balrog
    signed char prev_rounding_mode;
1674 222a3336 balrog
1675 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1676 222a3336 balrog
    if (!(mode & (1 << 2)))
1677 222a3336 balrog
        switch (mode & 3) {
1678 222a3336 balrog
        case 0:
1679 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1680 222a3336 balrog
            break;
1681 222a3336 balrog
        case 1:
1682 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1683 222a3336 balrog
            break;
1684 222a3336 balrog
        case 2:
1685 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1686 222a3336 balrog
            break;
1687 222a3336 balrog
        case 3:
1688 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1689 222a3336 balrog
            break;
1690 222a3336 balrog
        }
1691 222a3336 balrog
1692 adc71666 Aurelien Jarno
    d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
1693 adc71666 Aurelien Jarno
    d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status);
1694 222a3336 balrog
1695 222a3336 balrog
#if 0 /* TODO */
1696 222a3336 balrog
    if (mode & (1 << 3))
1697 222a3336 balrog
        set_float_exception_flags(
1698 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1699 222a3336 balrog
                        ~float_flag_inexact,
1700 222a3336 balrog
                        &env->sse_status);
1701 222a3336 balrog
#endif
1702 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1703 222a3336 balrog
}
1704 222a3336 balrog
1705 222a3336 balrog
void glue(helper_roundss, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1706 222a3336 balrog
{
1707 222a3336 balrog
    signed char prev_rounding_mode;
1708 222a3336 balrog
1709 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1710 222a3336 balrog
    if (!(mode & (1 << 2)))
1711 222a3336 balrog
        switch (mode & 3) {
1712 222a3336 balrog
        case 0:
1713 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1714 222a3336 balrog
            break;
1715 222a3336 balrog
        case 1:
1716 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1717 222a3336 balrog
            break;
1718 222a3336 balrog
        case 2:
1719 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1720 222a3336 balrog
            break;
1721 222a3336 balrog
        case 3:
1722 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1723 222a3336 balrog
            break;
1724 222a3336 balrog
        }
1725 222a3336 balrog
1726 adc71666 Aurelien Jarno
    d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
1727 222a3336 balrog
1728 222a3336 balrog
#if 0 /* TODO */
1729 222a3336 balrog
    if (mode & (1 << 3))
1730 222a3336 balrog
        set_float_exception_flags(
1731 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1732 222a3336 balrog
                        ~float_flag_inexact,
1733 222a3336 balrog
                        &env->sse_status);
1734 222a3336 balrog
#endif
1735 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1736 222a3336 balrog
}
1737 222a3336 balrog
1738 222a3336 balrog
void glue(helper_roundsd, SUFFIX) (Reg *d, Reg *s, uint32_t mode)
1739 222a3336 balrog
{
1740 222a3336 balrog
    signed char prev_rounding_mode;
1741 222a3336 balrog
1742 222a3336 balrog
    prev_rounding_mode = env->sse_status.float_rounding_mode;
1743 222a3336 balrog
    if (!(mode & (1 << 2)))
1744 222a3336 balrog
        switch (mode & 3) {
1745 222a3336 balrog
        case 0:
1746 222a3336 balrog
            set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1747 222a3336 balrog
            break;
1748 222a3336 balrog
        case 1:
1749 222a3336 balrog
            set_float_rounding_mode(float_round_down, &env->sse_status);
1750 222a3336 balrog
            break;
1751 222a3336 balrog
        case 2:
1752 222a3336 balrog
            set_float_rounding_mode(float_round_up, &env->sse_status);
1753 222a3336 balrog
            break;
1754 222a3336 balrog
        case 3:
1755 222a3336 balrog
            set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1756 222a3336 balrog
            break;
1757 222a3336 balrog
        }
1758 222a3336 balrog
1759 adc71666 Aurelien Jarno
    d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
1760 222a3336 balrog
1761 222a3336 balrog
#if 0 /* TODO */
1762 222a3336 balrog
    if (mode & (1 << 3))
1763 222a3336 balrog
        set_float_exception_flags(
1764 222a3336 balrog
                        get_float_exception_flags(&env->sse_status) &
1765 222a3336 balrog
                        ~float_flag_inexact,
1766 222a3336 balrog
                        &env->sse_status);
1767 222a3336 balrog
#endif
1768 222a3336 balrog
    env->sse_status.float_rounding_mode = prev_rounding_mode;
1769 222a3336 balrog
}
1770 222a3336 balrog
1771 222a3336 balrog
#define FBLENDP(d, s, m) m ? s : d
1772 222a3336 balrog
SSE_HELPER_I(helper_blendps, L, 4, FBLENDP)
1773 222a3336 balrog
SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP)
1774 222a3336 balrog
SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP)
1775 222a3336 balrog
1776 222a3336 balrog
void glue(helper_dpps, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
1777 222a3336 balrog
{
1778 170d5b4b Aurelien Jarno
    float32 iresult = float32_zero;
1779 222a3336 balrog
1780 222a3336 balrog
    if (mask & (1 << 4))
1781 222a3336 balrog
        iresult = float32_add(iresult,
1782 170d5b4b Aurelien Jarno
                        float32_mul(d->XMM_S(0), s->XMM_S(0), &env->sse_status),
1783 222a3336 balrog
                        &env->sse_status);
1784 222a3336 balrog
    if (mask & (1 << 5))
1785 222a3336 balrog
        iresult = float32_add(iresult,
1786 170d5b4b Aurelien Jarno
                        float32_mul(d->XMM_S(1), s->XMM_S(1), &env->sse_status),
1787 222a3336 balrog
                        &env->sse_status);
1788 222a3336 balrog
    if (mask & (1 << 6))
1789 222a3336 balrog
        iresult = float32_add(iresult,
1790 170d5b4b Aurelien Jarno
                        float32_mul(d->XMM_S(2), s->XMM_S(2), &env->sse_status),
1791 222a3336 balrog
                        &env->sse_status);
1792 222a3336 balrog
    if (mask & (1 << 7))
1793 222a3336 balrog
        iresult = float32_add(iresult,
1794 170d5b4b Aurelien Jarno
                        float32_mul(d->XMM_S(3), s->XMM_S(3), &env->sse_status),
1795 222a3336 balrog
                        &env->sse_status);
1796 170d5b4b Aurelien Jarno
    d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero;
1797 170d5b4b Aurelien Jarno
    d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero;
1798 170d5b4b Aurelien Jarno
    d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero;
1799 170d5b4b Aurelien Jarno
    d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero;
1800 222a3336 balrog
}
1801 222a3336 balrog
1802 222a3336 balrog
void glue(helper_dppd, SUFFIX) (Reg *d, Reg *s, uint32_t mask)
1803 222a3336 balrog
{
1804 170d5b4b Aurelien Jarno
    float64 iresult = float64_zero;
1805 222a3336 balrog
1806 222a3336 balrog
    if (mask & (1 << 4))
1807 222a3336 balrog
        iresult = float64_add(iresult,
1808 170d5b4b Aurelien Jarno
                        float64_mul(d->XMM_D(0), s->XMM_D(0), &env->sse_status),
1809 222a3336 balrog
                        &env->sse_status);
1810 222a3336 balrog
    if (mask & (1 << 5))
1811 222a3336 balrog
        iresult = float64_add(iresult,
1812 170d5b4b Aurelien Jarno
                        float64_mul(d->XMM_D(1), s->XMM_D(1), &env->sse_status),
1813 222a3336 balrog
                        &env->sse_status);
1814 170d5b4b Aurelien Jarno
    d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero;
1815 170d5b4b Aurelien Jarno
    d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero;
1816 222a3336 balrog
}
1817 222a3336 balrog
1818 222a3336 balrog
void glue(helper_mpsadbw, SUFFIX) (Reg *d, Reg *s, uint32_t offset)
1819 222a3336 balrog
{
1820 222a3336 balrog
    int s0 = (offset & 3) << 2;
1821 222a3336 balrog
    int d0 = (offset & 4) << 0;
1822 222a3336 balrog
    int i;
1823 222a3336 balrog
    Reg r;
1824 222a3336 balrog
1825 222a3336 balrog
    for (i = 0; i < 8; i++, d0++) {
1826 222a3336 balrog
        r.W(i) = 0;
1827 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0));
1828 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1));
1829 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2));
1830 222a3336 balrog
        r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3));
1831 222a3336 balrog
    }
1832 222a3336 balrog
1833 222a3336 balrog
    *d = r;
1834 222a3336 balrog
}
1835 222a3336 balrog
1836 222a3336 balrog
/* SSE4.2 op helpers */
1837 222a3336 balrog
/* it's unclear whether signed or unsigned */
1838 222a3336 balrog
#define FCMPGTQ(d, s) d > s ? -1 : 0
1839 222a3336 balrog
SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ)
1840 222a3336 balrog
1841 222a3336 balrog
static inline int pcmp_elen(int reg, uint32_t ctrl)
1842 222a3336 balrog
{
1843 222a3336 balrog
    int val;
1844 222a3336 balrog
1845 222a3336 balrog
    /* Presence of REX.W is indicated by a bit higher than 7 set */
1846 222a3336 balrog
    if (ctrl >> 8)
1847 222a3336 balrog
        val = abs1((int64_t) env->regs[reg]);
1848 222a3336 balrog
    else
1849 222a3336 balrog
        val = abs1((int32_t) env->regs[reg]);
1850 222a3336 balrog
1851 222a3336 balrog
    if (ctrl & 1) {
1852 222a3336 balrog
        if (val > 8)
1853 222a3336 balrog
            return 8;
1854 222a3336 balrog
    } else
1855 222a3336 balrog
        if (val > 16)
1856 222a3336 balrog
            return 16;
1857 222a3336 balrog
1858 222a3336 balrog
    return val;
1859 222a3336 balrog
}
1860 222a3336 balrog
1861 222a3336 balrog
static inline int pcmp_ilen(Reg *r, uint8_t ctrl)
1862 222a3336 balrog
{
1863 222a3336 balrog
    int val = 0;
1864 222a3336 balrog
1865 222a3336 balrog
    if (ctrl & 1) {
1866 222a3336 balrog
        while (val < 8 && r->W(val))
1867 222a3336 balrog
            val++;
1868 222a3336 balrog
    } else
1869 222a3336 balrog
        while (val < 16 && r->B(val))
1870 222a3336 balrog
            val++;
1871 222a3336 balrog
1872 222a3336 balrog
    return val;
1873 222a3336 balrog
}
1874 222a3336 balrog
1875 222a3336 balrog
static inline int pcmp_val(Reg *r, uint8_t ctrl, int i)
1876 222a3336 balrog
{
1877 222a3336 balrog
    switch ((ctrl >> 0) & 3) {
1878 222a3336 balrog
    case 0:
1879 222a3336 balrog
        return r->B(i);
1880 222a3336 balrog
    case 1:
1881 222a3336 balrog
        return r->W(i);
1882 222a3336 balrog
    case 2:
1883 222a3336 balrog
        return (int8_t) r->B(i);
1884 222a3336 balrog
    case 3:
1885 222a3336 balrog
    default:
1886 222a3336 balrog
        return (int16_t) r->W(i);
1887 222a3336 balrog
    }
1888 222a3336 balrog
}
1889 222a3336 balrog
1890 222a3336 balrog
static inline unsigned pcmpxstrx(Reg *d, Reg *s,
1891 222a3336 balrog
                int8_t ctrl, int valids, int validd)
1892 222a3336 balrog
{
1893 222a3336 balrog
    unsigned int res = 0;
1894 222a3336 balrog
    int v;
1895 222a3336 balrog
    int j, i;
1896 222a3336 balrog
    int upper = (ctrl & 1) ? 7 : 15;
1897 222a3336 balrog
1898 222a3336 balrog
    valids--;
1899 222a3336 balrog
    validd--;
1900 222a3336 balrog
1901 222a3336 balrog
    CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0);
1902 222a3336 balrog
1903 222a3336 balrog
    switch ((ctrl >> 2) & 3) {
1904 222a3336 balrog
    case 0:
1905 222a3336 balrog
        for (j = valids; j >= 0; j--) {
1906 222a3336 balrog
            res <<= 1;
1907 222a3336 balrog
            v = pcmp_val(s, ctrl, j);
1908 222a3336 balrog
            for (i = validd; i >= 0; i--)
1909 222a3336 balrog
                res |= (v == pcmp_val(d, ctrl, i));
1910 222a3336 balrog
        }
1911 222a3336 balrog
        break;
1912 222a3336 balrog
    case 1:
1913 222a3336 balrog
        for (j = valids; j >= 0; j--) {
1914 222a3336 balrog
            res <<= 1;
1915 222a3336 balrog
            v = pcmp_val(s, ctrl, j);
1916 222a3336 balrog
            for (i = ((validd - 1) | 1); i >= 0; i -= 2)
1917 222a3336 balrog
                res |= (pcmp_val(d, ctrl, i - 0) <= v &&
1918 222a3336 balrog
                        pcmp_val(d, ctrl, i - 1) >= v);
1919 222a3336 balrog
        }
1920 222a3336 balrog
        break;
1921 222a3336 balrog
    case 2:
1922 222a3336 balrog
        res = (2 << (upper - MAX(valids, validd))) - 1;
1923 222a3336 balrog
        res <<= MAX(valids, validd) - MIN(valids, validd);
1924 222a3336 balrog
        for (i = MIN(valids, validd); i >= 0; i--) {
1925 222a3336 balrog
            res <<= 1;
1926 222a3336 balrog
            v = pcmp_val(s, ctrl, i);
1927 222a3336 balrog
            res |= (v == pcmp_val(d, ctrl, i));
1928 222a3336 balrog
        }
1929 222a3336 balrog
        break;
1930 222a3336 balrog
    case 3:
1931 222a3336 balrog
        for (j = valids - validd; j >= 0; j--) {
1932 222a3336 balrog
            res <<= 1;
1933 222a3336 balrog
            res |= 1;
1934 222a3336 balrog
            for (i = MIN(upper - j, validd); i >= 0; i--)
1935 222a3336 balrog
                res &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i));
1936 222a3336 balrog
        }
1937 222a3336 balrog
        break;
1938 222a3336 balrog
    }
1939 222a3336 balrog
1940 222a3336 balrog
    switch ((ctrl >> 4) & 3) {
1941 222a3336 balrog
    case 1:
1942 222a3336 balrog
        res ^= (2 << upper) - 1;
1943 222a3336 balrog
        break;
1944 222a3336 balrog
    case 3:
1945 222a3336 balrog
        res ^= (2 << valids) - 1;
1946 222a3336 balrog
        break;
1947 222a3336 balrog
    }
1948 222a3336 balrog
1949 222a3336 balrog
    if (res)
1950 222a3336 balrog
       CC_SRC |= CC_C;
1951 222a3336 balrog
    if (res & 1)
1952 222a3336 balrog
       CC_SRC |= CC_O;
1953 222a3336 balrog
1954 222a3336 balrog
    return res;
1955 222a3336 balrog
}
1956 222a3336 balrog
1957 222a3336 balrog
static inline int rffs1(unsigned int val)
1958 222a3336 balrog
{
1959 222a3336 balrog
    int ret = 1, hi;
1960 222a3336 balrog
1961 222a3336 balrog
    for (hi = sizeof(val) * 4; hi; hi /= 2)
1962 222a3336 balrog
        if (val >> hi) {
1963 222a3336 balrog
            val >>= hi;
1964 222a3336 balrog
            ret += hi;
1965 222a3336 balrog
        }
1966 222a3336 balrog
1967 222a3336 balrog
    return ret;
1968 222a3336 balrog
}
1969 222a3336 balrog
1970 222a3336 balrog
static inline int ffs1(unsigned int val)
1971 222a3336 balrog
{
1972 222a3336 balrog
    int ret = 1, hi;
1973 222a3336 balrog
1974 222a3336 balrog
    for (hi = sizeof(val) * 4; hi; hi /= 2)
1975 222a3336 balrog
        if (val << hi) {
1976 222a3336 balrog
            val <<= hi;
1977 222a3336 balrog
            ret += hi;
1978 222a3336 balrog
        }
1979 222a3336 balrog
1980 222a3336 balrog
    return ret;
1981 222a3336 balrog
}
1982 222a3336 balrog
1983 222a3336 balrog
void glue(helper_pcmpestri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
1984 222a3336 balrog
{
1985 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
1986 222a3336 balrog
                    pcmp_elen(R_EDX, ctrl),
1987 222a3336 balrog
                    pcmp_elen(R_EAX, ctrl));
1988 222a3336 balrog
1989 222a3336 balrog
    if (res)
1990 222a3336 balrog
        env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
1991 222a3336 balrog
    else
1992 222a3336 balrog
        env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
1993 222a3336 balrog
}
1994 222a3336 balrog
1995 222a3336 balrog
void glue(helper_pcmpestrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
1996 222a3336 balrog
{
1997 222a3336 balrog
    int i;
1998 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
1999 222a3336 balrog
                    pcmp_elen(R_EDX, ctrl),
2000 222a3336 balrog
                    pcmp_elen(R_EAX, ctrl));
2001 222a3336 balrog
2002 222a3336 balrog
    if ((ctrl >> 6) & 1) {
2003 222a3336 balrog
        if (ctrl & 1)
2004 bc426899 Blue Swirl
            for (i = 0; i < 8; i++, res >>= 1) {
2005 222a3336 balrog
                d->W(i) = (res & 1) ? ~0 : 0;
2006 bc426899 Blue Swirl
            }
2007 222a3336 balrog
        else
2008 bc426899 Blue Swirl
            for (i = 0; i < 16; i++, res >>= 1) {
2009 222a3336 balrog
                d->B(i) = (res & 1) ? ~0 : 0;
2010 bc426899 Blue Swirl
            }
2011 222a3336 balrog
    } else {
2012 222a3336 balrog
        d->Q(1) = 0;
2013 222a3336 balrog
        d->Q(0) = res;
2014 222a3336 balrog
    }
2015 222a3336 balrog
}
2016 222a3336 balrog
2017 222a3336 balrog
void glue(helper_pcmpistri, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
2018 222a3336 balrog
{
2019 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
2020 222a3336 balrog
                    pcmp_ilen(s, ctrl),
2021 222a3336 balrog
                    pcmp_ilen(d, ctrl));
2022 222a3336 balrog
2023 222a3336 balrog
    if (res)
2024 222a3336 balrog
        env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
2025 222a3336 balrog
    else
2026 222a3336 balrog
        env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
2027 222a3336 balrog
}
2028 222a3336 balrog
2029 222a3336 balrog
void glue(helper_pcmpistrm, SUFFIX) (Reg *d, Reg *s, uint32_t ctrl)
2030 222a3336 balrog
{
2031 222a3336 balrog
    int i;
2032 222a3336 balrog
    unsigned int res = pcmpxstrx(d, s, ctrl,
2033 222a3336 balrog
                    pcmp_ilen(s, ctrl),
2034 222a3336 balrog
                    pcmp_ilen(d, ctrl));
2035 222a3336 balrog
2036 222a3336 balrog
    if ((ctrl >> 6) & 1) {
2037 222a3336 balrog
        if (ctrl & 1)
2038 bc426899 Blue Swirl
            for (i = 0; i < 8; i++, res >>= 1) {
2039 222a3336 balrog
                d->W(i) = (res & 1) ? ~0 : 0;
2040 bc426899 Blue Swirl
            }
2041 222a3336 balrog
        else
2042 bc426899 Blue Swirl
            for (i = 0; i < 16; i++, res >>= 1) {
2043 222a3336 balrog
                d->B(i) = (res & 1) ? ~0 : 0;
2044 bc426899 Blue Swirl
            }
2045 222a3336 balrog
    } else {
2046 222a3336 balrog
        d->Q(1) = 0;
2047 222a3336 balrog
        d->Q(0) = res;
2048 222a3336 balrog
    }
2049 222a3336 balrog
}
2050 222a3336 balrog
2051 222a3336 balrog
#define CRCPOLY        0x1edc6f41
2052 222a3336 balrog
#define CRCPOLY_BITREV 0x82f63b78
2053 222a3336 balrog
target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len)
2054 222a3336 balrog
{
2055 222a3336 balrog
    target_ulong crc = (msg & ((target_ulong) -1 >>
2056 222a3336 balrog
                            (TARGET_LONG_BITS - len))) ^ crc1;
2057 222a3336 balrog
2058 222a3336 balrog
    while (len--)
2059 222a3336 balrog
        crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0);
2060 222a3336 balrog
2061 222a3336 balrog
    return crc;
2062 222a3336 balrog
}
2063 222a3336 balrog
2064 222a3336 balrog
#define POPMASK(i)     ((target_ulong) -1 / ((1LL << (1 << i)) + 1))
2065 222a3336 balrog
#define POPCOUNT(n, i) (n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i))
2066 222a3336 balrog
target_ulong helper_popcnt(target_ulong n, uint32_t type)
2067 222a3336 balrog
{
2068 222a3336 balrog
    CC_SRC = n ? 0 : CC_Z;
2069 222a3336 balrog
2070 222a3336 balrog
    n = POPCOUNT(n, 0);
2071 222a3336 balrog
    n = POPCOUNT(n, 1);
2072 222a3336 balrog
    n = POPCOUNT(n, 2);
2073 222a3336 balrog
    n = POPCOUNT(n, 3);
2074 222a3336 balrog
    if (type == 1)
2075 222a3336 balrog
        return n & 0xff;
2076 222a3336 balrog
2077 222a3336 balrog
    n = POPCOUNT(n, 4);
2078 222a3336 balrog
#ifndef TARGET_X86_64
2079 222a3336 balrog
    return n;
2080 222a3336 balrog
#else
2081 222a3336 balrog
    if (type == 2)
2082 222a3336 balrog
        return n & 0xff;
2083 222a3336 balrog
2084 222a3336 balrog
    return POPCOUNT(n, 5);
2085 222a3336 balrog
#endif
2086 222a3336 balrog
}
2087 222a3336 balrog
#endif
2088 222a3336 balrog
2089 664e0f19 bellard
#undef SHIFT
2090 664e0f19 bellard
#undef XMM_ONLY
2091 664e0f19 bellard
#undef Reg
2092 664e0f19 bellard
#undef B
2093 664e0f19 bellard
#undef W
2094 664e0f19 bellard
#undef L
2095 664e0f19 bellard
#undef Q
2096 664e0f19 bellard
#undef SUFFIX