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# Date Author Comment
d07fee7e 03/15/2012 02:12 pm David Gibson

pseries: Add support for level interrupts to XICS

The pseries "xics" interrupt controller, like most interrupt
controllers can support both message (i.e. edge sensitive) interrupts
and level sensitive interrupts, but it needs to know which are which.

When I implemented the xics emulation for qemu, the only devices we...
c7a5c0c9 04/08/2011 12:32 pm David Gibson

pseries: Abolish envs array

Currently the pseries machine init code builds up an array, envs, of
CPUState pointers for all the cpus in the system. This is kind of
pointless, given the generic code already has a perfectly good linked list
of the cpus.

In addition, there are a number of places which assume that the cpu's...
b5cec4c5 04/01/2011 07:34 pm David Gibson

Implement the PAPR (pSeries) virtualized interrupt controller (xics)

PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular "interrupt server", i.e. CPU) and...