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target-arm: Fix use of free() in cpu_arm_close()
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
rsqrte_f32: No need to copy sign bit.
Indeed, the result is known to be always positive.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Fix typo
The command line option is called -kernel, not -kenrel.
Cc: Paul Brook <paul@codesourcery.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge remote-tracking branch 'pm-arm/for-upstream' into pm
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
target-arm: support for ARM1176JZF-s cores
Add support for v6K ARM1176JZF-S. This core includes the VA<->PAtranslation capability and security extensions.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,thus enabling the TLS registers, NOP hints, CLREX, half and byte wideexclusive load/stores, etc.
The VA-to-PA translation registers are not present on 1136r1, so...
target-arm: make VMSAv7 remapping and AP dependent on V6K
The VMSAv7 remapping and access permissions were introduced in ARMv6Kand not ARMv7.
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access
Correct the decode of the register numbers for BASEPRI, BASEPRI_MAXand FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR".
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>...
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010
Signed-off-by: Alex Zuepke <azuepke@sysgo.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Signal Underflow when denormal flushed to zero on output
On ARM the architecture mandates that when an output denormal is flushed tozero we must set the FPSCR UFC (underflow) bit, so map softfloat'sfloat_flag_output_denormal accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTS
The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormalsas special cases, so we must set the InputDenormal exception flag ourselves.
target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fns
The functions which do the core estimation algorithms for the VRSQRTEand VRECPE instructions should not set floating point exception flags,so use a local fp status for doing these calculations....
target-arm: Set Invalid flag for NaN in float-to-int conversions
When we catch the special case of an input NaN in ARM float to inthelper functions, set the Invalid flag as well as returning thecorrect result.
Implement basic part of SA-1110/SA-1100
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x
Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix some typos in comments and documentation
helpfull -> helpfulusefull -> usefulcotrol -> control
and a grammar fix.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Detect tininess before rounding for FP operations
The ARM architecture mandates that we detect tininess before rounding,so set the softfloat fp_status up appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
target-arm/helper.c: For float-int conversion helpers pass ints as ints
Correct the argument and return types for the float<->int conversion helperfunctions so that integer arguments and return values are declared asuint32_t/uint64_t, not float32/float64. This allows us to remove the...
target-arm: use make_float32() to make constant floats for VRSQRTS
The preferred way to create a constant floating point value is to usemake_float32() rather than doing a runtime int32_to_float32().Convert the code in the VRSQRTS helper to work this way....
target-arm: Fix VRECPS edge cases handling
Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0
target-arm: Fix GE bits for v6media signed modulo arithmetic
Fix the signed modulo arithmetic helpers for the v6mediainstructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to setthe GE bits correctly (based on the result of the add or subtractbefore it is truncated to 16 bits, not after)....
target-arm: Implement cp15 VA->PA translation
Implement VA->PA translations by cp15-c7 that went through unchangedpreviously.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Introduce float64_256 and float64_512 constants.
These two constants will be used by helper functions such as recpe_f32and rsqrte_f32.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix support for VRECPE.
Now use the same algorithm as described in the ARM ARM.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix support for VRSQRTE.
target-arm: Silence NaNs resulting from half-precision conversions
Silence the NaNs that may result from half-precision conversion,as we do for the other conversions.
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
softfloat: Add float16 type and float16 NaN handling functions
Add a float16 type to softfloat, rather than using bits16 directly.Also add the missing functions float16_is_quiet_nan(),float16_is_signaling_nan() and float16_maybe_silence_nan(),which are needed for the float16 conversion routines....
target-arm: Clean up handling of MPIDR
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architectureas the MPIDR. Clean up its implementation to remove A9 specific handling.
This commit includes fixing an error in the value returned for theMPIDR on A9, where we were erroneously claiming a cluster ID of 9....
target-arm: Add CPU feature flag for v7MP
Add a CPU feature flag for v7MP (the multiprocessing extensions); someinstructions exist only for v7MP and not for the base v7 architecture.
target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates(3 - op1 * op2) / 2) was missing the division operation. It alsodid not handle the special cases of (0,inf) and (inf,0).
target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status valuewhich should be used for operations which the ARM ARM indicates use"ARM standard floating-point arithmetic" rather than being controlled...
target-arm: Use the standard FPSCR value for VRSQRTS
VSQRTS always uses the standard FPSCR value as it is a Neon instruction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registersto stack of current mode" case in the helper function rather thaninline. This means the generated code does not make assumptions...
target-arm: Set softfloat cumulative exc flags from correct FPSCR bits
When handling a write to the ARM FPSCR, set the softfloat cumulativeexception flags from the cumulative flags in the FPSCR, not theexception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host...
target-arm: wire up the softfloat flush_input_to_zero flag
Wire up the new softfloat support for flushing input denormalsto zero on ARM. The FPSCR FZ bit enables flush-to-zero forboth inputs and outputs, but the reporting of when inputs areflushed to zero is via a separate IDC bit rather than the UFC...
target-arm: correct cp15 c1_sys reset value for cortex-a8
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translationtable descriptors assigned to manager domains.
ARM: Return correct result for float-to-integer conversion of NaN
The ARM architecture mandates that converting a NaN value tointeger gives zero (if Invalid Operation FP exceptions arenot being trapped). This isn't the behaviour of the SoftFloatlibrary, so NaNs must be special-cased....
ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversionis a NaN then the output is always forced to be a quiet NaN by settingthe most significant bit of the fraction part.
ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point
VCVT of 16 bit fixed point to float should ignore the top 16 bitsof the source register. Cast to int16_t and friends rather thanint16 -- the former is guaranteed exactly 16 bits wide where the...
ARM: Implement VCVT to 16 bit integer using new softfloat routines
Use the softfloat conversion routines for conversion to 16 bitintegers, because just casting to a 16 bit type truncates thevalue rather than saturating it at 16-bit MAXINT/MININT.
ARM: enable XScale/iWMMXT in linux-user mode
In linux-user mode, the XScale/iWMMXT coprocessors must be enabledat reset so that we can run code that uses these instructions.
ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to Ccode as well as generated code, so we can use them to read andwrite the FPSCR when saving and restoring VFP registers acrosssignal handlers in linux-user mode....
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-arm : fix parallel saturated subtraction implementation
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
arm: fix arm kernel boot for non zero start addr
Booting an arm kernel has been broken a while when booting from non zero startaddress. This is due to the order of events: board init loads the kernel andsets register 15 to the start address and then qemu_system_reset reset the cpu...
Fix arm-linux-user
Only include hw/loader.h from target-arm/helper.c when building forsystem emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
ARMv7-M reset fixes
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a boardreset routine to call this. Also load values directly from ROM asimages have not been copied yet.
Avoid clearing the NVIC pointer on cpu reset.
target-arm: disable PAGE_EXEC for XN pages
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protectionchecking if the page is already in the TLB.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
target-arm: support thumb exception handlers
When handling an exception, switch to the correct mode based on theThumb Exception (TE) bit in the SCTLR.
Signed-off-by: Rabin Vincent <rabin@rab.in>
target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of witha slow helper. If the the cp15 read/write was not TLS register access,fall back to the cp15 helper.
This makes accessing __thread variables in linux-user when apps are compiled...
ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.
ARM FP16 support
Implement the ARM VFP half precision floating point extensions.
ARM Cortex-A9 cpu support
Basic Cortex-A9 support.
target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are definedas subarchitecture specific and real functionality for any of theother bits has not been implemented in QEMU. However, current codeallows modifying all bits in the VFP FPEXC register leading to...
target-arm: use clz32() instead of a for loop
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
target-arm: fix sdiv helper
(INT32_MIN / -1) triggers an overflow, and the result depends on thehost architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use atest to output the correct value.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
Fix correct reset value for ARM CP15 c1 auxiliary control register
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary controlregister is 2, not zero (page 3.12).
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
clean build: Fix arm build warnings
Fix remaining arm warnings - except for the mess in the NetWinder FPemulator.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Implement flush-to-zero mode (denormal results are replaced with zero).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
Implement default-NaN mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARMv7 cp15 cache ID registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
Implement (very) basic Thumb2-EE support. This doesn't actually implementEE state, just the associated system coprocessor registers. It is sufficientto keep OS setup and context switching code happy.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
Fix VFP fixed point conversion routines.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ARMv7 MMU access permissions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARMv6 translation table base address calculation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
Optimize redundant cp15 coprocessor access control register writes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
Add GDB XML register description support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv6: fix SIMD add/sub carry flags (Vincent Palatin).
After a quick code review, it seems to be a bad cut-n-paste between16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits bypair instead of one at a time.Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT...
Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).
helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1
op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat
translate.c...
ARMv7-M interrupt stack alignment fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
Fix incorrect argument types.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4291 c046a42c-6fe2-441c-8c8c-71466251a162
Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
Correct more ARM VFP 32/64 and signed/unsigned typos.
Fixes unreadable fonts in Maemo guest.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
Add basic OMAP2 chip support.
Add the OMAP242x (arm1136 core) initialisation with basic on-chipperipherals and update OMAP1 peripherals which are re-used in OMAP2.Make palmte.c and sd.c errors go to stderr.Allow disabling SD chipselect.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
Store the right TCG temp (typo).
Stops ARMv6 target from segfaulting early.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
Fix few spelling issues in comments
(Stefan Weil)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4187 c046a42c-6fe2-441c-8c8c-71466251a162
ARM N=Z=1 flag fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 14/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162