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cris: Handle opcode zero
It's a valid branch pc + 2.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Fix typo in comment (truely -> truly)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
cris: Allow more TB chaining for crisv10
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
cris: avoid a write only variable
Compiling with GCC 4.6.0 20100925 produced a warning:In file included from /src/qemu/target-cris/translate.c:3154:0:/src/qemu/target-cris/translate_v10.c: In function 'dec10_prep_move_m':/src/qemu/target-cris/translate_v10.c:111:22: error: variable 'rd' set but not used [-Werror=unused-but-set-variable]...
Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop executionso it must not be used for abnormal termination.
Use cpu_abort() when in CPU context, abort() otherwise.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Update to a hopefully more future proof FSF address
See also 8167ee883931cb20c6264fc19d040ce2dc6ceaaa,530e7615ce3c01882e582c84dc6304ab98a3d5c5 andfad6cb1a565bb73f83fc0e2654489457b489e436.
cris: Mask interrupts on dslots for CRISv10.
CRISv10 cores (unlike v32) do not take any interrupts while delayedjumps are pending (delay slots).
crisv10: Prettify.
cris: Add support for CRISv10 translation.