target-arm: Fix Neon VQDMULH.S16 instructions
Correct an error in the implementation of the 16 bitforms of VQDMULH, bringing them into line with the32 bit implementation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range iszero. It merely removes the guard against (sh == 0), and makes:_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag_usat(0x87654321, 0) return 0 and set the saturation flag...
target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from inthe various "multiply vector by scalar" ops (VMUL by scalarand friends).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Log instruction start in TCG code
Add support for logging the start of instructions in TCGcode debug dumps for ARM targets.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-arm: Translate with VFP-enabled from TB flags, not CPUState
When translating code, whether the VFP unit is enabled for this TBis stored in a bit in the TB flags. Use this rather than incorrectlyreading the FPEXC from the CPUState passed to translation....
target-arm: Translate with VFP len/stride from TB flags, not CPUState
When translating, the VFP vector length and stride for this TB are encodedin the TB flags; the CPUState copies may be different and must not be used.
target-arm: Translate with Thumb state from TB flags, not CPUState
The Thumb/ARM state for the TB being translated should come fromthe TB flags, not the CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags;the CPUState condexec bits may be different.
This patch fixes https://bugs.launchpad.net/bugs/604872 where we mightsegfault if we took an exception in the middle of a TB with an IT...
target-arm: Set privileged bit in TB flags correctly for M profile
M profile ARM cores don't have a CPSR mode field. Set the bit in theTB flags that indicates non-user mode correctly for these cores.
target-arm: Translate with user-state from TB flags, not CPUState
When translating, get the user/priv state from the TB flags, notthe CPUState.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumbmode SWI. (SWI and WFI generate "exceptions" which happen after theexecution of the instruction, ie when PC and IT bits have updated....
target-arm: Refactor translation of exception generating instructions
Create a new function which does the common sequence of gen_set_condexec,gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.
target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming executionafter taking an unexpected exception in the middle of an IT block.Fix this by tracking them along with PC changes and restoring in...
target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates(3 - op1 * op2) / 2) was missing the division operation. It alsodid not handle the special cases of (0,inf) and (inf,0).
target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status valuewhich should be used for operations which the ARM ARM indicates use"ARM standard floating-point arithmetic" rather than being controlled...
target-arm: Use the standard FPSCR value for VRSQRTS
VSQRTS always uses the standard FPSCR value as it is a Neon instruction.
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registersto stack of current mode" case in the helper function rather thaninline. This means the generated code does not make assumptions...
target-arm: Add symbolic constants for bitfields in TB flags
Add symbolic constants for the bitfields we use in the TB flags.
ARM: add neon helpers for VQSHLU
Add neon helper functions to implement VQSHLU, which is asigned-to-unsigned version of VQSHL available only as animmediate form.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
ARM: Fix decoding of VQSHL/VQSHLU immediate forms
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,including using the new VQSHLU helper functions where appropriate.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Set softfloat cumulative exc flags from correct FPSCR bits
When handling a write to the ARM FPSCR, set the softfloat cumulativeexception flags from the cumulative flags in the FPSCR, not theexception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host...
target-arm: wire up the softfloat flush_input_to_zero flag
Wire up the new softfloat support for flushing input denormalsto zero on ARM. The FPSCR FZ bit enables flush-to-zero forboth inputs and outputs, but the reporting of when inputs areflushed to zero is via a separate IDC bit rather than the UFC...
target-arm: fix SMMLA/SMMLS instructions
SMMLA and SMMLS are broken on both in normal and thumb mode, that isboth (different) implementations are wrong. They try to avoid a 64-bitadd for the rounding, which is not trivial if you want to support bothSMMLA and SMMLS with the same code....
target-arm: fix UMAAL instruction
UMAAL should use unsigned multiply instead of signed.
This patch fixes this issue by handling UMAAL separately fromUMULL/UMLAL/SMULL/SMLAL as these instructions are differentenough. It also explicitly list instructions in case and catch...
target-arm: correct cp15 c1_sys reset value for cortex-a8
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translationtable descriptors assigned to manager domains.
target-arm: Correct result in saturating cases for VQSHL of s8/16/32
Where VQSHL of a signed 8/16/32 bit value saturated, the resultvalue was not being calculated correctly (it should be eitherthe minimum or maximum value for the size of the signed type)....
target-arm: remove pointless else clause in VQSHL of u64
Remove a pointless else clause in the neon_qshl_u64 helper.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix VQSHL of signed 64 bit values by shift counts >= 64
VQSHL of a signed 64 bit non-zero value by a shift count >= 64 shouldsaturate; return the correct value in this case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix VQSHL of signed 64 bit values
Add a missing '-' which meant that we were misinterpreting the shiftargument for VQSHL of 64 bit signed values and treating almost everyshift value as if it were an extremely large right shift.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: Fix arguments passed to VQSHL helpers
Correct the arguments passed when generating neon qshl_{u,s}64()helpers so that we use the correct registers.
target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performingan 8-bit sign extend, causing this part of the expression to alwas be 0.
Reported-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write thehigh word of the 64-bit value from addr+4.Also make ldrexd and strexd agree that for a 64 bit value theaddress in env->exclusive_addr is that of the low word.
This fixes the issues reported in...
ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
Correct the decoding of source and destination registersfor the VFP forms of the VCVT instructions which convertbetween floating point and integer or fixed-point.
ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...
ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
ARM: Return correct result for float-to-integer conversion of NaN
The ARM architecture mandates that converting a NaN value tointeger gives zero (if Invalid Operation FP exceptions arenot being trapped). This isn't the behaviour of the SoftFloatlibrary, so NaNs must be special-cased....
ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversionis a NaN then the output is always forced to be a quiet NaN by settingthe most significant bit of the fraction part.
ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point
VCVT of 16 bit fixed point to float should ignore the top 16 bitsof the source register. Cast to int16_t and friends rather thanint16 -- the former is guaranteed exactly 16 bits wide where the...
ARM: Implement VCVT to 16 bit integer using new softfloat routines
Use the softfloat conversion routines for conversion to 16 bitintegers, because just casting to a 16 bit type truncates thevalue rather than saturating it at 16-bit MAXINT/MININT.
target-arm: Add support for PKHxx in thumb2
The PKHxx instructions were not recognized by the thumb2 decoder. Thesolution provided in this changeset is identical to the arm-modeimplementation.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Fix mixup in decoding of saturating add and sub
The thumb2 decoder contained a mixup between the bit controllingdoubling and the bit controlling if the operation was an add or a sub.
target-arm: Handle 'smc' as an undefined instruction
Refine check on bkpt so that smc and undefined instruction encodings arehandled as an undefined instruction and trap.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
ARM: enable XScale/iWMMXT in linux-user mode
In linux-user mode, the XScale/iWMMXT coprocessors must be enabledat reset so that we can run code that uses these instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to Ccode as well as generated code, so we can use them to read andwrite the FPSCR when saving and restoring VFP registers acrosssignal handlers in linux-user mode....
[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
target-arm: fix addsub/subadd implementation
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm : fix thumb2 parallel add/sub opcode decoding
target-arm : fix parallel saturated subtraction implementation
NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcitshift/or rather than using gen_bfi. This voids redundant maskoperations.
Signed-off-by: Paul Brook <paul@codesourcery.com>
arm: fix arm kernel boot for non zero start addr
Booting an arm kernel has been broken a while when booting from non zero startaddress. This is due to the order of events: board init loads the kernel andsets register 15 to the start address and then qemu_system_reset reset the cpu...
arm: prevent coprocessor IO reset
This prevent coprocessor IO structure from being reset on cpu reset. This wasa problem for PXA which uses coprocessor 6 and 14.
Signed-off-by: Lars Munch <lars@segv.dk>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.
Fix arm-linux-user
Only include hw/loader.h from target-arm/helper.c when building forsystem emulation.
ARMv7-M reset fixes
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a boardreset routine to call this. Also load values directly from ROM asimages have not been copied yet.
Avoid clearing the NVIC pointer on cpu reset.
target-arm: disable PAGE_EXEC for XN pages
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protectionchecking if the page is already in the TLB.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when thecondition code is AL as this will trigger an internal error.
Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust thecondition check accordingly.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always beingtreated an an invalid op.
target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a64bit destination vector but forgot to perform the actual shiftingoperation.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Riku Voipio <riku.voipio@nokia.com>...
target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncatingwas done when rounding was meant and vice verse.
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.
target-arm: support thumb exception handlers
When handling an exception, switch to the correct mode based on theThumb Exception (TE) bit in the SCTLR.
Signed-off-by: Rabin Vincent <rabin@rab.in>
target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.
Signed-off-by: Rabin Vincent <rabin@rab.in>Signed-off-by: Paul Brook <paul@codesourcery.com>
target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bitsthan the instruction wants to, and CPSIE does nothing. Fix it bypassing the correct mask (the "affect" bits) and value.
target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of witha slow helper. If the the cp15 read/write was not TLS register access,fall back to the cp15 helper.
This makes accessing __thread variables in linux-user when apps are compiled...
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.
ARM FP16 support
Implement the ARM VFP half precision floating point extensions.
ARM Cortex-A9 cpu support
Basic Cortex-A9 support.
target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.This patch changes the code so that it stores the intermediateresult in the target neon register directly and eliminates the needto use a temporary to hold the intermediate value thus leaving the...
target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch isrevised to follow more closely the specification and raisesundefined exception if 64bit element size is used for vld2/vst2 or...
target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are definedas subarchitecture specific and real functionality for any of theother bits has not been implemented in QEMU. However, current codeallows modifying all bits in the VFP FPEXC register leading to...
target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporaryvariable in the processing of NEON vsri, vshl and vsli instructions.This patch has been revised to also include a fix for the specialcase where the code would previously try to shift an integer value...
target-arm: fix neon shift helper functions
Current code is broken at least on recent compilers, comparisonbetween signed and unsigned types yield incorrect code and renderthe neon shift helper functions defunct. This is the third revisionof this patch, casting all comparisons with the sizeof operator to...
target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32but incorrectly released using dead_tmp which will cause resourceleak tracking to report false leaks.
target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a32x32->64 multiply which then uses only 32 least significant bits ofthe result. Replace that with a simple 32x32->32 multiply.
target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks intarget-arm/translate.c. This version also includes the leak patch forgen_set_cpsr macro, now converted as a static inline function, which Isent earlier as a separate patch on top of this patch....
target-arm: use clz32() instead of a for loop
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
target-arm: fix sdiv helper
(INT32_MIN / -1) triggers an overflow, and the result depends on thehost architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use atest to output the correct value.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed
Use load_reg_var() instead of accessing cpu_R[rn] directly to generatecorrect code when rn = 15.
target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7
target-arm: remove T0 and T1
target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: convert disas_neon_ls_insn not to use cpu_T
target-arm: convert disas_dsp_insn not use cpu_T
target-arm: convert disas_iwmmxt_insn not to use cpu_T
target-arm: convert VFP not to use cpu_T