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target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-arm: Use cpu_reset() in cpu_arm_init()
Commit 3c30dd5a68e9fee6af67cfd0d14ed7520820f36a (target-arm: Move resethandling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacingcpu_state_reset() with cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need toobtain an ARMCPU through arm_env_get_cpu() in machine init code.This requires to adjust the inclusion site of cpu-qom.h and in turn,...
target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move thereset code over to the class reset function and have cpu_state_resetsimply do a reset on the CPU QOM object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop cpu_reset_model_id()
cpu_reset_model_id() is now empty and we can remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Andreas Färber <afaerber@suse.de>
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() bycreating a field for the reset value in ARMCPU and setting itup in the cpu specific init functions.
target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;since these registers are only accessible on CPUs with theOMAPCP feature set there's no need to guard this reset witheither a CPUID or feature bit check....
target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.
target-arm: Move iWMMXT wCID reset to cpu_state_reset
Move the iWMMXT wCID reset to cpu_state_reset(). Sincewe use the same value for all CPUs with this feature(with the major/minor revision fields set to the QEMUspecific 'Q' value) there's no need to create an ARMCPU...
target-arm: Drop JTAG_ID documentation
None of the machines in QEMU offer a JTAG debug interface, so this infowas unused. Further, the PXA250 ID contradicts the February 2002Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised inthe per-cpu init functions. It can then be reset by asimple copy, and we can drop the code from cpu_reset_model_id().
target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU fieldset up by per-cpu init fns.
target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,so they are set up by the implementation-specific instanceinit functions rather than in cpu_reset_model_id().
target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in theper-implementation instance init function. At reset we thenjust copy the reset value into the CPUARMState field.
target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()to each CPU's instance init function. This requires us to movethe features field in CPUARMState so that it is not clearedon reset.
target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the...
Userspace ARM BE8 support
Add support for ARM BE8 userspace binaries.i.e. big-endian data and little-endian code.In principle LE8 mode is also possible, but AFAIK has never actuallybeen implemented/used.
System emulation doesn't have any useable big-endian board models,...
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registerswith a test for a new feature flag ARM_FEATURE_MVFR, and sets this featurefor all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu...
target-arm: Minimalistic CPU QOM'ification
Introduce only one non-abstract type TYPE_ARM_CPU and do not touchcp15 registers to not interfere with Peter's ongoing remodelling.Embed CPUARMState as first (additional) field of ARMCPU.
Let CPUClass::reset() call cpu_state_reset() for now....
target-arm: Drop cpu_arm_close()
It's unused, so no need to QOM'ify it later.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clearthe IT bits. Since the IT bits are cached in env->condexec_bitswe must clear them there: writing the bits in env->uncached_cpsrhas no effect. (Reported as LP:944645.)...
target-arm: Fix typo in ARM946 cp15 c5 handling
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling(instruction access permission bits) that meant it wouldreturn the data access permission bits by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...
target-arm: Clean includes
Remove some include statements which are not needed.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-arm/helper.c: tb_flush() on CPU reset
Since target-arm has some CPUState fields for which we take the approachof baking assumptions about them into translated code and then callingtb_flush() when the fields change, we must also tb_flush on CPU reset,...
target-arm/helper.c: Correct FPSID value for Cortex-A9
The correct FPSID for the Cortex-A9 (according to the TRM) is0x41033090 for the r0p0 that we claim to model.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add Cortex-A15 CPU definition
Add a definition of a Cortex-A15 CPU. Note that for the moment we donot implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc)...
Add dummy implementation of generic timer cp15 registers
Add a dummy implementation of the cp15 registers for the generictimer (found in the Cortex-A15), just sufficient for Linux todecide that it can't use it. This requires at least CNTP_CTL andCNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14....
target-arm: Fix implementation of TLB invalidate operations
Fix some bugs in the implementation of the TLB invalidateoperations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since...
target-arm/helper.c: Don't assume softfloat int32 is 32 bits only
In the helper routines for VCVT float-to-int conversions, addan explicit cast rather than relying on the softfloat int32type being exactly 32 bits wide (which it is not guaranteed to be)....
arm: store the config_base_register during cpu_reset
Long term, the config_base_register will be a QDM parameter. In themeantime, models that use it need to be able to preserve it acrosscpu_reset() calls.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>...
arm: Add dummy support for co-processor 15's secure config register
Signed-off-by: Rob Herring <rob.herring@calxeda.com>Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Don't use cpu_single_env in bank_number()
Avoid using cpu_single_env in bank_number() -- if we werecalled via the gdb stub reading or writing the CPSR thenit is NULL and we will segfault if we take the cpu_abort().
target-arm: Ignore attempts to set invalid modes in CPSR
Ignore attempts to set the CPSR mode field to an invalid value.This is UNPREDICTABLE, but we should not cpu_abort() for thingsa malicious guest (or a confused user on the gdbstub interface)can provoke....
arm: add dummy A9-specific cp15 registers
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currentlydefault to 0, but may have improved support after the QOMCPU patches are finished.
target-arm: Infer VFPv3 feature from VFPv4
VFP4 => VFP3
Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv5 feature from ARMv6
V6 => V5
target-arm: Infer ARMv6 feature from v6K
V6K => V6
target-arm: Infer ARMv6(K) feature from ARMv7
V7 && M => V6V7 && !M => V6K
target-arm: Infer AUXCR feature from ARMv6
V6 && !M => AUXCR
target-arm: Infer Thumb2 feature from ARMv7
V7 => THUMB2
target-arm: Infer Thumb division feature from M profile
M => THUMB_DIV
target-arm: Infer VFP feature from VFPv3
VFP3 => VFP
arm: Fix CP15 FSR (C5) domain setting
Return the correct value in the domain field in the cp15 DFSR(C5) -- bug noticed during Xvisor development.
Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>[Peter Maydell: reworded commit message]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Infer ARMv4T feature from ARMv5
V5 => V4T
target-arm/helper.c: Don't allocate TCG resources unless TCG enabled
Don't call arm_translate_init() (which allocates TCG resources)unless TCG is enabled.
target-arm: Fix use of free() in cpu_arm_close()
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
rsqrte_f32: No need to copy sign bit.
Indeed, the result is known to be always positive.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Fix typo
The command line option is called -kernel, not -kenrel.
Cc: Paul Brook <paul@codesourcery.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Andreas Färber <andreas.faerber@web.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Merge remote-tracking branch 'pm-arm/for-upstream' into pm
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
target-arm: support for ARM1176JZF-s cores
Add support for v6K ARM1176JZF-S. This core includes the VA<->PAtranslation capability and security extensions.
Signed-off-by: Jamie Iles <jamie@jamieiles.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Mark 1136r1 as a v6K core
The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,thus enabling the TLS registers, NOP hints, CLREX, half and byte wideexclusive load/stores, etc.
The VA-to-PA translation registers are not present on 1136r1, so...
target-arm: make VMSAv7 remapping and AP dependent on V6K
The VMSAv7 remapping and access permissions were introduced in ARMv6Kand not ARMv7.
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access
Correct the decode of the register numbers for BASEPRI, BASEPRI_MAXand FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR".
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>...
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010
Signed-off-by: Alex Zuepke <azuepke@sysgo.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Signal Underflow when denormal flushed to zero on output
On ARM the architecture mandates that when an output denormal is flushed tozero we must set the FPSCR UFC (underflow) bit, so map softfloat'sfloat_flag_output_denormal accordingly.
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTS
The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormalsas special cases, so we must set the InputDenormal exception flag ourselves.
target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fns
The functions which do the core estimation algorithms for the VRSQRTEand VRECPE instructions should not set floating point exception flags,so use a local fp status for doing these calculations....
target-arm: Set Invalid flag for NaN in float-to-int conversions
When we catch the special case of an input NaN in ARM float to inthelper functions, set the Invalid flag as well as returning thecorrect result.
Implement basic part of SA-1110/SA-1100
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x
Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the...
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix some typos in comments and documentation
helpfull -> helpfulusefull -> usefulcotrol -> control
and a grammar fix.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Detect tininess before rounding for FP operations
The ARM architecture mandates that we detect tininess before rounding,so set the softfloat fp_status up appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
target-arm/helper.c: For float-int conversion helpers pass ints as ints
Correct the argument and return types for the float<->int conversion helperfunctions so that integer arguments and return values are declared asuint32_t/uint64_t, not float32/float64. This allows us to remove the...
target-arm: use make_float32() to make constant floats for VRSQRTS
The preferred way to create a constant floating point value is to usemake_float32() rather than doing a runtime int32_to_float32().Convert the code in the VRSQRTS helper to work this way....
target-arm: Fix VRECPS edge cases handling
Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0
target-arm: Fix GE bits for v6media signed modulo arithmetic
Fix the signed modulo arithmetic helpers for the v6mediainstructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to setthe GE bits correctly (based on the result of the add or subtractbefore it is truncated to 16 bits, not after)....
target-arm: Implement cp15 VA->PA translation
Implement VA->PA translations by cp15-c7 that went through unchangedpreviously.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Introduce float64_256 and float64_512 constants.
These two constants will be used by helper functions such as recpe_f32and rsqrte_f32.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix support for VRECPE.
Now use the same algorithm as described in the ARM ARM.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix support for VRSQRTE.
target-arm: Silence NaNs resulting from half-precision conversions
Silence the NaNs that may result from half-precision conversion,as we do for the other conversions.
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
softfloat: Add float16 type and float16 NaN handling functions
Add a float16 type to softfloat, rather than using bits16 directly.Also add the missing functions float16_is_quiet_nan(),float16_is_signaling_nan() and float16_maybe_silence_nan(),which are needed for the float16 conversion routines....
target-arm: Clean up handling of MPIDR
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architectureas the MPIDR. Clean up its implementation to remove A9 specific handling.
This commit includes fixing an error in the value returned for theMPIDR on A9, where we were erroneously claiming a cluster ID of 9....
target-arm: Add CPU feature flag for v7MP
Add a CPU feature flag for v7MP (the multiprocessing extensions); someinstructions exist only for v7MP and not for the base v7 architecture.
target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates(3 - op1 * op2) / 2) was missing the division operation. It alsodid not handle the special cases of (0,inf) and (inf,0).
target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status valuewhich should be used for operations which the ARM ARM indicates use"ARM standard floating-point arithmetic" rather than being controlled...
target-arm: Use the standard FPSCR value for VRSQRTS
VSQRTS always uses the standard FPSCR value as it is a Neon instruction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registersto stack of current mode" case in the helper function rather thaninline. This means the generated code does not make assumptions...
target-arm: Set softfloat cumulative exc flags from correct FPSCR bits
When handling a write to the ARM FPSCR, set the softfloat cumulativeexception flags from the cumulative flags in the FPSCR, not theexception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host...
target-arm: wire up the softfloat flush_input_to_zero flag
Wire up the new softfloat support for flushing input denormalsto zero on ARM. The FPSCR FZ bit enables flush-to-zero forboth inputs and outputs, but the reporting of when inputs areflushed to zero is via a separate IDC bit rather than the UFC...
target-arm: correct cp15 c1_sys reset value for cortex-a8
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translationtable descriptors assigned to manager domains.
ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point
VCVT of 16 bit fixed point to float should ignore the top 16 bitsof the source register. Cast to int16_t and friends rather thanint16 -- the former is guaranteed exactly 16 bits wide where the...
ARM: Implement VCVT to 16 bit integer using new softfloat routines
Use the softfloat conversion routines for conversion to 16 bitintegers, because just casting to a 16 bit type truncates thevalue rather than saturating it at 16-bit MAXINT/MININT.