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target-cris: Move TCG initialization to CRISCPU initfn
Split out TCG initialization from cpu_cris_init(). Avoid CPUCRISStatedependency for v10-specific initialization and for non-v10 by inliningthe decision into the initfn as well.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-cris: Avoid AREG0 for helpers
Add an explicit CPUCRISState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-cris: Switch to AREG0 free mode
Add an explicit CPUCRISState parameter instead of relying on AREG0, anduse cpu_ld* in translation and interrupt handling. Remove AREG0 swappingin tlb_fill(). Switch to AREG0 free mode
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>...
cris: Add break support for v10.
Still no retb
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
target-cris: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUCRISState/g" target-cris/*.[hc] sed -i "s/#define CPUCRISState/#define CPUState/" target-cris/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
cris: Handle conditional stores on CRISv10
Signed-off-by: Stefan Sandstrom <Stefan.Sandstrom@axis.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
cris: Handle opcode zero
It's a valid branch pc + 2.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Fix typo in comment (truely -> truly)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
cris: Allow more TB chaining for crisv10
cris: avoid a write only variable
Compiling with GCC 4.6.0 20100925 produced a warning:In file included from /src/qemu/target-cris/translate.c:3154:0:/src/qemu/target-cris/translate_v10.c: In function 'dec10_prep_move_m':/src/qemu/target-cris/translate_v10.c:111:22: error: variable 'rd' set but not used [-Werror=unused-but-set-variable]...
Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop executionso it must not be used for abnormal termination.
Use cpu_abort() when in CPU context, abort() otherwise.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Update to a hopefully more future proof FSF address
See also 8167ee883931cb20c6264fc19d040ce2dc6ceaaa,530e7615ce3c01882e582c84dc6304ab98a3d5c5 andfad6cb1a565bb73f83fc0e2654489457b489e436.
cris: Mask interrupts on dslots for CRISv10.
CRISv10 cores (unlike v32) do not take any interrupts while delayedjumps are pending (delay slots).
crisv10: Prettify.
cris: Add support for CRISv10 translation.