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tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-arm: Export cpu_env
The cpu_env tcg variable will be used by both the AArch32 and AArch64handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: John Rigby <john.rigby@linaro.org>...
target-arm: Fix target_ulong/uint32_t confusions
Correct a few places that were using uint32_t or a 32 bitonly format string to handle something that should be a target_ulong.
target-arm: Pass DisasContext* to gen_set_pc_im()
We want gen_set_pc_im() to work for both AArch64 and AArch32, butto do this we'll need the DisasContext* so we can tell which modewe're in, so pass it in as a parameter.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Prepare translation for AArch64 code
This patch adds all the prerequisites for AArch64 support that didn'tfit into split up patches. It extends important bits in the core cpuheaders to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag...
target-arm: Add AArch64 translation stub
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,registers look vastly different, instruction encoding is completely different,basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the...
target-arm: Abstract out load/store from a vaddr in AArch32
AArch32 code (ie traditional 32 bit world) expects to beable to pass a vaddr in a TCGv_i32. However when QEMU iscompiled with TARGET_LONG_BITS=32 the TCG load/storefunctions take a TCGv_i64. Abstract out load/store with...
target-arm: Extract the disas struct to a header file
We will need to share the disassembly status struct between AArch32 andAArch64 modes. So put it into a header file that both sides can use.
target-arm: Use sextract32() in branch decode
In the decode of ARM B and BL insns, swap the order of the"append 2 implicit zeros to imm24" and the sign extend, anduse the new sextract32() utility function to do the latter.This avoids a direct dependency on the undefined C behaviour...
Merge remote-tracking branch 'mjt/trivial-patches' into staging
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
target-arm: Report unimplemented opcodes (LOG_UNIMP)
These unimplemented opcodes are handled like illegal opcodes, butthey are used in existing code. We should at least report when theyare executed.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Support coprocessor registers which do I/O
Add an ARM_CP_IO flag which an ARMCPRegInfo definition can use toindicate that the register's implementation does I/O and thusits accesses need to be surrounded by gen_io_start()/gen_io_end()in order for icount to work. Most notably, cp registers which...
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm: implement LDA/STL instructions
This adds support for the ARMv8 load acquire/store release instructions.Since qemu does nothing special for memory barriers, these can beemulated like their non-acquire/release counterparts.
Signed-off-by: Mans Rullgard <mans@mansr.com>...
target-arm: explicitly decode SEVL instruction
The ARMv8 SEVL instruction is in the architectural hint space alreadyemulated as nop. This makes the decoding of SEVL explicit for clarity.
Signed-off-by: Mans Rullgard <mans@mansr.com>Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com...
target-arm: add feature flag for ARMv8
Signed-off-by: Mans Rullgard <mans@mansr.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Merge remote-tracking branch 'pmaydell/target-arm.next' into staging
Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.orgSigned-off-by: Anthony Liguori <aliguori@us.ibm.com>
Fix rfe instruction
The rfe instruction has been broken since patch5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo.
Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Remove unnecessary break statements
Fix these warnings from cppcheck:
hw/display/cirrus_vga.c:2603:hw/sd/sd.c:348:hw/timer/exynos4210_mct.c:1033:target-arm/translate.c:9886:target-s390x/mem_helper.c:518:target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary....
target-arm: Remove gen_{ld,st}* definitions
All the uses of the gen_{ld,st}* functions are gone now, so removethe functions themselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove uses of gen_{ld,st}* from Neon code
target-arm: Remove use of gen_{ld,st}* from ldrex/strex
target-arm: Remove gen_{ld,st}* from basic ARM insns
target-arm: Remove gen_{ld,st}* from Thumb insns
target-arm: Remove gen_{ld,st}* from thumb2 decoder
target-arm: Remove uses of gen_{ld,st}* from iWMMXt code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Remove gen_ld64() and gen_st64()
gen_ld64() and gen_st64() are used only in one place, so justexpand them out.
target-arm: Don't use TCGv when we mean TCGv_i32
TCGv changes size depending on the compile time value ofTARGET_LONG_BITS. This is useful for generating code for MIPS style"instructions are the same but the register width changes" CPUs, andalso for the generic bits of QEMU which operate on "width of a...
target-arm: Reinsert missing return statement in ARM mode SRS decode
Since patch 81465888c5306cd94abb9847e560796fd13d3c2f target-arm: factor out handling of SRS instructionthe ARM mode SRS instruction has not worked in QEMU.
The problem is a missing return directive that was removed in the...
target-arm: Factor out handling of SRS instruction
Factor out the handling of the SRS instruction rather thanduplicating it between the Thumb and ARM decoders. This inpassing fixes two bugs in the Thumb decoder's SRS handlingwhich didn't exist in the ARM decoder:...
target-arm: Don't decode RFE or SRS on M profile cores
M profile cores do not have the RFE or SRS instructions, socorrectly UNDEF these insn patterns on those cores.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
arm/translate.c: Fix adc_CC/sbc_CC implementation
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CCand sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path)...
target-arm: Fix sbc_CC carry
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Using the ~T1 makes the add and subtract code paths nearlyidentical, so have sbc_CC use adc_CC....
target-arm: Use mul[us]2 in gen_mul[us]_i64_i32
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Use mul[us]2 and add2 in umlal et al
target-arm: Use add2 in gen_add_CC
target-arm: Implement adc_cc inline
Use add2 if available, otherwise use 64-bit arithmetic.
target-arm: Implement sbc_cc inline
Use sub2 if available, otherwise use 64-bit arithmetic.
target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes
Fix a leak of a TCG temporary in code paths for VFP system registerwrites for cases which UNDEF or are write-ignored.
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
target-arm: Use TCG operation for Neon 64 bit negation
Use the TCG operation to do Neon 64 bit negations rather than callinga helper routine for it.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helperfunction.
target-arm/translate: Fix RRX operands
Instructions that both use the RRX second operand and update CS wereincorrect, as the Carry flag was updated too early. An example of such aninstruction would be:
ands r12,r13,RRX
Ands, because of the "s" flag will update the carry flag. But the RRX second...
target-arm: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. Itallows the host to emit the corresponding instruction if available.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Reinstate display of VFP registers in cpu_dump_state
Reinstate the display of VFP registers in cpu_dump_state(), ifthe CPU has them (this code had been #if 0'd out a for a long time).We drop the attempt ot display the values as floating point, since...
target-arm: use globals for CC flags
Use globals for CC flags instead of loading/storing them each they areaccessed. This allows some optimizations to be performed by the TCGoptimization passes.
target-arm: convert add_cc and sub_cc helpers to TCG
Now that the setcond TCG op is available, it's possible to replaceadd_cc and sub_cc helpers by TCG code. The code generated by TCG isactually very close to the one generated by GCC for the helper, and...
target-arm: convert sar, shl and shr helpers to TCG
Now that the movcond TCG op is available, it's possible to replaceshl and shr helpers by TCG code. The code generated by TCG is slightlylonger than the code generated by GCC for the helper but is still worth...
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert remaining helpers
Convert remaining helpers to AREG0 free mode: add an explicitCPUState parameter instead of relying on AREG0.
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
arm: translate: comment typo - s/middel/middle/
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Fix TCG temp handling in 64 bit cp writes
Fix errors in the TCG temp handling in the 64 bit coprocessorwrite path: we were reusing a 32 bit temp after it had beenfreed by store_reg(), and failing to free a 64 bit temp.
This bug has no visible effect at this point because there...
target-arm: Fix CP15 based WFI
The coprocessor register rework broke cp15 based WFI instructions.We incorrectly fall through the normal register write case, whichincorrectly adds a forced block termination. We've already donea special version of this (DISAS_WFI), so return immediately....
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,so it can be deleted.
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.This includes only providing them on the CPUs which implementedthem, rather than the previous blunderbuss approach of makingall MCRR instructions on all CPUs act as NOPs....
target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers tothe new scheme.
target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework
target-arm: Convert WFI/barriers special cases to cp_reginfo
Convert the various WFI and barrier instruction special cases to usecp_reginfo infrastructure.
target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR touse arm_cp_reginfo.
target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to thecp_reginfo scheme.
target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so wecan remove it and the infrastructure it used.
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
target-arm: Make SETEND respect bswap_code (BE8) setting
Make the SETEND instruction respect the setting of bswap_code,so that in BE8 mode we UNDEF for attempts to switch intolittle-endian mode and nop for attempts to stay in big-endianmode. (This is the inverse of the existing handling of SETEND...
Userspace ARM BE8 support
Add support for ARM BE8 userspace binaries.i.e. big-endian data and little-endian code.In principle LE8 mode is also possible, but AFAIK has never actuallybeen implemented/used.
System emulation doesn't have any useable big-endian board models,...
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registerswith a test for a new feature flag ARM_FEATURE_MVFR, and sets this featurefor all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu...
target-arm: Decode SETEND correctly in Thumb
Decode the SETEND instruction correctly in Thumb mode,rather than accidentally treating it like CPS. We don'tsupport BE8 mode, but this change brings the Thumb modein to line with behaviour in ARM mode: 'SETEND BE' is...
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...
target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17
This fixes an issue reported as LP:913925....
target-arm/translate.c: Fix slightly misleading comment in Thumb decoder
Clarify some slightly misleading comments in the Thumb decoder'shandling of the memory hint space -- in particular one code pathmarked as 'UNPREDICTABLE or unallocated hint' also includes some...
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
target-arm: v6 media multiply space: UNDEF on unassigned encodings
Clean up the decoding of the v6 media multiply space so that we UNDEFon unassigned encodings rather than randomly interpreting them assome instruction in this space.
target-arm: Support v6 barriers in linux-user mode
ARMv6 implemented various operations as special cases of cp15 accesseswhich are true instructions in v7; this includes barriers (DMB, DSB, ISB).Catch this special case at translate time, so that it works in linux-user...
target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. Inparticular, we now generate an undef exception for overlarge imm8values rather than generating 1000+ TCG ops and hitting an assertion....
target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.This avoids a TCG assert later when the VCVTT/VCVTB code tries touse a source register that wasn't ever set up.
We pull the check for the presence of the half-precision extension...
target-arm: Don't print debug messages for various UNDEF cases
Remove some stray printfs for cases which don't generally happen(some VFP UNDEF cases, reads and writes to unknown cp14 registers);we should simply generate an UNDEF when the instruction is executed....
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
Revert "target-arm: Use global env in neon_helper.c helpers"
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3so that we return to passing CPUState to helpers as an explicit parameter.(There were a number of conflicts in target-arm/translate.c which had...
target-arm: Pass fp status pointer explicitly to neon fp helpers
Make the Neon helpers for various floating point operations take anexplicit pointer to the float_status they use, so they don't rely onthe global environment pointer any more. This also allows us to drop...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: Add helper function to generate code to get fpstatus pointer
Add and use a helper function which returns a TCGv which is a pointerto the fp_status for either Neon or VFP operations.
Revert "target-arm: Use global env in iwmmxt_helper.c helpers"
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79,returning the iwmmxt helpers to passing env in as a parameter.