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# Date Author Comment
29b69198 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: More use of TAI and SAI helper macros

Finish conversion of all memory operations.

Signed-off-by: Richard Henderson <>
8327a470 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Use TCG_REG_Rn constants

Instead of bare N, for clarity. The only (intentional) exception made
is for insns that encode R|0, i.e. when R0 encoded into the insn is
interpreted as zero not the contents of the register.

Signed-off-by: Richard Henderson <>
5e0f40cf 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Use tcg_out64

Signed-off-by: Richard Henderson <>
541dd4ce 09/25/2013 05:46 pm Richard Henderson

tcg-ppc64: Reformat tcg-target.c

Whitespace and brace changes only.

Signed-off-by: Richard Henderson <>
a05b5b9b 09/02/2013 07:08 pm Richard Henderson

tcg: Change tcg_out_ld/st offset to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
e58eb534 09/02/2013 07:08 pm Richard Henderson

exec: Split softmmu_defs.h

The _cmmu helpers can be moved to exec-all.h. The helpers that are
used from TCG will shortly need access to tcg_target_long so move
their declarations into tcg.h.

This requires minor include adjustments to all TCG backends.
...
32f5717f 09/02/2013 07:08 pm Richard Henderson

tcg-ppc64: Implement muluh, mulsh

Using these instead of mulu2 and muls2 lets us avoid having to argument
overlap analysis in the backend. Normal register allocation will DTRT.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2ba7fae2 09/02/2013 07:08 pm Richard Henderson

tcg: Change relocation offsets to intptr_t

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5b9f72ab 07/09/2013 05:14 pm Richard Henderson

tcg-ppc64: Don't implement rem

Reviewed-by: Andreas Färber <>
Signed-off-by: Richard Henderson <>
82e0f917 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: bswap64 rotates output 32 bits

If our input and output is in the same register, bswap64 tries to
undo a rotate of the input. This just ends up rotating the output.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
84247357 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: Fix add2_i64

add2_i64 was adding the lower double word to the upper double word
of each input. Fix this so we add the lower double words, then the
upper double words with carry propagation.

Cc:
Signed-off-by: Anton Blanchard <>...
d1bdd3af 06/17/2013 08:42 pm Anton Blanchard

tcg-ppc64: rotr_i32 rotates wrong amount

rotr_i32 calculates the amount to left shift and puts it into a
temporary, but then doesn't use it when doing the shift.

Cc:
Signed-off-by: Anton Blanchard <>
Signed-off-by: Richard Henderson <>
8a94cfb0 06/17/2013 08:41 pm Anton Blanchard

tcg-ppc64: Fix RLDCL opcode

The rldcl instruction doesn't have an sh field, so the minor opcode
is shifted 1 bit. We were using the XO30 macro which shifted the
minor opcode 2 bits.

Remove XO30 and add MD30 and MDS30 macros which match the
Power ISA categories....
39dc85b9 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Handle deposit of zero

The TCG optimizer does great work when inserting constants, being able
to fold the open-coded deposit expansion to just an AND or an OR. Avoid
a bit the regression caused by having the deposit opcode by expanding
deposit of zero as an AND....
027ffea9 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement movcond

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
1e6e9aca 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use getauxval for ISA detection

Glibc 2.16 includes an easy way to get feature bits previously
buried in /proc or the program startup auxiliary vector. Use it.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6c858762 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement add2/sub2_i64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6645c147 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement mulu2/muls2_i64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
991041a4 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Cleanup i32 constants to tcg_out_cmp

Nothing else in the call chain ensures that these
constants don't have garbage in the high bits.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6995a4a0 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use MFOCRF instead of MFCR

It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.

Reviewed-by: Aurelien Jarno <>...
70fac59a 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use ISEL for setcond

There are a few simple special cases that should be handled first.
Break these out to subroutines to avoid code duplication.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
33de9ed2 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement deposit

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ef809300 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use I constraint for mul

The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us. The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.

Reviewed-by: Aurelien Jarno <>...
4c314da6 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Use TCGType throughout compares

The optimization/bug being fixed is that tcg_out_cmp was not applying the
right type to loading a constant, in the case it can't be implemented
directly. Rather than recomputing the TCGType enum from the arch64 bool,...
68aebd45 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement bswap64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ce1010d6 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement compound logicals

Mostly copied from the ppc32 port.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
37251b98 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Handle constant inputs for some compound logicals

Since we have special code to handle and/or/xor with a constant,
apply the same to andc/orc/eqv with a constant.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5d221582 04/15/2013 09:09 pm Richard Henderson

tcg-ppc64: Implement bswap16 and bswap32

Signed-off-by: Richard Henderson <>
313d91c7 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Implement rotates

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
49d9870a 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Streamline qemu_ld/st insn selection

Using a table to look up insns of the right width and sign.
Include support for the Power 2.06 LDBRX and STDBRX insns.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
28f2dba6 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Use automatic implementation of ext32u_i64

The enhancements to and immediate obviate this.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
a9249dff 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve and_i32 with constant

Use RLWINM

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
637af30c 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve and_i64 with constant

Use RLDICL and RLDICR.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
dce74c57 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Tidy or and xor patterns.

Handle constants in common code; we'll want to reuse that later.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
148bdd23 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Allow constant first argument to sub

Using SUBFIC for 16-bit signed constants.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
ee924fa6 04/15/2013 08:55 pm Richard Henderson

tcg-ppc64: Improve constant add and sub ops.

Improve constant addition -- previously we'd emit useless addi with 0.
Use new constraints to force the driver to pull full 64-bit constants
into a register.

Reviewed-by: Aurelien Jarno <>...
3d582c61 04/15/2013 08:52 pm Richard Henderson

tcg-ppc64: Rearrange integer constant constraints

We'll need a zero, and Z makes more sense for that. Make sure we
have a full compliment of signed and unsigned 16 and 32-bit tests.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
421233a1 04/15/2013 08:52 pm Richard Henderson

tcg-ppc64: Cleanup tcg_out_movi

The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing
a signed 32-bit quantity against an unsigned 32-bit quantity.

When possible, use addi+oris for 32-bit unsigned constants. Otherwise,
standardize on addi+oris+ori instead of addis+ori+rldicl....
752c1fdb 04/15/2013 08:51 pm Richard Henderson

tcg-ppc64: Fix setcond_i32

We weren't ignoring the high 32 bits during a NE comparison.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
2fd8eddc 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use TAI and SAI

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
5e916c28 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_shri64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
0a9564b9 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_shli64

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
6e5e0602 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_ext32u

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
9e555b73 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Introduce and use tcg_out_rlw

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
aceac8d6 04/15/2013 08:44 pm Richard Henderson

tcg-ppc64: Use TCGReg everywhere

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Richard Henderson <>
022c62cb 12/19/2012 09:31 am Paolo Bonzini

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <>
0aed257f 10/06/2012 07:48 pm Richard Henderson

tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS

There are several cases that can be handled easier inside both
translators and code generators if we have out-of-band values
for conditions. It's easy enough to handle ALWAYS and NEVER in
the natural way inside the tcg middle-end....
626cd050 10/06/2012 07:47 pm Aurelien Jarno

tcg: remove obsolete jmp op

The TCG jmp operation doesn't really make sense in the QEMU context, it
is unused, it is not implemented by some targets, and it is wrongly
implemented by some others.

This patch simply removes it.

Reviewed-by: Richard Henderson <>...
6e17d0c5 09/22/2012 05:52 pm Stefan Weil

tcg: Remove tcg_target_get_call_iarg_regs_count

The TCG targets no longer need individual implementations.

Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,
'flags' is no longer used in tcg_target_get_call_iarg_regs_count.

The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
89c33337 09/15/2012 08:51 pm Blue Swirl

Remove unused CONFIG_TCG_PASS_AREG0 and dead code

Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,
remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.

Remove dyngen-exec.h and all references to it. Although included by
hw/spapr_hcall.c, it does not seem to use it....
affe5189 06/24/2012 01:54 am Alexander Graf

TCG: Fix compile breakage in tcg_dump_ops

Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convert
all users (notably missing the ppc ones) to it. Fix them to the new syntax.

Signed-off-by: Alexander Graf <>
Signed-off-by: malc <>
c82e5848 05/14/2012 11:53 pm Andreas Färber

tcg/ppc64: Don't hardcode register numbers for qemu_ld/st

Facilitates using r3 for prepended AREG0.

Signed-off-by: Andreas F?rber <>
Signed-off-by: malc <>
f4f7d01a 05/14/2012 11:53 pm Andreas Färber

tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0

In qemu_ld/st load the registers for the helper calls directly rather
than rotating them around afterwards for AREG0.

Also clobber the additional register.

Signed-off-by: Andreas F?rber <>
Signed-off-by: malc <>
f6af014e 05/03/2012 02:47 pm malc

Restore consistent formatting

Signed-off-by: malc <>
f638f0d3 03/29/2012 10:10 am Li Zhang

qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs

There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes an
assertion failure in tcg_add_target_add_op_defs() when --enable-debug is
used on a ppc64 backend (that's ppc64 host, not target)....
e141ab52 03/18/2012 02:21 pm Blue Swirl

softmmu templates: optionally pass CPUState to memory access functions

Optionally, make memory access helpers take a parameter for CPUState
instead of relying on global env.

On most targets, perform simple moves to reorder registers. On i386,
switch from regparm(3) calling convention to standard stack-based...
9349b4f9 03/14/2012 11:20 pm Andreas Färber

Rename CPUState -> CPUArchState

Scripted conversion:
for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
sed -i "s/CPUState/CPUArchState/g" $file
done...
25cc4a76 11/19/2011 01:17 pm Blue Swirl

Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf

  • 's390-1.0' of git://repo.or.cz/qemu/agraf:
    s390x: initialize virtio dev region
    tcg: Use TCGReg for standard tcg-target entry points.
    tcg: Standardize on TCGReg as the enum for hard registers
    s390x: Add shutdown for TCG s390-virtio machine...
2a534aff 11/14/2011 06:47 pm Richard Henderson

tcg: Use TCGReg for standard tcg-target entry points.

Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.

Signed-off-by: Richard Henderson <>
Reviewed-by: Andreas Färber <>
Reviewed-by: Stefan Weil <>...
9df3b45d 11/11/2011 06:33 pm David Gibson

tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6

tcg/ppc64/tcg-target.c has a couple of places where variables are set
unconditionally, but otherwise used only for softmmu builds, not
userspace only builds. This causes compiler warnings (which are fatal...
be9c4183 09/17/2011 08:56 pm Stefan Weil

tcg/ppc64: Only one call output register needed for 64 bit hosts

The second register is only needed for 32 bit hosts.

Cc: Vassili Karpov <>
Fine-with-me'd-by: Vassili Karpov <>
Signed-off-by: Stefan Weil <>...
e89720b1 09/09/2011 06:07 pm Thomas Huth

tcg/ppc64: Fix zero extension code generation bug for ppc64 host

The ppc64 code generation backend uses an rldicr (Rotate Left Double
Immediate and Clear Right) instruction to implement zero extension of
a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However...
157f2662 08/22/2011 01:40 pm malc

tcg/ppc64: implement not_i32/64 and ext32u_i64

Signed-off-by: malc <>
136a0b5a 06/28/2011 01:49 am Blue Swirl

TCG/PPC: use stack for TCG temps

Use stack instead of temp_buf array in CPUState for TCG temps.

Signed-off-by: Blue Swirl <>
Signed-off-by: malc <>
c24a9c6e 06/28/2011 01:27 am malc

tcg/ppc64: Remove tcg_out_addi

The only user (within tcg.c) was removed

Signed-off-by: malc <>
614f104d 06/26/2011 09:25 pm Blue Swirl

Delegate setup of TCG temporaries to targets

Delegate TCG temp_buf setup to targets, so that they can use a stack
frame later instead.

Signed-off-by: Blue Swirl <>
cea5f9a2 06/26/2011 09:25 pm Blue Swirl

cpu-exec.c: avoid AREG0 use

Make functions take a parameter for CPUState instead of relying
on global env. Pass CPUState pointer to TCG prologue, which moves
it to AREG0.

Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue
change.

Revert the hacks to avoid AREG0 use on Sparc hosts....
b1d6d51d 08/14/2010 11:57 pm Andreas Färber

TCG: Revert ppc64 tcg_out_movi32 change

3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target
compilation in the code path without guest base.

Reverting this line fixes the build.

Signed-off-by: Andreas F?rber <>...
b9e946c7 06/29/2010 10:30 pm Richard Henderson

tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.

We need not reserve the register unless we're going to use it.

Signed-off-by: Richard Henderson <>
Signed-off-by: malc <>
e4d58b41 06/09/2010 12:18 pm Richard Henderson

tcg: Make some tcg-target.c routines static.

Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
3b6dac34 06/09/2010 12:18 pm Richard Henderson

tcg: Add TYPE parameter to tcg_out_mov.

Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.

Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"...
98926b0a 04/07/2010 01:26 am malc

tcg/ppc64: Fix typo

Signed-off-by: malc <>
355b1943 04/05/2010 02:28 am Paul Brook

Split TLB addend and target_phys_addr_t

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t). However since the introduction of...
86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...
8a56e840 03/26/2010 10:29 pm Richard Henderson

tcg: Use TCGCond where appropriate.

Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
35f6b599 03/12/2010 11:27 pm malc

tcg/ppc64: Only define addend load helpers in softmmu case

Signed-off-by: malc <>
1cd62ae9 02/07/2010 01:48 am malc

tcg/ppc64: implement setcond

Signed-off-by: malc <>
591d6f1d 12/15/2009 06:45 pm malc

tcg/ppc64: Fix loading of 32bit constants

Signed-off-by: malc <>
5d7ff5bb 12/06/2009 05:20 pm Andreas Faerber

TCG: Mac OS X support for ppc64 target

Darwin/ppc64 does not use function descriptors,
adapt prologue and tcg_out_call accordingly.
GPR2 is available for general use, so let's use it.

http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html...
016b2b28 11/24/2009 08:51 pm Aurelien Jarno

tcg/ppc64,x86_64: fix constraints of op_qemu_st64

This op only takes two arguments, not two.

Signed-off-by: Aurelien Jarno <>
f6548c0a 07/18/2009 12:16 pm malc

PPC 32/64 GUEST_BASE support

Signed-off-by: malc <>
4f4a67ae 07/18/2009 12:16 pm malc

Fix LHZX opcode value

Signed-off-by: malc <>
2ffebe2d 04/11/2009 11:19 am malc

Remove reserved registers from tcg_target_reg_alloc_order

Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7082 c046a42c-6fe2-441c-8c8c-71466251a162
9de187a0 04/11/2009 10:39 am malc

Whack [LS]MW

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
095271d4 02/11/2009 08:54 pm malc

Add missing r24..r26 to callee save registers

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6613 c046a42c-6fe2-441c-8c8c-71466251a162
b1503cda 12/22/2008 10:33 pm malc

Use the ARRAY_SIZE() macro where appropriate.

Change from v1:
Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
8421d9e5 11/12/2008 10:36 pm malc

Avoid compiler warning

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5710 c046a42c-6fe2-441c-8c8c-71466251a162
828808f5 11/11/2008 05:04 am malc

Fix alignment problem with some 64bit load/store instructions

LD/STD/LWA require displacement to be multiple of 4, provide
tcg_out_ldsta which checks the supplied displacement and falls
back on indexed variant when the check fails. All uses of
LD/STD/LWA outside of tcg_out_ldst appear to be safe....
d4a9eb1f 10/05/2008 12:59 pm blueswir1

Add some missing static and const qualifiers, reg_names only used if NDEBUG set

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
3ee1b855 10/02/2008 11:02 pm malc

Optimize 64 bit bswap

Use rldimi instead of rldicr/or pair, saves us one instruction.
Suggested by Hollis Blanchard.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5404 c046a42c-6fe2-441c-8c8c-71466251a162
79383c9c 08/30/2008 12:51 pm blueswir1

Fix some warnings that would be generated by gcc -Wredundant-decls

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
735ee40d 08/21/2008 01:39 am malc

Relax qemu_ld/st constraints for !SOFTMMU case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5034 c046a42c-6fe2-441c-8c8c-71466251a162
109719ec 08/21/2008 01:39 am malc

Avoid clobbering input/aliased registers in !SOFTMMU+64bit+bswap case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5033 c046a42c-6fe2-441c-8c8c-71466251a162
0b7c1d89 08/21/2008 01:39 am malc

Clear the upper 32 bits of addr_reg in TARGET_LONG_BITS == 32 case

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5032 c046a42c-6fe2-441c-8c8c-71466251a162
a2a546b3 08/21/2008 01:39 am malc

Move tcg_out_tlb_read into #ifdef CONFIG_SOFTMMU block to avoid compiler warning

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5031 c046a42c-6fe2-441c-8c8c-71466251a162
fe6f943f 07/29/2008 02:46 am malc

Immediate versions of some operations

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4962 c046a42c-6fe2-441c-8c8c-71466251a162
000a2d86 07/29/2008 02:46 am malc

Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
e924bbec 07/28/2008 10:42 pm malc

Set the L field of CMP[L][I] when dealing with 64 bit quantities

This (along with previous 2 commits) makes X86_64 work on ppc64 too.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4960 c046a42c-6fe2-441c-8c8c-71466251a162
880e52b8 07/28/2008 10:42 pm malc

Fix preprocessor guard condition

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4959 c046a42c-6fe2-441c-8c8c-71466251a162