Statistics
| Branch: | Revision:

root / hw / xilinx_zynq.c @ 5e22c276

History | View | Annotate | Download (6.6 kB)

# Date Author Comment
9c17d615 12/19/2012 09:32 am Paolo Bonzini

softmmu: move include files to include/sysemu/

Signed-off-by: Paolo Bonzini <>

022c62cb 12/19/2012 09:31 am Paolo Bonzini

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <>

1422e32d 12/19/2012 09:31 am Paolo Bonzini

net: reorganize headers

Move public headers to include/net, and leave private headers in net/.
Put the virtio headers in include/net/tap.h, removing the multiple copies
that existed. Leave include/net/tap.h as the interface for NICs, and
net/tap_int.h as the interface for OS-specific parts of the tap backend....

e376a788 12/13/2012 10:32 pm Anthony Liguori

Merge remote-tracking branch 'kwolf/for-anthony' into staging

  • kwolf/for-anthony: (43 commits)
    qcow2: Factor out handle_dependencies()
    qcow2: Execute run_dependent_requests() without lock
    qcow2: Enable dirty flag in qcow2_alloc_cluster_link_l2
    qcow2: Allocate l2meta only for cluster allocations...
79f5d67e 12/11/2012 01:30 pm walimis

xilinx_zynq: Add one variable to avoid overwriting QSPI bus

commit 7b482bcf xilinx_zynq: added QSPI controller

Adds one QSPI controller, which has two spi buses, one is for
spi0, and another is for spi1. But when initializing the spi1
bus, "dev" has been overwrited by the ssi_create_slave_no_init() function,...

2d0d2837 12/11/2012 12:05 pm Christian Borntraeger

Support default block interfaces per QEMUMachine

There are QEMUMachines that have neither IF_IDE nor IF_SCSI as a
default/standard interface to their block devices / drives. Therefore,
this patch introduces a new field default_block_type per QEMUMachine
struct. The prior use_scsi field becomes thereby obsolete and is...

892776ce 11/01/2012 04:17 pm Peter Crosthwaite

xilinx_zynq: add USB controllers

Add the two usb controllers in Zynq.

Signed-off-by: Peter Crosthwaite <>
Signed-off-by: Gerd Hoffmann <>

7b482bcf 10/29/2012 08:38 am Peter Crosthwaite

xilinx_zynq: added QSPI controller

Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow
modelling of the different geometries. E.G. Dual parallel and dual stacked
mode can both be tested with this one arrangement.

Signed-off-by: Peter Crosthwaite <>

5f072e1f 10/20/2012 10:53 am Eduardo Habkost

create struct for machine initialization arguments

This should help us to:
- More easily add or remove machine initialization arguments without
having to change every single machine init function;
- More easily make mechanical changes involving the machine init...

559d489f 10/10/2012 04:13 am Peter A. G. Crosthwaite

xilinx_zynq: Added SPI controllers + flashes

Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.

Signed-off-by: Peter A. G. Crosthwaite <>
Acked-by: Peter Maydell <>

17c2f0bf 06/11/2012 01:23 am Andreas Färber

xilinx_zynq: Use cpu_arm_init() to obtain ARMCPU

Needed for arm_load_kernel().

Signed-off-by: Andreas Färber <>
Acked-by: Peter A.G. Crosthwaite <>

3aaa8dfa 06/11/2012 01:23 am Andreas Färber

arm_boot: Pass ARMCPU to arm_load_kernel()

In particular this simplifies the &s->mpu->cpu->env expression again.

first_cpu and ->next_cpu are expected to be QOM'ified later.

Signed-off-by: Andreas Färber <>
Acked-by: Igor Mitsyanko <> (for exynos)...

4bd74661 06/11/2012 01:23 am Andreas Färber

arm_pic: Pass ARMCPU to arm_pic_init_cpu()

Pass it through to arm_pic_cpu_handler().

Signed-off-by: Andreas Färber <>
Acked-by: Peter Maydell <>
Acked-by: Igor Mitsyanko <> (for exynos)

5ae93306 03/14/2012 11:20 pm Andreas Färber

arm hw/: Don't use CPUState

Scripted conversion:
for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c hw/xilinx_zynq.c ; do...

e3260506 03/07/2012 03:20 am Peter A. G. Crosthwaite

xilinx_zynq: machine model initial version

Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific
system level control register (SLCR) module.

Signed-off-by: Peter A. G. Crosthwaite <>
Acked-by: Edgar E. Iglesias <>...