root / target-sparc / cpu.h @ 5f8ae8e2
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | 047b39e4 | Stefan Weil | #include "qemu-common.h" |
6 | 30038fd8 | Richard Henderson | #include "bswap.h" |
7 | af7bf89b | bellard | |
8 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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9 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
10 | 30038fd8 | Richard Henderson | #define TARGET_DPREGS 16 |
11 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
12 | 058ed88c | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
13 | 058ed88c | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
14 | 058ed88c | Richard Henderson | #else
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15 | 058ed88c | Richard Henderson | #define TARGET_LONG_BITS 64 |
16 | 30038fd8 | Richard Henderson | #define TARGET_DPREGS 32 |
17 | 058ed88c | Richard Henderson | #define TARGET_PAGE_BITS 13 /* 8k */ |
18 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 41 |
19 | 52705890 | Richard Henderson | # ifdef TARGET_ABI32
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20 | 52705890 | Richard Henderson | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
21 | 52705890 | Richard Henderson | # else
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22 | 52705890 | Richard Henderson | # define TARGET_VIRT_ADDR_SPACE_BITS 44 |
23 | 52705890 | Richard Henderson | # endif
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24 | af7bf89b | bellard | #endif
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25 | 3cf1e035 | bellard | |
26 | 9349b4f9 | Andreas Färber | #define CPUArchState struct CPUSPARCState |
27 | c2764719 | pbrook | |
28 | 7a3f1944 | bellard | #include "cpu-defs.h" |
29 | 7a3f1944 | bellard | |
30 | 7a0e1f41 | bellard | #include "softfloat.h" |
31 | 7a0e1f41 | bellard | |
32 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
33 | 1fddef4b | bellard | |
34 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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35 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARC
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36 | 9042c0e2 | ths | #else
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37 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARCV9
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38 | 9042c0e2 | ths | #endif
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39 | 9042c0e2 | ths | |
40 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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41 | 7a3f1944 | bellard | |
42 | cf495bcf | bellard | /* trap definitions */
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43 | 3475187d | bellard | #ifndef TARGET_SPARC64
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44 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
45 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
46 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
47 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
48 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
49 | 5fafdf24 | ths | #define TT_WIN_UNF 0x06 |
50 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x07 |
51 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
52 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
53 | e32f879d | blueswir1 | #define TT_TOVF 0x0a |
54 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
55 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x21 |
56 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH 0x25 |
57 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x29 |
58 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
59 | fcc72045 | blueswir1 | #define TT_NCP_INSN 0x24 |
60 | cf495bcf | bellard | #define TT_TRAP 0x80 |
61 | 3475187d | bellard | #else
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62 | 8194f35a | Igor Kovalenko | #define TT_POWER_ON_RESET 0x01 |
63 | 3475187d | bellard | #define TT_TFAULT 0x08 |
64 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x0a |
65 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
66 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH TT_ILL_INSN
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67 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
68 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
69 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
70 | e32f879d | blueswir1 | #define TT_TOVF 0x23 |
71 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
72 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
73 | 3475187d | bellard | #define TT_DFAULT 0x30 |
74 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x32 |
75 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x34 |
76 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
77 | 3475187d | bellard | #define TT_EXTINT 0x40 |
78 | 74b9decc | blueswir1 | #define TT_IVEC 0x60 |
79 | e19e4efe | blueswir1 | #define TT_TMISS 0x64 |
80 | e19e4efe | blueswir1 | #define TT_DMISS 0x68 |
81 | 74b9decc | blueswir1 | #define TT_DPROT 0x6c |
82 | 3475187d | bellard | #define TT_SPILL 0x80 |
83 | 3475187d | bellard | #define TT_FILL 0xc0 |
84 | 88c8e03f | Igor V. Kovalenko | #define TT_WOTHER (1 << 5) |
85 | 3475187d | bellard | #define TT_TRAP 0x100 |
86 | 3475187d | bellard | #endif
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87 | 7a3f1944 | bellard | |
88 | 4b8b8b76 | blueswir1 | #define PSR_NEG_SHIFT 23 |
89 | 4b8b8b76 | blueswir1 | #define PSR_NEG (1 << PSR_NEG_SHIFT) |
90 | 4b8b8b76 | blueswir1 | #define PSR_ZERO_SHIFT 22 |
91 | 4b8b8b76 | blueswir1 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) |
92 | 4b8b8b76 | blueswir1 | #define PSR_OVF_SHIFT 21 |
93 | 4b8b8b76 | blueswir1 | #define PSR_OVF (1 << PSR_OVF_SHIFT) |
94 | 4b8b8b76 | blueswir1 | #define PSR_CARRY_SHIFT 20 |
95 | 4b8b8b76 | blueswir1 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
96 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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97 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
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98 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
99 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
100 | e8af50a3 | bellard | #define PSR_S (1<<7) |
101 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
102 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
103 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
104 | 2aae2b8e | Igor V. Kovalenko | #endif
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105 | e8af50a3 | bellard | |
106 | 8393617c | Blue Swirl | #define CC_SRC (env->cc_src)
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107 | 8393617c | Blue Swirl | #define CC_SRC2 (env->cc_src2)
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108 | 8393617c | Blue Swirl | #define CC_DST (env->cc_dst)
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109 | 8393617c | Blue Swirl | #define CC_OP (env->cc_op)
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110 | 8393617c | Blue Swirl | |
111 | 8393617c | Blue Swirl | enum {
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112 | 8393617c | Blue Swirl | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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113 | 8393617c | Blue Swirl | CC_OP_FLAGS, /* all cc are back in status register */
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114 | 8393617c | Blue Swirl | CC_OP_DIV, /* modify N, Z and V, C = 0*/
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115 | 8393617c | Blue Swirl | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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116 | 8393617c | Blue Swirl | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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117 | 8393617c | Blue Swirl | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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118 | 8393617c | Blue Swirl | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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119 | 8393617c | Blue Swirl | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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120 | 8393617c | Blue Swirl | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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121 | 8393617c | Blue Swirl | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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122 | 8393617c | Blue Swirl | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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123 | 8393617c | Blue Swirl | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
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124 | 8393617c | Blue Swirl | CC_OP_NB, |
125 | 8393617c | Blue Swirl | }; |
126 | 8393617c | Blue Swirl | |
127 | e8af50a3 | bellard | /* Trap base register */
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128 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
129 | e8af50a3 | bellard | |
130 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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131 | 5210977a | Igor Kovalenko | #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ |
132 | 5210977a | Igor Kovalenko | #define PS_IG (1<<11) /* v9, zero on UA2007 */ |
133 | 5210977a | Igor Kovalenko | #define PS_MG (1<<10) /* v9, zero on UA2007 */ |
134 | 5210977a | Igor Kovalenko | #define PS_CLE (1<<9) /* UA2007 */ |
135 | 5210977a | Igor Kovalenko | #define PS_TLE (1<<8) /* UA2007 */ |
136 | 6ef905f6 | blueswir1 | #define PS_RMO (1<<7) |
137 | 5210977a | Igor Kovalenko | #define PS_RED (1<<5) /* v9, zero on UA2007 */ |
138 | 5210977a | Igor Kovalenko | #define PS_PEF (1<<4) /* enable fpu */ |
139 | 5210977a | Igor Kovalenko | #define PS_AM (1<<3) /* address mask */ |
140 | 3475187d | bellard | #define PS_PRIV (1<<2) |
141 | 3475187d | bellard | #define PS_IE (1<<1) |
142 | 5210977a | Igor Kovalenko | #define PS_AG (1<<0) /* v9, zero on UA2007 */ |
143 | a80dde08 | bellard | |
144 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
145 | 6f27aba6 | blueswir1 | |
146 | 6f27aba6 | blueswir1 | #define HS_PRIV (1<<2) |
147 | 3475187d | bellard | #endif
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148 | 3475187d | bellard | |
149 | e8af50a3 | bellard | /* Fcc */
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150 | ba6a9d8c | blueswir1 | #define FSR_RD1 (1ULL << 31) |
151 | ba6a9d8c | blueswir1 | #define FSR_RD0 (1ULL << 30) |
152 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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153 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
154 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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155 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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156 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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157 | e8af50a3 | bellard | |
158 | ba6a9d8c | blueswir1 | #define FSR_NVM (1ULL << 27) |
159 | ba6a9d8c | blueswir1 | #define FSR_OFM (1ULL << 26) |
160 | ba6a9d8c | blueswir1 | #define FSR_UFM (1ULL << 25) |
161 | ba6a9d8c | blueswir1 | #define FSR_DZM (1ULL << 24) |
162 | ba6a9d8c | blueswir1 | #define FSR_NXM (1ULL << 23) |
163 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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164 | e8af50a3 | bellard | |
165 | ba6a9d8c | blueswir1 | #define FSR_NVA (1ULL << 9) |
166 | ba6a9d8c | blueswir1 | #define FSR_OFA (1ULL << 8) |
167 | ba6a9d8c | blueswir1 | #define FSR_UFA (1ULL << 7) |
168 | ba6a9d8c | blueswir1 | #define FSR_DZA (1ULL << 6) |
169 | ba6a9d8c | blueswir1 | #define FSR_NXA (1ULL << 5) |
170 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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171 | e8af50a3 | bellard | |
172 | ba6a9d8c | blueswir1 | #define FSR_NVC (1ULL << 4) |
173 | ba6a9d8c | blueswir1 | #define FSR_OFC (1ULL << 3) |
174 | ba6a9d8c | blueswir1 | #define FSR_UFC (1ULL << 2) |
175 | ba6a9d8c | blueswir1 | #define FSR_DZC (1ULL << 1) |
176 | ba6a9d8c | blueswir1 | #define FSR_NXC (1ULL << 0) |
177 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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178 | e8af50a3 | bellard | |
179 | ba6a9d8c | blueswir1 | #define FSR_FTT2 (1ULL << 16) |
180 | ba6a9d8c | blueswir1 | #define FSR_FTT1 (1ULL << 15) |
181 | ba6a9d8c | blueswir1 | #define FSR_FTT0 (1ULL << 14) |
182 | 47ad35f1 | blueswir1 | //gcc warns about constant overflow for ~FSR_FTT_MASK
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183 | 47ad35f1 | blueswir1 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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184 | 47ad35f1 | blueswir1 | #ifdef TARGET_SPARC64
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185 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
186 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
187 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
188 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
189 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
190 | 47ad35f1 | blueswir1 | #else
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191 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffe3fffULL |
192 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
193 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
194 | 47ad35f1 | blueswir1 | #endif
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195 | 3a3b925d | blueswir1 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
196 | ba6a9d8c | blueswir1 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
197 | ba6a9d8c | blueswir1 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) |
198 | ba6a9d8c | blueswir1 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) |
199 | ba6a9d8c | blueswir1 | #define FSR_FTT_INVAL_FPR (6ULL << 14) |
200 | e8af50a3 | bellard | |
201 | 4b8b8b76 | blueswir1 | #define FSR_FCC1_SHIFT 11 |
202 | ba6a9d8c | blueswir1 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
203 | 4b8b8b76 | blueswir1 | #define FSR_FCC0_SHIFT 10 |
204 | ba6a9d8c | blueswir1 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
205 | e8af50a3 | bellard | |
206 | e8af50a3 | bellard | /* MMU */
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207 | 0f8a249a | blueswir1 | #define MMU_E (1<<0) |
208 | 0f8a249a | blueswir1 | #define MMU_NF (1<<1) |
209 | e8af50a3 | bellard | |
210 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
211 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
212 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
213 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
214 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
215 | e8af50a3 | bellard | |
216 | 0f8a249a | blueswir1 | #define PG_ACCESSED_BIT 5 |
217 | 0f8a249a | blueswir1 | #define PG_MODIFIED_BIT 6 |
218 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
219 | e8af50a3 | bellard | |
220 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
221 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
222 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
223 | e8af50a3 | bellard | |
224 | 1a14026e | blueswir1 | /* 3 <= NWINDOWS <= 32. */
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225 | 1a14026e | blueswir1 | #define MIN_NWINDOWS 3 |
226 | 1a14026e | blueswir1 | #define MAX_NWINDOWS 32 |
227 | cf495bcf | bellard | |
228 | 6f27aba6 | blueswir1 | #if !defined(TARGET_SPARC64)
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229 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
230 | 6f27aba6 | blueswir1 | #else
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231 | 2065061e | Igor V. Kovalenko | #define NB_MMU_MODES 6 |
232 | 375ee38b | blueswir1 | typedef struct trap_state { |
233 | 375ee38b | blueswir1 | uint64_t tpc; |
234 | 375ee38b | blueswir1 | uint64_t tnpc; |
235 | 375ee38b | blueswir1 | uint64_t tstate; |
236 | 375ee38b | blueswir1 | uint32_t tt; |
237 | 375ee38b | blueswir1 | } trap_state; |
238 | 6f27aba6 | blueswir1 | #endif
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239 | 6ebbf390 | j_mayer | |
240 | 5578ceab | blueswir1 | typedef struct sparc_def_t { |
241 | 5578ceab | blueswir1 | const char *name; |
242 | 5578ceab | blueswir1 | target_ulong iu_version; |
243 | 5578ceab | blueswir1 | uint32_t fpu_version; |
244 | 5578ceab | blueswir1 | uint32_t mmu_version; |
245 | 5578ceab | blueswir1 | uint32_t mmu_bm; |
246 | 5578ceab | blueswir1 | uint32_t mmu_ctpr_mask; |
247 | 5578ceab | blueswir1 | uint32_t mmu_cxr_mask; |
248 | 5578ceab | blueswir1 | uint32_t mmu_sfsr_mask; |
249 | 5578ceab | blueswir1 | uint32_t mmu_trcr_mask; |
250 | 963262de | blueswir1 | uint32_t mxcc_version; |
251 | 5578ceab | blueswir1 | uint32_t features; |
252 | 5578ceab | blueswir1 | uint32_t nwindows; |
253 | 5578ceab | blueswir1 | uint32_t maxtl; |
254 | 5578ceab | blueswir1 | } sparc_def_t; |
255 | 5578ceab | blueswir1 | |
256 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLOAT (1 << 0) |
257 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLOAT128 (1 << 1) |
258 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_SWAP (1 << 2) |
259 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_MUL (1 << 3) |
260 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_DIV (1 << 4) |
261 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLUSH (1 << 5) |
262 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FSQRT (1 << 6) |
263 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FMUL (1 << 7) |
264 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_VIS1 (1 << 8) |
265 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_VIS2 (1 << 9) |
266 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FSMULD (1 << 10) |
267 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_HYPV (1 << 11) |
268 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_CMT (1 << 12) |
269 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_GL (1 << 13) |
270 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ |
271 | 4a2ba232 | Fabien Chouteau | #define CPU_FEATURE_ASR17 (1 << 15) |
272 | 60f356e8 | Fabien Chouteau | #define CPU_FEATURE_CACHE_CTRL (1 << 16) |
273 | 60f356e8 | Fabien Chouteau | |
274 | 5578ceab | blueswir1 | #ifndef TARGET_SPARC64
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275 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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276 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
277 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
278 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
279 | 5578ceab | blueswir1 | #else
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280 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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281 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
282 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
283 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
284 | 5578ceab | blueswir1 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
285 | 5578ceab | blueswir1 | enum {
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286 | 5578ceab | blueswir1 | mmu_us_12, // Ultrasparc < III (64 entry TLB)
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287 | 5578ceab | blueswir1 | mmu_us_3, // Ultrasparc III (512 entry TLB)
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288 | 5578ceab | blueswir1 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
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289 | 5578ceab | blueswir1 | mmu_sun4v, // T1, T2
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290 | 5578ceab | blueswir1 | }; |
291 | 5578ceab | blueswir1 | #endif
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292 | 5578ceab | blueswir1 | |
293 | f707726e | Igor Kovalenko | #define TTE_VALID_BIT (1ULL << 63) |
294 | d1afc48b | Tsuneo Saito | #define TTE_NFO_BIT (1ULL << 60) |
295 | f707726e | Igor Kovalenko | #define TTE_USED_BIT (1ULL << 41) |
296 | f707726e | Igor Kovalenko | #define TTE_LOCKED_BIT (1ULL << 6) |
297 | d1afc48b | Tsuneo Saito | #define TTE_SIDEEFFECT_BIT (1ULL << 3) |
298 | 06e12b65 | Tsuneo Saito | #define TTE_PRIV_BIT (1ULL << 2) |
299 | 06e12b65 | Tsuneo Saito | #define TTE_W_OK_BIT (1ULL << 1) |
300 | 2a90358f | Blue Swirl | #define TTE_GLOBAL_BIT (1ULL << 0) |
301 | f707726e | Igor Kovalenko | |
302 | f707726e | Igor Kovalenko | #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
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303 | d1afc48b | Tsuneo Saito | #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
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304 | f707726e | Igor Kovalenko | #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
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305 | f707726e | Igor Kovalenko | #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
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306 | d1afc48b | Tsuneo Saito | #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
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307 | 06e12b65 | Tsuneo Saito | #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
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308 | 06e12b65 | Tsuneo Saito | #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
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309 | 2a90358f | Blue Swirl | #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
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310 | f707726e | Igor Kovalenko | |
311 | f707726e | Igor Kovalenko | #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
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312 | f707726e | Igor Kovalenko | #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
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313 | f707726e | Igor Kovalenko | |
314 | 06e12b65 | Tsuneo Saito | #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) |
315 | 06e12b65 | Tsuneo Saito | #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) |
316 | 06e12b65 | Tsuneo Saito | |
317 | ccc76c24 | Tsuneo Saito | #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ |
318 | ccc76c24 | Tsuneo Saito | #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ |
319 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ |
320 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ |
321 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ |
322 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ |
323 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ |
324 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ |
325 | ccc76c24 | Tsuneo Saito | #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ |
326 | ccc76c24 | Tsuneo Saito | #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ |
327 | ccc76c24 | Tsuneo Saito | #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ |
328 | ccc76c24 | Tsuneo Saito | #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ |
329 | ccc76c24 | Tsuneo Saito | #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ |
330 | ccc76c24 | Tsuneo Saito | |
331 | ccc76c24 | Tsuneo Saito | #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ |
332 | ccc76c24 | Tsuneo Saito | #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) |
333 | ccc76c24 | Tsuneo Saito | #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ |
334 | ccc76c24 | Tsuneo Saito | #define SFSR_CT_SECONDARY (1ULL << 4) |
335 | ccc76c24 | Tsuneo Saito | #define SFSR_CT_NUCLEUS (2ULL << 4) |
336 | ccc76c24 | Tsuneo Saito | #define SFSR_CT_NOTRANS (3ULL << 4) |
337 | ccc76c24 | Tsuneo Saito | #define SFSR_CT_MASK (3ULL << 4) |
338 | ccc76c24 | Tsuneo Saito | |
339 | 79227036 | Blue Swirl | /* Leon3 cache control */
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340 | 79227036 | Blue Swirl | |
341 | 79227036 | Blue Swirl | /* Cache control: emulate the behavior of cache control registers but without
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342 | 79227036 | Blue Swirl | any effect on the emulated */
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343 | 79227036 | Blue Swirl | |
344 | 79227036 | Blue Swirl | #define CACHE_STATE_MASK 0x3 |
345 | 79227036 | Blue Swirl | #define CACHE_DISABLED 0x0 |
346 | 79227036 | Blue Swirl | #define CACHE_FROZEN 0x1 |
347 | 79227036 | Blue Swirl | #define CACHE_ENABLED 0x3 |
348 | 79227036 | Blue Swirl | |
349 | 79227036 | Blue Swirl | /* Cache Control register fields */
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350 | 79227036 | Blue Swirl | |
351 | 79227036 | Blue Swirl | #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ |
352 | 79227036 | Blue Swirl | #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ |
353 | 79227036 | Blue Swirl | #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ |
354 | 79227036 | Blue Swirl | #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ |
355 | 79227036 | Blue Swirl | #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ |
356 | 79227036 | Blue Swirl | #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ |
357 | 79227036 | Blue Swirl | #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ |
358 | 79227036 | Blue Swirl | #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ |
359 | 79227036 | Blue Swirl | |
360 | 6e8e7d4c | Igor Kovalenko | typedef struct SparcTLBEntry { |
361 | 6e8e7d4c | Igor Kovalenko | uint64_t tag; |
362 | 6e8e7d4c | Igor Kovalenko | uint64_t tte; |
363 | 6e8e7d4c | Igor Kovalenko | } SparcTLBEntry; |
364 | 6e8e7d4c | Igor Kovalenko | |
365 | 8f4efc55 | Igor V. Kovalenko | struct CPUTimer
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366 | 8f4efc55 | Igor V. Kovalenko | { |
367 | 8f4efc55 | Igor V. Kovalenko | const char *name; |
368 | 8f4efc55 | Igor V. Kovalenko | uint32_t frequency; |
369 | 8f4efc55 | Igor V. Kovalenko | uint32_t disabled; |
370 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask; |
371 | 8f4efc55 | Igor V. Kovalenko | int64_t clock_offset; |
372 | 8f4efc55 | Igor V. Kovalenko | struct QEMUTimer *qtimer;
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373 | 8f4efc55 | Igor V. Kovalenko | }; |
374 | 8f4efc55 | Igor V. Kovalenko | |
375 | 8f4efc55 | Igor V. Kovalenko | typedef struct CPUTimer CPUTimer; |
376 | 8f4efc55 | Igor V. Kovalenko | |
377 | 8f4efc55 | Igor V. Kovalenko | struct QEMUFile;
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378 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(struct QEMUFile *f, CPUTimer *s); |
379 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(struct QEMUFile *f, CPUTimer *s); |
380 | 8f4efc55 | Igor V. Kovalenko | |
381 | cb159821 | Andreas Färber | typedef struct CPUSPARCState CPUSPARCState; |
382 | cb159821 | Andreas Färber | |
383 | cb159821 | Andreas Färber | struct CPUSPARCState {
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384 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
385 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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386 | af7bf89b | bellard | target_ulong pc; /* program counter */
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387 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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388 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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389 | dc99a3f2 | blueswir1 | |
390 | dc99a3f2 | blueswir1 | /* emulator internal flags handling */
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391 | d9bdab86 | blueswir1 | target_ulong cc_src, cc_src2; |
392 | dc99a3f2 | blueswir1 | target_ulong cc_dst; |
393 | 8393617c | Blue Swirl | uint32_t cc_op; |
394 | dc99a3f2 | blueswir1 | |
395 | 7c60cc4b | bellard | target_ulong t0, t1; /* temporaries live across basic blocks */
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396 | 7c60cc4b | bellard | target_ulong cond; /* conditional branch result (XXX: save it in a
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397 | 7c60cc4b | bellard | temporary register when possible) */
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398 | 7c60cc4b | bellard | |
399 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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400 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
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401 | 30038fd8 | Richard Henderson | CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
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402 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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403 | cf495bcf | bellard | from PSR) */
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404 | 5210977a | Igor Kovalenko | #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
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405 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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406 | 5210977a | Igor Kovalenko | #endif
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407 | 3475187d | bellard | target_ulong tbr; /* trap base register */
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408 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
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409 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
410 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
411 | e8af50a3 | bellard | int psret; /* enable traps */ |
412 | 5210977a | Igor Kovalenko | #endif
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413 | 327ac2e7 | blueswir1 | uint32_t psrpil; /* interrupt blocking level */
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414 | 327ac2e7 | blueswir1 | uint32_t pil_in; /* incoming interrupt level bitmap */
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415 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
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416 | e80cfcfc | bellard | int psref; /* enable fpu */ |
417 | 2aae2b8e | Igor V. Kovalenko | #endif
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418 | cf495bcf | bellard | int interrupt_index;
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419 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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420 | 1a14026e | blueswir1 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
421 | d720b93d | bellard | |
422 | a316d335 | bellard | CPU_COMMON |
423 | a316d335 | bellard | |
424 | 89aaf60d | Blue Swirl | target_ulong version; |
425 | 89aaf60d | Blue Swirl | uint32_t nwindows; |
426 | 89aaf60d | Blue Swirl | |
427 | e8af50a3 | bellard | /* MMU regs */
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428 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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429 | 3475187d | bellard | uint64_t lsu; |
430 | 3475187d | bellard | #define DMMU_E 0x8 |
431 | 3475187d | bellard | #define IMMU_E 0x4 |
432 | 6e8e7d4c | Igor Kovalenko | //typedef struct SparcMMU
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433 | 6e8e7d4c | Igor Kovalenko | union {
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434 | 6e8e7d4c | Igor Kovalenko | uint64_t immuregs[16];
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435 | 6e8e7d4c | Igor Kovalenko | struct {
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436 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
437 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_primary_context; // use DMMU
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438 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_secondary_context; // use DMMU
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439 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
440 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
441 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
442 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
443 | 6e8e7d4c | Igor Kovalenko | } immu; |
444 | 6e8e7d4c | Igor Kovalenko | }; |
445 | 6e8e7d4c | Igor Kovalenko | union {
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446 | 6e8e7d4c | Igor Kovalenko | uint64_t dmmuregs[16];
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447 | 6e8e7d4c | Igor Kovalenko | struct {
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448 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
449 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_primary_context; |
450 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_secondary_context; |
451 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
452 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
453 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
454 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
455 | 6e8e7d4c | Igor Kovalenko | } dmmu; |
456 | 6e8e7d4c | Igor Kovalenko | }; |
457 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry itlb[64];
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458 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry dtlb[64];
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459 | fb79ceb9 | blueswir1 | uint32_t mmu_version; |
460 | 3475187d | bellard | #else
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461 | 3dd9a152 | blueswir1 | uint32_t mmuregs[32];
|
462 | 952a328f | blueswir1 | uint64_t mxccdata[4];
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463 | 952a328f | blueswir1 | uint64_t mxccregs[8];
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464 | 4d2c2b77 | Blue Swirl | uint32_t mmubpctrv, mmubpctrc, mmubpctrs; |
465 | 4d2c2b77 | Blue Swirl | uint64_t mmubpaction; |
466 | 4017190e | blueswir1 | uint64_t mmubpregs[4];
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467 | 3ebf5aaf | blueswir1 | uint64_t prom_addr; |
468 | 3475187d | bellard | #endif
|
469 | e8af50a3 | bellard | /* temporary float registers */
|
470 | 1f587329 | blueswir1 | float128 qt0, qt1; |
471 | 7a0e1f41 | bellard | float_status fp_status; |
472 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
|
473 | c19148bd | blueswir1 | #define MAXTL_MAX 8 |
474 | c19148bd | blueswir1 | #define MAXTL_MASK (MAXTL_MAX - 1) |
475 | c19148bd | blueswir1 | trap_state ts[MAXTL_MAX]; |
476 | 0f8a249a | blueswir1 | uint32_t xcc; /* Extended integer condition codes */
|
477 | 3475187d | bellard | uint32_t asi; |
478 | 3475187d | bellard | uint32_t pstate; |
479 | 3475187d | bellard | uint32_t tl; |
480 | c19148bd | blueswir1 | uint32_t maxtl; |
481 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
482 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
483 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
484 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
485 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
486 | 3475187d | bellard | uint64_t fprs; |
487 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
488 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *tick, *stick; |
489 | 709f2c1b | Igor V. Kovalenko | #define TICK_NPT_MASK 0x8000000000000000ULL |
490 | 709f2c1b | Igor V. Kovalenko | #define TICK_INT_DIS 0x8000000000000000ULL |
491 | 725cb90b | bellard | uint64_t gsr; |
492 | e9ebed4d | blueswir1 | uint32_t gl; // UA2005
|
493 | e9ebed4d | blueswir1 | /* UA 2005 hyperprivileged registers */
|
494 | c19148bd | blueswir1 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
495 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *hstick; // UA 2005
|
496 | 361dea40 | Blue Swirl | /* Interrupt vector registers */
|
497 | 361dea40 | Blue Swirl | uint64_t ivec_status; |
498 | 361dea40 | Blue Swirl | uint64_t ivec_data[3];
|
499 | 9d926598 | blueswir1 | uint32_t softint; |
500 | 8fa211e8 | blueswir1 | #define SOFTINT_TIMER 1 |
501 | 8fa211e8 | blueswir1 | #define SOFTINT_STIMER (1 << 16) |
502 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_INTRMASK (0xFFFE) |
503 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
|
504 | 3475187d | bellard | #endif
|
505 | 5578ceab | blueswir1 | sparc_def_t *def; |
506 | b04d9890 | Fabien Chouteau | |
507 | b04d9890 | Fabien Chouteau | void *irq_manager;
|
508 | c5f9864e | Andreas Färber | void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); |
509 | b04d9890 | Fabien Chouteau | |
510 | b04d9890 | Fabien Chouteau | /* Leon3 cache control */
|
511 | b04d9890 | Fabien Chouteau | uint32_t cache_control; |
512 | cb159821 | Andreas Färber | }; |
513 | 64a88d5d | blueswir1 | |
514 | e59be77a | Andreas Färber | #include "cpu-qom.h" |
515 | e59be77a | Andreas Färber | |
516 | 5a834bb4 | Blue Swirl | #ifndef NO_CPU_IO_DEFS
|
517 | ab3b491f | Blue Swirl | /* cpu_init.c */
|
518 | e59be77a | Andreas Färber | SPARCCPU *cpu_sparc_init(const char *cpu_model); |
519 | 91736d37 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
520 | 047b39e4 | Stefan Weil | void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
521 | 163fa5ca | Blue Swirl | /* mmu_helper.c */
|
522 | 48585ec5 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
523 | 97b348e7 | Blue Swirl | int mmu_idx);
|
524 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
|
525 | 48585ec5 | blueswir1 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
|
526 | c5f9864e | Andreas Färber | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
|
527 | 91736d37 | blueswir1 | |
528 | 44520db1 | Fabien Chouteau | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
529 | c5f9864e | Andreas Färber | int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
|
530 | 44520db1 | Fabien Chouteau | uint8_t *buf, int len, int is_write); |
531 | 44520db1 | Fabien Chouteau | #define TARGET_CPU_MEMORY_RW_DEBUG
|
532 | 44520db1 | Fabien Chouteau | #endif
|
533 | 44520db1 | Fabien Chouteau | |
534 | 44520db1 | Fabien Chouteau | |
535 | 91736d37 | blueswir1 | /* translate.c */
|
536 | 91736d37 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env);
|
537 | 91736d37 | blueswir1 | |
538 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
539 | 91736d37 | blueswir1 | int cpu_sparc_exec(CPUSPARCState *s);
|
540 | 7a3f1944 | bellard | |
541 | 070af384 | Blue Swirl | /* win_helper.c */
|
542 | c5f9864e | Andreas Färber | target_ulong cpu_get_psr(CPUSPARCState *env1); |
543 | c5f9864e | Andreas Färber | void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
|
544 | 5a834bb4 | Blue Swirl | #ifdef TARGET_SPARC64
|
545 | c5f9864e | Andreas Färber | target_ulong cpu_get_ccr(CPUSPARCState *env1); |
546 | c5f9864e | Andreas Färber | void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
|
547 | c5f9864e | Andreas Färber | target_ulong cpu_get_cwp64(CPUSPARCState *env1); |
548 | c5f9864e | Andreas Färber | void cpu_put_cwp64(CPUSPARCState *env1, int cwp); |
549 | c5f9864e | Andreas Färber | void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
|
550 | 4c6aa085 | Blue Swirl | #endif
|
551 | c5f9864e | Andreas Färber | int cpu_cwp_inc(CPUSPARCState *env1, int cwp); |
552 | c5f9864e | Andreas Färber | int cpu_cwp_dec(CPUSPARCState *env1, int cwp); |
553 | c5f9864e | Andreas Färber | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
554 | 070af384 | Blue Swirl | |
555 | 79227036 | Blue Swirl | /* int_helper.c */
|
556 | c5f9864e | Andreas Färber | void do_interrupt(CPUSPARCState *env);
|
557 | c5f9864e | Andreas Färber | void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); |
558 | b04d9890 | Fabien Chouteau | |
559 | 4c6aa085 | Blue Swirl | /* sun4m.c, sun4u.c */
|
560 | 4c6aa085 | Blue Swirl | void cpu_check_irqs(CPUSPARCState *env);
|
561 | 1a14026e | blueswir1 | |
562 | 60f356e8 | Fabien Chouteau | /* leon3.c */
|
563 | 60f356e8 | Fabien Chouteau | void leon3_irq_ack(void *irq_manager, int intno); |
564 | 60f356e8 | Fabien Chouteau | |
565 | 299b520c | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
566 | 299b520c | Igor V. Kovalenko | |
567 | 299b520c | Igor V. Kovalenko | static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) |
568 | 299b520c | Igor V. Kovalenko | { |
569 | 299b520c | Igor V. Kovalenko | return (x & mask) == (y & mask);
|
570 | 299b520c | Igor V. Kovalenko | } |
571 | 299b520c | Igor V. Kovalenko | |
572 | 299b520c | Igor V. Kovalenko | #define MMU_CONTEXT_BITS 13 |
573 | 299b520c | Igor V. Kovalenko | #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) |
574 | 299b520c | Igor V. Kovalenko | |
575 | 299b520c | Igor V. Kovalenko | static inline int tlb_compare_context(const SparcTLBEntry *tlb, |
576 | 299b520c | Igor V. Kovalenko | uint64_t context) |
577 | 299b520c | Igor V. Kovalenko | { |
578 | 299b520c | Igor V. Kovalenko | return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
|
579 | 299b520c | Igor V. Kovalenko | } |
580 | 299b520c | Igor V. Kovalenko | |
581 | 299b520c | Igor V. Kovalenko | #endif
|
582 | 3475187d | bellard | #endif
|
583 | 3475187d | bellard | |
584 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
585 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
586 | a8170e5e | Avi Kivity | void cpu_unassigned_access(CPUSPARCState *env1, hwaddr addr,
|
587 | b14ef7c9 | Blue Swirl | int is_write, int is_exec, int is_asi, int size); |
588 | b64b6436 | Tsuneo Saito | #if defined(TARGET_SPARC64)
|
589 | a8170e5e | Avi Kivity | hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, |
590 | 2065061e | Igor V. Kovalenko | int mmu_idx);
|
591 | fe8d8f0f | Blue Swirl | #endif
|
592 | b64b6436 | Tsuneo Saito | #endif
|
593 | f0d5e471 | blueswir1 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
594 | 7a3f1944 | bellard | |
595 | e59be77a | Andreas Färber | #ifndef NO_CPU_IO_DEFS
|
596 | e59be77a | Andreas Färber | static inline CPUSPARCState *cpu_init(const char *cpu_model) |
597 | e59be77a | Andreas Färber | { |
598 | e59be77a | Andreas Färber | SPARCCPU *cpu = cpu_sparc_init(cpu_model); |
599 | e59be77a | Andreas Färber | if (cpu == NULL) { |
600 | e59be77a | Andreas Färber | return NULL; |
601 | e59be77a | Andreas Färber | } |
602 | e59be77a | Andreas Färber | return &cpu->env;
|
603 | e59be77a | Andreas Färber | } |
604 | e59be77a | Andreas Färber | #endif
|
605 | e59be77a | Andreas Färber | |
606 | 9467d44c | ths | #define cpu_exec cpu_sparc_exec
|
607 | 9467d44c | ths | #define cpu_gen_code cpu_sparc_gen_code
|
608 | 9467d44c | ths | #define cpu_signal_handler cpu_sparc_signal_handler
|
609 | c732abe2 | j_mayer | #define cpu_list sparc_cpu_list
|
610 | 9467d44c | ths | |
611 | 4d2c2b77 | Blue Swirl | #define CPU_SAVE_VERSION 7 |
612 | b3c7724c | pbrook | |
613 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
614 | 2aae2b8e | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
615 | 2aae2b8e | Igor V. Kovalenko | #define MMU_USER_IDX 0 |
616 | 6f27aba6 | blueswir1 | #define MMU_MODE0_SUFFIX _user
|
617 | 2aae2b8e | Igor V. Kovalenko | #define MMU_USER_SECONDARY_IDX 1 |
618 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE1_SUFFIX _user_secondary
|
619 | 2aae2b8e | Igor V. Kovalenko | #define MMU_KERNEL_IDX 2 |
620 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE2_SUFFIX _kernel
|
621 | 2aae2b8e | Igor V. Kovalenko | #define MMU_KERNEL_SECONDARY_IDX 3 |
622 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE3_SUFFIX _kernel_secondary
|
623 | 2aae2b8e | Igor V. Kovalenko | #define MMU_NUCLEUS_IDX 4 |
624 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE4_SUFFIX _nucleus
|
625 | 2aae2b8e | Igor V. Kovalenko | #define MMU_HYPV_IDX 5 |
626 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE5_SUFFIX _hypv
|
627 | 2aae2b8e | Igor V. Kovalenko | #else
|
628 | 9e31b9e2 | blueswir1 | #define MMU_USER_IDX 0 |
629 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE0_SUFFIX _user
|
630 | 9e31b9e2 | blueswir1 | #define MMU_KERNEL_IDX 1 |
631 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE1_SUFFIX _kernel
|
632 | 2aae2b8e | Igor V. Kovalenko | #endif
|
633 | 2aae2b8e | Igor V. Kovalenko | |
634 | 2aae2b8e | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
635 | c5f9864e | Andreas Färber | static inline int cpu_has_hypervisor(CPUSPARCState *env1) |
636 | 2aae2b8e | Igor V. Kovalenko | { |
637 | 2aae2b8e | Igor V. Kovalenko | return env1->def->features & CPU_FEATURE_HYPV;
|
638 | 2aae2b8e | Igor V. Kovalenko | } |
639 | 2aae2b8e | Igor V. Kovalenko | |
640 | c5f9864e | Andreas Färber | static inline int cpu_hypervisor_mode(CPUSPARCState *env1) |
641 | 2aae2b8e | Igor V. Kovalenko | { |
642 | 2aae2b8e | Igor V. Kovalenko | return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
|
643 | 2aae2b8e | Igor V. Kovalenko | } |
644 | 2aae2b8e | Igor V. Kovalenko | |
645 | c5f9864e | Andreas Färber | static inline int cpu_supervisor_mode(CPUSPARCState *env1) |
646 | 2aae2b8e | Igor V. Kovalenko | { |
647 | 2aae2b8e | Igor V. Kovalenko | return env1->pstate & PS_PRIV;
|
648 | 2aae2b8e | Igor V. Kovalenko | } |
649 | 2065061e | Igor V. Kovalenko | #endif
|
650 | 9e31b9e2 | blueswir1 | |
651 | c5f9864e | Andreas Färber | static inline int cpu_mmu_index(CPUSPARCState *env1) |
652 | 6ebbf390 | j_mayer | { |
653 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
654 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
655 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
656 | 22548760 | blueswir1 | return env1->psrs;
|
657 | 6f27aba6 | blueswir1 | #else
|
658 | 9fd1ae3a | Igor V. Kovalenko | if (env1->tl > 0) { |
659 | 9fd1ae3a | Igor V. Kovalenko | return MMU_NUCLEUS_IDX;
|
660 | 9fd1ae3a | Igor V. Kovalenko | } else if (cpu_hypervisor_mode(env1)) { |
661 | 9e31b9e2 | blueswir1 | return MMU_HYPV_IDX;
|
662 | 2aae2b8e | Igor V. Kovalenko | } else if (cpu_supervisor_mode(env1)) { |
663 | 2aae2b8e | Igor V. Kovalenko | return MMU_KERNEL_IDX;
|
664 | 2aae2b8e | Igor V. Kovalenko | } else {
|
665 | 2aae2b8e | Igor V. Kovalenko | return MMU_USER_IDX;
|
666 | 2aae2b8e | Igor V. Kovalenko | } |
667 | 6f27aba6 | blueswir1 | #endif
|
668 | 6f27aba6 | blueswir1 | } |
669 | 6f27aba6 | blueswir1 | |
670 | c5f9864e | Andreas Färber | static inline int cpu_interrupts_enabled(CPUSPARCState *env1) |
671 | 2df6c2d0 | Igor V. Kovalenko | { |
672 | 2df6c2d0 | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
673 | 2df6c2d0 | Igor V. Kovalenko | if (env1->psret != 0) |
674 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
675 | 2df6c2d0 | Igor V. Kovalenko | #else
|
676 | 2df6c2d0 | Igor V. Kovalenko | if (env1->pstate & PS_IE)
|
677 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
678 | 2df6c2d0 | Igor V. Kovalenko | #endif
|
679 | 2df6c2d0 | Igor V. Kovalenko | |
680 | 2df6c2d0 | Igor V. Kovalenko | return 0; |
681 | 2df6c2d0 | Igor V. Kovalenko | } |
682 | 2df6c2d0 | Igor V. Kovalenko | |
683 | c5f9864e | Andreas Färber | static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) |
684 | d532b26c | Igor V. Kovalenko | { |
685 | d532b26c | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
|
686 | d532b26c | Igor V. Kovalenko | /* level 15 is non-maskable on sparc v8 */
|
687 | d532b26c | Igor V. Kovalenko | return pil == 15 || pil > env1->psrpil; |
688 | d532b26c | Igor V. Kovalenko | #else
|
689 | d532b26c | Igor V. Kovalenko | return pil > env1->psrpil;
|
690 | d532b26c | Igor V. Kovalenko | #endif
|
691 | d532b26c | Igor V. Kovalenko | } |
692 | d532b26c | Igor V. Kovalenko | |
693 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
|
694 | c5f9864e | Andreas Färber | static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp) |
695 | 6e68e076 | pbrook | { |
696 | f8ed7070 | pbrook | if (newsp)
|
697 | 6e68e076 | pbrook | env->regwptr[22] = newsp;
|
698 | 6e68e076 | pbrook | env->regwptr[0] = 0; |
699 | 6e68e076 | pbrook | /* FIXME: Do we also need to clear CF? */
|
700 | 6e68e076 | pbrook | /* XXXXX */
|
701 | 6e68e076 | pbrook | printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
|
702 | 6e68e076 | pbrook | } |
703 | 6e68e076 | pbrook | #endif
|
704 | 6e68e076 | pbrook | |
705 | 7a3f1944 | bellard | #include "cpu-all.h" |
706 | 7a3f1944 | bellard | |
707 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
|
708 | f4b1a842 | blueswir1 | /* sun4u.c */
|
709 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
|
710 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer); |
711 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
|
712 | c5f9864e | Andreas Färber | trap_state* cpu_tsptr(CPUSPARCState* env); |
713 | f4b1a842 | blueswir1 | #endif
|
714 | c28ae41e | Richard Henderson | void cpu_restore_state2(CPUSPARCState *env, uintptr_t retaddr);
|
715 | f4b1a842 | blueswir1 | |
716 | f838e2c5 | Blue Swirl | #define TB_FLAG_FPU_ENABLED (1 << 4) |
717 | f838e2c5 | Blue Swirl | #define TB_FLAG_AM_ENABLED (1 << 5) |
718 | f838e2c5 | Blue Swirl | |
719 | c5f9864e | Andreas Färber | static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, |
720 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
721 | 6b917547 | aliguori | { |
722 | 6b917547 | aliguori | *pc = env->pc; |
723 | 6b917547 | aliguori | *cs_base = env->npc; |
724 | 6b917547 | aliguori | #ifdef TARGET_SPARC64
|
725 | 6b917547 | aliguori | // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
|
726 | f838e2c5 | Blue Swirl | *flags = (env->pstate & PS_PRIV) /* 2 */
|
727 | 9fd1ae3a | Igor V. Kovalenko | | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */ |
728 | 9fd1ae3a | Igor V. Kovalenko | | ((env->tl & 0xff) << 8) |
729 | 9fd1ae3a | Igor V. Kovalenko | | (env->dmmu.mmu_primary_context << 16); /* 16... */ |
730 | f838e2c5 | Blue Swirl | if (env->pstate & PS_AM) {
|
731 | f838e2c5 | Blue Swirl | *flags |= TB_FLAG_AM_ENABLED; |
732 | f838e2c5 | Blue Swirl | } |
733 | f838e2c5 | Blue Swirl | if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
|
734 | f838e2c5 | Blue Swirl | && (env->fprs & FPRS_FEF)) { |
735 | f838e2c5 | Blue Swirl | *flags |= TB_FLAG_FPU_ENABLED; |
736 | f838e2c5 | Blue Swirl | } |
737 | 6b917547 | aliguori | #else
|
738 | 6b917547 | aliguori | // FPU enable . Supervisor
|
739 | f838e2c5 | Blue Swirl | *flags = env->psrs; |
740 | f838e2c5 | Blue Swirl | if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
|
741 | f838e2c5 | Blue Swirl | *flags |= TB_FLAG_FPU_ENABLED; |
742 | f838e2c5 | Blue Swirl | } |
743 | f838e2c5 | Blue Swirl | #endif
|
744 | f838e2c5 | Blue Swirl | } |
745 | f838e2c5 | Blue Swirl | |
746 | f838e2c5 | Blue Swirl | static inline bool tb_fpu_enabled(int tb_flags) |
747 | f838e2c5 | Blue Swirl | { |
748 | f838e2c5 | Blue Swirl | #if defined(CONFIG_USER_ONLY)
|
749 | f838e2c5 | Blue Swirl | return true; |
750 | f838e2c5 | Blue Swirl | #else
|
751 | f838e2c5 | Blue Swirl | return tb_flags & TB_FLAG_FPU_ENABLED;
|
752 | f838e2c5 | Blue Swirl | #endif
|
753 | f838e2c5 | Blue Swirl | } |
754 | f838e2c5 | Blue Swirl | |
755 | f838e2c5 | Blue Swirl | static inline bool tb_am_enabled(int tb_flags) |
756 | f838e2c5 | Blue Swirl | { |
757 | f838e2c5 | Blue Swirl | #ifndef TARGET_SPARC64
|
758 | f838e2c5 | Blue Swirl | return false; |
759 | f838e2c5 | Blue Swirl | #else
|
760 | f838e2c5 | Blue Swirl | return tb_flags & TB_FLAG_AM_ENABLED;
|
761 | 6b917547 | aliguori | #endif
|
762 | 6b917547 | aliguori | } |
763 | 6b917547 | aliguori | |
764 | 3993c6bd | Andreas Färber | static inline bool cpu_has_work(CPUState *cpu) |
765 | f081c76c | Blue Swirl | { |
766 | 3993c6bd | Andreas Färber | CPUSPARCState *env1 = &SPARC_CPU(cpu)->env; |
767 | 3993c6bd | Andreas Färber | |
768 | f081c76c | Blue Swirl | return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
|
769 | f081c76c | Blue Swirl | cpu_interrupts_enabled(env1); |
770 | f081c76c | Blue Swirl | } |
771 | f081c76c | Blue Swirl | |
772 | f081c76c | Blue Swirl | #include "exec-all.h" |
773 | f081c76c | Blue Swirl | |
774 | c5f9864e | Andreas Färber | static inline void cpu_pc_from_tb(CPUSPARCState *env, TranslationBlock *tb) |
775 | f081c76c | Blue Swirl | { |
776 | f081c76c | Blue Swirl | env->pc = tb->pc; |
777 | f081c76c | Blue Swirl | env->npc = tb->cs_base; |
778 | f081c76c | Blue Swirl | } |
779 | f081c76c | Blue Swirl | |
780 | 7a3f1944 | bellard | #endif |