ppc: Fix up usermode only builds
The recent usage of MemoryRegion in kvm_ppc.h breaks builds withCONFIG_USER_ONLY=y. This patch fixes it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>Signed-off-by: Alexander Graf <agraf@suse.de>
KVM: PPC: Override host vmx/vsx/dfp only when information known
The -cpu host feature tries to find out the host capabilities basedon device tree information. However, we don't always have that availablebecause it's an optional property in dt.
So instead of force unsetting values depending on an unreliable source...
PPC: Disable non-440 CPUs for ppcemb target
The sole reason we have the ppcemb target is to support MMUs that haveless than the usual 4k possible page size. There are very few of thesechips and I don't want to add additional QA and testing burden to everyone...
pseries: Correct vmx/dfp handling in both KVM and TCG cases
Currently, when KVM is enabled, the pseries machine checks if the hostCPU supports VMX, VSX and/or DFP instructions and advertisesaccordingly in the guest device tree. It does this regardless of what...
PPC: Bump qemu-system-ppc to 64-bit physical address space
Some 32-bit PPC CPUs can use up to 36 bit of physical address space.Treat them accordingly in the qemu-system-ppc binary type.
Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Remove broken partial PVR matching
The ppc target contains a ppc_find_by_pvr() function, which looks up aCPU spec based on a PVR (that is, based on the value in the target cpu'sProcessor Version Register). PVR values contain information on both the...
ppc: First cut implementation of -cpu host
For convenience with kvm, x86 allows the user to specify -cpu host on theqemu command line, which means make the guest cpu the same as the hostcpu. This patch implements the same option for ppc targets.
For now, this just read the host PVR (Processor Version Register) and...
ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3
This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3.This allows -cpu host to be used on these host cpus.
pseries: Support SMT systems for KVM Book3S-HV
Alex Graf has already made qemu support KVM for the pseries machinewhen using the Book3S-PR KVM variant (which runs the guest inusermode, emulating supervisor operations). This code allows gets usvery close to also working with KVM Book3S-HV (using the hypervisor...
pseries: Allow KVM Book3S-HV on PPC970 CPUS
At present, using the hypervisor aware Book3S-HV KVM will only workwith qemu on POWER7 CPUs. PPC970 CPUs also have hypervisorcapability, but they lack the VRMA feature which makes assigning guestmemory easier....
pseries: Use Book3S-HV TCE acceleration capabilities
The pseries machine of qemu implements the TCE mechanism used as avirtual IOMMU for the PAPR defined virtual IO devices. Because thePAPR spec only defines a small DMA address space, the guest VIOdrivers need to update TCE mappings very frequently - the virtual...
Set an invalid-bits mask for each SPE instructions
SPE instructions are defined by pairs. Currently, the invalid-bits mask is setfor the first instruction, but the second one can have a different mask.
example:GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),...
ppc: Generalize the kvmppc_get_clockfreq() function
Currently the kvmppc_get_clockfreq() function reads the host's clockfrequency from /proc/device-tree, which is useful to past to the guestin KVM setups. However, there are some other host propertiesadvertised in the device tree which can also be relevant to the...
pseries: Add device tree properties for VMX/VSX and DFP under kvm
Sufficiently recent PAPR specifications define properties "ibm,vmx" and "ibm,dfp" on the CPU node which advertise whether the VMX vectorextensions (or the later VSX version) and/or the Decimal Floating...
PPC: booke timers
While working on the emulation of the freescale p2010 (e500v2) I realized thatthere's no implementation of booke's timers features. Currently mpc8544 usesppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (forexample booke uses different SPR)....
KVM: PPC: Use HIOR setting for -M pseries with PR KVM
When running with PR KVM, we need to set HIOR directly. Thankfully thereis now a new interface to set registers individually so we can just use thatand poke HIOR into the guest vcpu's HIOR register....
Gdbstub: handle read of fpscr
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Alexander Graf <agraf@suse.de>
kvm: ppc: booke206: use MMU API
Share the TLB array with KVM. This allows us to set the initial TLBboth on initial boot and reset, is useful for debugging, and couldeventually be used to support migration.
Signed-off-by: Scott Wood <scottwood@freescale.com>...
ppc: booke206: add "info tlb" support
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
This definition is backward compatible with MAV=1.0 as long asthe guest does not set reserved bits in MAS1/MAS4.
Also, fix the shift in booke206_tlb_to_page_size -- it's the basethat should be able to hold a 4G page size, not the shift count....
Implement POWER7's CFAR in TCG
This patch implements support for the CFAR SPR on POWER7 (Come FromAddress Register), which snapshots the PC value at the time of a branch oran rfid. The latest powerpc-next kernel also catches it and can show it inxmon or in the signal frames....
PPC: Enable to use PAPR with PR style KVM
When running PR style KVM, we need to tell the kernel that we wantto run in PAPR mode now. This means that we need to pass some moreregister information down and enable papr mode. We also need to alignthe HTAB to htab_size boundary....
PPC: KVM: Remove kvmppc_read_host_property
We just got rid of the last user of kvmppc_read_host_property, so wecan now safely remove it.
PPC: KVM: Add stubs for kvm helper functions
We have a bunch of helper functions that don't have any stubs for them in casewe don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc canoptimize them out pretty well, but we should really provide them....
PPC: bamboo: Move host fdt copy to target
We have some code in generic kvm_ppc.c that is only used by 440. Move tothe 440 specific device code.
PPC: KVM: Add generic function to read host clockfreq
We need to find out the host's clock-frequency when running on KVM, solet's export a respective function.
v1 -> v2:
- enable 64bit values
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
core: remove qemu_service_io
qemu_service_io was mainly an alias to qemu_notify_event,currently used only by PPC for timer hack, so callqemu_notify_event directly.
Signed-off-by: Frediano Ziglio <freddy77@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove blanks before \n in output strings
Those blanks violate the coding conventions, seescripts/checkpatch.pl.
Blanks missing after colons in the changed lines were added.
This patch does not try to fix tabs, long lines and otherproblems in the changed lines, therefore checkpatch.pl reports...
PPC: E500: Add ESR bit definitions
The BookE spec specifies a number of ESR bits. Add defines for themso we can use them later on.
Reported-by: Jason Wessel <jason.wessel@windriver.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
PPC: E500: Inject SPE exception on invalid SPE access
When accessing an SPE instruction despite it being not available,throw an SPE exception instead of an APU exception. That way theguest knows what's going on and actually uses SPE.
Reported-by: Jason Wessel <jason.wessel@windriver.com>...
PPC: E500: Set ESR values
When an exception occurs on BookE, we need to set ESR bits to exposeto the guest information on what exactly happened. Add the obvious ones.
Reported-by: Jason Wessel <jason.wessel@windriver.com>Signed-off-by: Alexander Graf <agraf@suse.de>...
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
Avoid allocating TCG resources in non-TCG mode
Do not allocate TCG-only resources like the translation buffer whenrunning over KVM or XEN. Saves a "few" bytes in the qemu address spaceand is also conceptually cleaner.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
target-alpha, target-ppc: Remove unnecessary setjmp.h include
Remove the include of setjmp.h from the cpu.h of target-alphaand target-ppc. This is unnecessary because cpu-defs.h alreadyincludes this header; this change brings these two targetsinto line with all the rest....
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
kvm: ppc: Drop KVM_CAP build dependencies
No longer needed with accompanied kernel headers.
CC: Alexander Graf <agraf@suse.de>Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Reviewed-by: Alexander Graf <agraf@suse.de>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: ppc: Drop CONFIG_KVM_PPC_PVR
Required header support is now unconditionally available.
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types andallocated that union. While it's a waste of memory (and cache) to allocateTLB information for a TLB type with much information when you only needlittle, it also inflicts another issue....
PPC: E500: Use MAS registers instead of internal TLB representation
The natural format for e500 cores to do TLB manipulation with are the MASregisters. Instead of converting them into some internal representationand back again when the guest reads them, we can just keep the data...
PPC: Only set lower 32bits with mtmsr
As Nathan pointed out correctly, the mtmsr instruction does not modifythe high 32 bits of MSR. It also doesn't matter if SF is set or not,the instruction always behaves the same.
This patch moves it a bit closer to the spec....
target-ppc: Handle memory-forced I/O controller access
On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07Fis special-cased as memory-forced I/O controller access. It is supposedto be checked immediately if T=1, bypassing all protection mechanisms...
Fix compilation warning due to missing header for sigaction (followup)
This patch removes all references to signal.h when qemu-common.h is includedas they become redundant.
Signed-off-by: Alexandre Raymond <cerbere@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-ppc: remove old CONFIG_SOFTFLOAT #ifdef
target-ppc has been switched to softfloat only long ago, but afew #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.
Cc: Alexander Graf <agraf@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
ppc: Fix compilation for ppc64-softmmu
When QEMU was configured with --enable-debug-tcg,compilation fails in spr_write_booke206_mmucsr0() and inspr_write_booke_pid(). Similar changes are also neededin conditional code which is normally unused.
Cc: Alexander Graf <agraf@suse.de>...
PPC: fix sregs usage on booke
When compiling qemu with kvm support on BookE PPC machines, I getthe following error:
cc1: warnings being treated as errors /tmp/qemu/target-ppc/kvm.c: In function 'kvm_arch_get_registers': /tmp/qemu/target-ppc/kvm.c:188: error: unused variable 'sregs'...
Merge branch 'trivial-patches' of git://repo.or.cz/qemu/stefanha
Fix typos in comments (chek -> check)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
w32: Fix compilation and replace non-portable usage of ulong
ulong is undefined for w32 (and maybe other) compilations.Replace it by uintptr_t (which also fixes compilation for w64and is a better choice for pointer to integer conversions).
Cc: Aurelien Jarno <aurelien@aurel32.net>...
Fix a bug in mtsr/mtsrin emulation on ppc64
Early ppc64 CPUs include a hack to partially simulate the ppc32 segmentregisters, by translating writes to them into writes to the SLB. This isnot used by any current Linux kernel, but it is used by the openbios used...
PPC: Add GS MSR definition
The BookE specification defines MSR bit 28 as Guest State. Add itto the list of MSR macros.
PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currentlyselected CPU emulation, we have a feature mask of what exactly the respectiveinstruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
kvm: ppc: detect old headers
When compiling Qemu with older kernel headers, the PVR settingmechanism isn't available yet. Unfortunately, back then I didn't adda capability we could check against, so all we can do is add a configuretest to see if we support PVR setting. For BookE, we don't care yet....
kvm: ppc: fixes for KVM_SET_SREGS on init
Classic/server ppc has had SREGS for a while now (though I think notalways?), but it's still missing for booke. Check the capability beforecalling KVM_SET_SREGS.
Without this, booke kvm fails to boot as of commit...
monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),and display them in "info registers".
Also get CR and PID from the existing KVM_GET_REGS.
Fix typos in comments (instanciation -> instantiation)
Fix typo in comment (embeded -> embedded)
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
target-ppc: fix SPE comparison functions
efstst*() functions are fast SPE funtions which do not take into accountspecial values (infinites, NaN, etc.), while efscmp*() functions areIEEE754 compliant.
Given that float32_*() functions are IEEE754 compliant, the efscmp*()...
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
target-ppc: remove #ifdef FLOAT128
Now that PPC defaults to softfloat which always provides float128support, there is no need to keep two version of the code, depending iffloat128 support is available or not. Suggested by Peter Maydell.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
ppce500_mpc8544ds: Fix compile with --enable-debug and --disable-kvm
When configured with --enable-debug, we compile without optimization.This means that the function mpc8544_copy_soc_cell() in ppce500_mpc8544ds.cis not optimized out, even though it is never called without kvm. That in...
Use existing helper function to implement popcntd instruction
The recent patches adding partial support for POWER7 cpu emulation includedimplementing the popcntd instruction. The support for this was open coded,but host-utils.h already included a function implementing an equivalent...
Implement PAPR VPA functions for pSeries shared processor partitions
Shared-processor partitions are those where a CPU is time-sliced betweenpartitions, rather than being permanently dedicated to a singlepartition. qemu emulated partitions, since they are just scheduled with...
Implement PAPR CRQ hypercalls
This patch implements the infrastructure and hypercalls necessary for thePAPR specified CRQ (Command Request Queue) mechanism. This generalrequest queueing system is used by many of the PAPR virtual IO devices,including the virtual scsi adapter....
Clean up slb_lookup() function
The slb_lookup() function, used in the ppc translation path returns anumber of slb entry fields in reference parameters. However, only oneof the two callers of slb_lookup() actually wants this information.
This patch, therefore, makes slb_lookup() return a simple pointer to the...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't(quite) get the hash value for the ppc hashed page table. Instead itgets the hash shifted - effectively the offset of the hash bucket within...
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()has a mix of common and 32 or 64 bit specific code. However thedivision is not done terribly well which results in a lot of messy codeflipping between common and divided paths....
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used onpowerpc MMUs were 256MB in size. This was the only option on all hashpage table based 32-bit powerpc cpus, and on the earlier 64-bit hash pagetable based cpus. However, newer 64-bit cpus also permit 1TB segments...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full systempartitions, the guest does not have direct access to the hardware pagetable. Instead, the pagetable exists in hypervisor memory, and the guest...
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 isstoreed in a structure with the unhelpfully named fields 'tmp'and 'tmp64'. While the layout in these fields does match thedescription of the SLB in the architecture document, it is not...
Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a specialhypervisor mode, and a corresponding form of the system callinstruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
Implement missing parts of the logic for the POWER PURR
The PURR (Processor Utilization Resource Register) is a register foundon recent POWER CPUs. The guts of implementing it at least enough toget by are already present in qemu, however some of the helper...
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introducedin POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results...
target-ppc: ext32u instead of andi with constant
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: add support for 6 SPE instructions
Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}}
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Merge remote branch 'qemu-kvm/uq/master' into staging
change all other clock references to use nanosecond resolution accessors
This was done with:
sed -i 's/qemu_get_clock\>/qemu_get_clock_ns/' \ $(git grep -l 'qemu_get_clock\>' ) sed -i 's/qemu_new_timer\>/qemu_new_timer_ns/' \ $(git grep -l 'qemu_new_timer\>' )...
kvm: Align kvm_arch_handle_exit to kvm_cpu_exec changes
Make the return code of kvm_arch_handle_exit directly usable forkvm_cpu_exec. This is straightforward for x86 and ppc, just s390would require more work. Avoid this for now by pushing the return code...
kvm: Rename kvm_arch_process_irqchip_events to async_events
We will broaden the scope of this function on x86 beyond irqchip events.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: ppc: Fix breakage of kvm_arch_pre_run/process_irqchip_events
Commit 7a39fe5882 failed to convert the right arch function.
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Handle icount for powerpc tbl/tbu/decr load and store.
Handle option '-icount X' on powerpc targets.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>