softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Gdbstub: Fix back-trace on SPARC32
Gdb expects all registers windows to be flushed in ram, which is not the casein Qemu. Therefore the back-trace generation doesn't work. This patch adds afunction to handle reads (and only read) in stack frames as if windows were...
Sparc64: remove useless variable
Remove a useless variable, spotted by clang analyzer:/src/qemu/target-sparc/op_helper.c:3904:18: warning: unused variable 'tmp' [-Wunused-variable] target_ulong tmp = val;The error message is actually incorrect since the variable is used....
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
Fix handling of conditional branches in delay slot of a conditional branch
Check whether dc->npc is dynamic before using its value for branch.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: fix non-faulting unassigned memory accesses
Commit b14ef7c9ab41ea824c3ccadb070ad95567cca84eintroduced cpu_unassigned_access() function. On Sparc,the function does not restore AREG0 used for global CPUStateon function exit, causing bugs with non-faulting unassigned...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destinationregisters.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: implement %fprs dirty bits
Implement %fprs.DU/DL bits.The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31and %f32-63 respectively.
target-sparc: Fix compiler errors (format strings)
This change is needed because commit 06e12b65now uses an unsigned long long value(uint64_t && unsigned long long => unsigned long long).
Cc: Tsuneo Saito <tsnsaito@gmail.com>Cc: Blue Swirl <blauwirbel@gmail.com>...
SPARC64: implement addtional MMU faults related to nonfaulting load
This patch implements MMU faults caused by TTE.NFO and TTE.E:- access other than nonfaulting load to a page marked NFO should raise data_access_exception- nonfaulting load to a page marked with E bit should raise...
SPARC64: implement MMU miss traps on nonfaulting loads
Nonfaulting loads should raise fast_data_access_MMU_miss traps asnormal loads do. It is up to the guest OS kernel that detect MMU misseson nonfaulting load instructions and make them complete without signaling....
SPARC64: fix fault status overwritten on nonfaulting load
cpu_get_phys_page_nofault() calls get_physical_address() twice,that results in overwriting the fault status in the SFSR.We need this change in order for nonfaulting loads to raising MMU faultsas normal loads do....
SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault()
This patch makes cpu_get_phys_page_debug() independent fromcpu_get_phys_page_nofault() in advance of implementing nonfaulting load.This also modifies cpu_get_phys_page_nofault() to be compiled only on...
SPARC64: introduce a convenience function for getting physical addresses
Introduce cpu_sparc_get_phys_page() to be used as a help for splittingcpu_get_phys_page_debug() from cpu_get_phys_page_nofault().
SPARC64: SFSR cleanup and fix
Add macros for SFSR fields and use macros instead of magic numbers.Also fix the update of the register fields on MMU faults.
SPARC64: TTE bits cleanup
Add macros for TTE bits and modify to use macros instead ofmagic numbers.
Fix unassigned memory access handling
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memoryaccess handling. Fix them by always passing CPUState to the handlers.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: treat UA2007 ASI_BLK_* as translating ASIs.
UA2007 ASI_BLK_* should be added in is_translating_asi().
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: add missing break on fmovdcc
"break" is missing on V9 fmovdcc (%icc).
SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions(fcmp*<16|32>) are not FP registers but general purpose r registers.Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>...
Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to checkfor FPU enable state and 32 bit address masking on Sparc64.
Fix by using TB flags instead.
SPARC64: C99 comment fix for block-transfer ASIs
Fixed C99 comments on block-tranfer ASIs.
SPARC64: Add JPS1 ASI_BLK_AIU[PS]L ASIs for ldfa and stfa
Support JPS1 little endian block transfer ASIs.
SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfa
Support UA2007 block store ASIs for stfa instructions.
SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for ldfa
Support UA2007 block load ASIs for ldfa instructions.
SPARC64: fp_disabled checks on stfa/stdfa/stqfa
stfa/stdfa/stqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructionswith non block-store ASIs.
SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
SPARC64: Implement ldfa/lddfa/ldqfa instructions properly
This patch implements sparcv9 ldfa/lddfa/ldqfa instructionswith non block-load ASIs.
fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx
udivx and sdvix don't modify condition flags, so they shall notoverwrite cpu_cc_*
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
sparc: move do_interrupt to helper.c
do_interrupt() was mixing CPUState pointer passed from callerand global env (AREG0).
Fix by moving the function to helper.c. Introduce a helper for callingchange_pstate() safely from outside of execution context.
sparc: fix coding style of the area to be moved
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, saveand load all MXCC registers.
Fix compilation warning due to missing header for sigaction (followup)
This patch removes all references to signal.h when qemu-common.h is includedas they become redundant.
Signed-off-by: Alexandre Raymond <cerbere@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
sparc64: fix incorrect BPcc target sign extension
Fix wrong number of bits used when sign extending the branch offset of BPccinstructions.
Reported-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: fix wrpstate and wrtl on delay slot
Use TCG local to work around TCG register flush due to a branch.
Thanks to Artyom Tarasenko, Igor Kovalenko and Aurelien Jarno.
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC: Fix Leon3 cache control
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.cwhich leads to segfault error with the global "env".
Now cache control is a CPU feature and everything is handled in op_helper.c.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>...
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (moreinformation on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.Three devices are implemented: uart, timers and IRQ manager....
SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: fix NaN handling
Fix several bugs in NaN handling: * e in fcmpe* only changes qNaN handling * FCC is unchanged if an exception is raised * clear previous FTT before setting it
Reported-by: Mateusz Loskot <mateusz@loskot.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: fix udiv(cc) and sdiv(cc)
Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes ona Debian Etch image. The commit itself is fine, but it triggers a bugdue to wrong computation of flags for udiv(cc) and sdiv(cc).
This patch only compute cc_src2 for the cc version of udiv/sdiv. It...
Sparc: implement monitor command 'info tlb'
Use existing dump_mmu() to implement monitor command 'info tlb'.
target-sparc: Use fprintf_function (format checking)
This change was missing in commit9a78eead0c74333a394c0f7bbfc4423ac746fcd5.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: remove unused functions cpu_lock(), cpu_unlock()
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
sparc64: fix umul and smul insns
- truncate and sign or zero extend operands before multiplication- factor out common code to gen_op_multiply() with parameter to sign/zero extend- call gen_op_multiply from gen_op_umul and gen_op_smul
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
sparc64: fix udiv and sdiv insns
- truncate second operand to 32bit
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: improve ldf and stf insns
- implemented block load/store primary/secondary with user privilege
sparc64: use symbolic name for MMU index v1
- use symbolic name for MMU indexv0->v1:- change debug traces to DPRINTF_MMU- fix debug trace function names
sparc64: fix ldxfsr insn
- rearrange code to break from switch when appropriate- allow deprecated ldfsr insn
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns- address masking for lddf and stdf insns- address masking for translating ASI (Ultrasparc IIi)v0->v1:- move arch-specific code to helpers and drop more ifdefs at call sites...
sparc64: fix tag access register on mmu traps
- set mmu tag access register on FAULT and PROT traps as well
sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)
SuperSPARC MMU Breakpoint Action register is used by OBP at boot
The patch allows booting Solaris and some other OS withSPARCStation-20 OBP.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>...
sparc64: fix user emulator build
Accesses with _nucleus prefix are not available when building useremulators: CC sparc64-linux-user/op_helper.occ1: warnings being treated as errors/src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi':...
sparc64: fix 128-bit atomic load from nucleus context v1
- change 128-bit atomic loads to reference nucleus contextv0->v1: dropped disassembler changeSigned-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: flush translations on mmu context change
- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed...
sparc64: fix mmu context at trap levels above zero
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero- cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed...
sparc64: fix dump_mmu to look for global bit in tte value instead of tag
sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu- conditionally set hypervisor bit in hpstate register- reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well...
sparc64: generate data access exception on RW violation
- separate PRIV and PROT handling- DPRINTF_MMU macro to clean up debug code- dump mmu_idx, trap level and mmu context registers along with address translation values
Fix %lld or %llx printf format use
target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs. By avoiding anexternal function call, we generate near-optimal code forthe common cases of add+addx (double-word arithmetic) andcmp+addx (a setcc pattern)....
target-sparc: Simplify ICC generation.
Use int32 types instead of target_ulong when computing ICC. Thissimplifies the generated code for 32-bit host and 64-bit guest.Use the same simplified expressions for ICC as were already usedfor XCC in carry flag generation....
target-sparc: Fix compilation with --enable-debug.
Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: move DT and QT defines to op_helper.c
sparc64: fix TT_WOTHER value
- fix off by one error in spill trap number bit for other window (must be bit 5)- fixes invalid instruction issue with HelenOS
sparc64: fix mmu demap operand typo
- must use store address operand to demap, not store value
target-sparc: Fix wrong printf argument
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoidwrong output on big endian hosts. We could also use TARGET_FMT_lx,but that would print 8 instead of 2 digits.
Cc: Blue Swirl <blauwirbel@gmail.com>...
sparc: Fix lazy flag calculation on interrupts, refactor
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlierflags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actualfunctions to op_helper.c.
Thanks to Igor Kovalenko for reporting....
sparc: lazy C flag calculation
Calculate only the carry flag for ADDX/SUBX instead of fullset of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlierversion.
sparc64: fix build with older gccs
Fix errors missed in 2065061ede22d401aae2ce995c3af54db9d28639: CC sparc64-softmmu/helper.occ1: warnings being treated as errors/src/qemu/target-sparc/helper.c: In function 'get_physical_address':/src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function...
sparc64: handle asi referencing nucleus and secondary MMU contexts
- increase max supported MMU modes to 6- handle nucleus context asi- handle secondary context asi- handle non-faulting loads from secondary context
sparc64: implement global translation table entries v1
- match global tte against any context- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb- should fix gcc warning about uninitialized context variable
target-sparc: Fix -singlestep.
Single-stepping was not properly updating npc, resulting in someinstructions being executed twice. In addition, we were emittingdead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step...
target-sparc: Fix address masking in ldqf and stqf.
Use address_mask on both addr and addr+8 in both these routines,rather than explicit masking with 0xffffffff.
Reformulate address_mask to return a result, rather than maskinga pass-by-reference argument....
Fix harmless if statements with empty body, spotted by clang
These clang errors are harmless but worth fixing: CC ppc-softmmu/usb-ohci.o/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body] ohci->ctrl_head, ohci->ctrl_cur);...
target-sparc: Free instruction temporaries.
Rather than creating new temporaries for constants, use theones created in disas_sparc_insn. Remember the temps createdthere so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:...
target-sparc: Fix TARGET_{PHYS,VIRT}_ADDR_SPACE_BITS.
The 32 and 64-bit definitions were swapped in the ifdef.
Sparc: fix PC/NPC during FPU traps
All FPU instructions can trap, so save PC/NPC state beforeexecuting them.
Sparc: fix exceptions in delay slot
Fix a case where an exception happens with theinstruction in the delay slot.
Recovery of branch condition in the exception handlingcode was not converted to TCG. Because the conditionwas bogus, wrong NPC could be selected from the two...
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-sparc: fix --enable-debug build for 64 bit host
b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixedthe compilation for 32 bit hosts, but introduceda new error for 64 bit hosts:
tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sparc: fix --enable-debug build
Use 32-bit arithmetic for the address offset calculation to fix abuild failure on 32-bit hosts.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>