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# Date Author Comment
bf45a2e6 04/27/2013 12:02 am Aurelien Jarno

target-ppc: optimize fabs, fnabs, fneg

fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.

Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
fcfda20f 04/27/2013 12:02 am Aurelien Jarno

target-ppc: emulate cmpb instruction

Needed for Power ISA version 2.05 compliance.

Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
Signed-off-by: Alexander Graf <>
9baea4a3 03/22/2013 04:28 pm David Gibson

target-ppc: Remove vestigial PowerPC 620 support

The PowerPC 620 was the very first 64-bit PowerPC implementation, but
hardly anyone ever actually used the chips. qemu notionally supports the
620, but since we don't actually have code to implement the segment table,...
23ad1d5d 02/23/2013 07:25 pm Richard Henderson

target-ppc: Use mul*2 in mulh* insns

Cc: Alexander Graf <>
Signed-off-by: Richard Henderson <>
Signed-off-by: Blue Swirl <>
8e33944f 02/01/2013 02:52 am Alexander Graf

PPC: Unify dcbzl code path

The bit that makes a dcbz instruction a dcbzl instruction was declared as
reserved in ppc32 ISAs. However, hardware simply ignores the bit, making
code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.

Thus, mark the bit as unreserved so that we properly emulate a simple dcbz...
68c2dd70 01/07/2013 06:37 pm Alexander Graf

PPC: Bring EPR support closer to reality

We already used to support the external proxy facility of FSL MPICs,
but only implemented it halfway correctly.

This patch adds support for

  • dynamic enablement of the EPR facility
  • interrupt acknowledgement only when the interrupt is delivered...
022c62cb 12/19/2012 09:31 am Paolo Bonzini

exec: move include files to include/exec/

Signed-off-by: Paolo Bonzini <>
8f885ef8 10/28/2012 03:54 pm Aurelien Jarno

target-ppc: rename helper flags

Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Cc: Alexander Graf <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
2a7a47fc 06/24/2012 02:04 am Alexander Graf

PPC: BookE: Implement EPR SPR

On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.

Signed-off-by: Alexander Graf <>
d0f1562d 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for timebase helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
d523dd00 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for misc helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
2f5a189c 06/24/2012 02:04 am Blue Swirl

ppc: Move load and store helpers, switch to AREG0 free mode

Add an explicit CPUPPCState parameter instead of relying on AREG0
and rename op_helper.c (which only contains load and store helpers)
to mem_helper.c. Remove AREG0 swapping in
tlb_fill().

Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation...
c6c7cf05 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for MMU etc. helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
8e703949 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for FPU and SPE helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
d15f74fb 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for integer and vector helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>...
e5f17ac6 06/24/2012 02:04 am Blue Swirl

ppc: Avoid AREG0 for exception helpers

Add an explicit CPUPPCState parameter instead of relying on AREG0.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
9e0b5cb1 02/02/2012 03:47 am Alexander Graf

PPC: E500: Implement msgclr

This patch implements the msgclr instruction. It is part of the
Embedded.Processor Control specification and clears pending doorbell
interrupts on the current CPU.

Signed-off-by: Alexander Graf <>
d5d11a39 02/02/2012 03:47 am Alexander Graf

PPC: E500: Implement msgsnd

This patch implements the msgsnd instruction. It is part of the
Embedded.Processor Control specification and allows one CPU to
IPI another CPU without going through an interrupt controller.

Signed-off-by: Alexander Graf <>
6d3db821 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Implement tlbilx

The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used
to flush TLB entries. It's the recommended way of flushing in virtualized
environments.

So far we got away without implementing it, but Linux for e500mc uses this...
2c0d18dd 06/03/2011 05:07 pm Aurelien Jarno

target-ppc: remove old CONFIG_SOFTFLOAT #ifdef

target-ppc has been switched to softfloat only long ago, but a
few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.

Cc: Alexander Graf <>
Reviewed-by: Peter Maydell <>...
01662f3e 05/12/2011 01:24 am Alexander Graf

PPC: Implement e500 (FSL) MMU

Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.

Signed-off-by: Alexander Graf <>
81762d6d 04/01/2011 07:34 pm David Gibson

Clean up PowerPC SLB handling code

Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'. While the layout in these fields does match the
description of the SLB in the architecture document, it is not...
efdef95f 04/01/2011 07:34 pm David Gibson

Implement PowerPC slbmfee and slbmfev instructions

For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions...
3a7f009a 04/01/2011 07:34 pm David Gibson

Implement missing parts of the logic for the POWER PURR

The PURR (Processor Utilization Resource Register) is a register found
on recent POWER CPUs. The guts of implementing it at least enough to
get by are already present in qemu, however some of the helper...
eaabeef2 04/01/2011 07:34 pm David Gibson

Correct ppc popcntb logic, implement popcntw and popcntd

qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results...
0bffbc6c 07/13/2010 07:18 pm Aurelien Jarno

target-ppc: add vexptefp instruction

Signed-off-by: Aurelien Jarno <>
2bece2c8 06/16/2010 12:29 pm Richard Henderson

tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.

Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments. Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be...
95ff895f 02/06/2010 06:14 pm Aurelien Jarno

target-ppc: change DCR helpers to target_long arguments

The recent transition to always have the DCR helper functions take 32 bit
values broke the PPC64 target, as target_long became 64 bits there.

This patch changes DCR helpers to target_long arguments, and cast the values...
73b01960 12/21/2009 05:03 pm Alexander Graf

PPC: Make DCR uint32_t

For what I know DCR is always 32 bits wide, so we should also use uint32_t to
pass it along the stacks.

This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making
it compile without --disable-werror

Signed-off-by: Alexander Graf <>...
c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...
99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>
69a218fc 04/16/2009 03:57 pm aurel32

target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PURE

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
651721b2 03/09/2009 08:50 pm aurel32

targe-ppc: optimize mfcr and mtcrf

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
071fc3b1 02/09/2009 06:49 pm aurel32

target-ppc: Add vrsqrtefp instruction

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
bdfbac35 02/09/2009 06:49 pm aurel32

target-ppc: Add vrefp instruction

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
875b31db 02/09/2009 06:49 pm aurel32

target-ppc: Add vct{u,s}xs instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
819ca121 02/09/2009 06:49 pm aurel32

target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
35cf7c7e 02/09/2009 06:48 pm aurel32

target-ppc: Add vmaddfp and vnmsubfp instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
56fdd213 02/09/2009 06:48 pm aurel32

target-ppc: Add v{add,sub}fp instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
1536ff64 02/09/2009 06:48 pm aurel32

target-ppc: Add v{max,min}fp instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
b580763f 02/06/2009 12:33 am aurel32

target-ppc: change instruction name vrlogefp into vlogefp

Thanks to Nathan Froyd for noticing that.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
f586ce09 02/05/2009 03:42 pm aurel32

target-ppc: add vrlogefp instruction

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
e140632e 02/04/2009 03:52 pm aurel32

Add vcf{u,s}x instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
f6b19645 02/04/2009 03:52 pm aurel32

Add vrfi{m,n,p,z} instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
6e87b7c7 02/03/2009 09:56 pm aurel32

Make mtvscr use a helper

Do this so we can set float statuses once per mtvscr, rather than once
per Altivec instruction.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
5ab09f33 01/09/2009 01:19 am aurel32

Add v{add, sub}{s, u}{b, h, w}s instructions

Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
c026766b 01/08/2009 08:54 pm aurel32

Add vspltis{b,h,w} instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
d9430add 01/08/2009 08:54 pm aurel32

Add vs{l,r} instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
1add6e23 01/08/2009 08:54 pm aurel32

Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
8142cddd 01/05/2009 12:13 am aurel32

Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
cbfb6ae9 01/05/2009 12:13 am aurel32

Add {l,st}ve{b,h,w}x instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
bcd2ee23 01/05/2009 12:13 am aurel32

Add vmladduhm instruction.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
eae07261 01/05/2009 12:12 am aurel32

Add vmsumsh{m,s} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6186 c046a42c-6fe2-441c-8c8c-71466251a162
4d9903b6 01/05/2009 12:12 am aurel32

Add vmsumuh{m,s} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6185 c046a42c-6fe2-441c-8c8c-71466251a162
b161ae27 01/05/2009 12:12 am aurel32

Add vmh{,r}addshs instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6184 c046a42c-6fe2-441c-8c8c-71466251a162
1dd9ffb9 01/05/2009 12:12 am aurel32

Add vpkpx instruction.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6183 c046a42c-6fe2-441c-8c8c-71466251a162
5335a145 01/05/2009 12:12 am aurel32

Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6182 c046a42c-6fe2-441c-8c8c-71466251a162
d1258698 01/05/2009 12:11 am aurel32

Add vsel and vperm instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
b04ae981 01/05/2009 12:11 am aurel32

Add vmsum{u,m}bm instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
6cf1c6e5 01/05/2009 12:11 am aurel32

Add vupk{h,l}s{b,h} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
79f85c3a 01/05/2009 12:11 am aurel32

Add vupk{h,l}px instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
e4e6bee7 01/05/2009 12:10 am aurel32

Add vsplt{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
cd633b10 01/05/2009 12:10 am aurel32

Add vsldoi instruction.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
5e1d0985 01/05/2009 12:09 am aurel32

Add vrl{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
bf8d8ded 01/05/2009 12:09 am aurel32

Add lvs{l,r} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
e343da72 01/05/2009 12:09 am aurel32

Add v{add,sub}cuw instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6168 c046a42c-6fe2-441c-8c8c-71466251a162
7b239bec 01/05/2009 12:09 am aurel32

Add vs{l,r}o instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6167 c046a42c-6fe2-441c-8c8c-71466251a162
d79f0809 01/05/2009 12:09 am aurel32

Add vsl{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6166 c046a42c-6fe2-441c-8c8c-71466251a162
07ef34c3 01/05/2009 12:08 am aurel32

Add vsr{,a}{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6165 c046a42c-6fe2-441c-8c8c-71466251a162
2c277908 01/05/2009 12:08 am aurel32

Add vmul{e,o}{s,u}{b,h} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
3b430048 01/05/2009 12:08 am aurel32

Add vmrg{l,h}{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
e4039339 01/03/2009 03:31 pm aurel32

Add v{min, max}{s, u}{b, h, w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6157 c046a42c-6fe2-441c-8c8c-71466251a162
fab3cbe9 01/03/2009 03:31 pm aurel32

Add vavg{s,u}{b,h,w} instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6156 c046a42c-6fe2-441c-8c8c-71466251a162
7872c51c 01/03/2009 03:31 pm aurel32

Add v{add,sub}u{b,h,w}m instructions.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6155 c046a42c-6fe2-441c-8c8c-71466251a162
9a819377 12/14/2008 09:34 pm aurel32

target-ppc: fix fcmp{o,u} instructions

The instructions are specified to update the condition register even if
an error is to be signaled because of NaN input.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>...
6e35d524 12/14/2008 08:40 pm aurel32

target-ppc: fix mtfsb0 and mtfsb1

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6032 c046a42c-6fe2-441c-8c8c-71466251a162
e06fcd75 12/12/2008 12:42 am aurel32

target-ppc: rework exception code

... also remove two warnings.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
45d827d2 12/07/2008 03:40 pm aurel32

target-ppc: convert SPR accesses to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
74d37793 12/06/2008 11:46 pm aurel32

target-ppc: convert SLB/TLB instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
06dca6a7 12/06/2008 06:37 pm aurel32

target-ppc: convert dcr load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
6527f6ea 12/06/2008 03:03 pm aurel32

target-ppc: convert msr load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
22e0e173 12/06/2008 02:19 pm aurel32

target-ppc: convert POWER bridge instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
ef0d51af 11/30/2008 07:26 pm aurel32

target-ppc: convert PPC 440 instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
d72a19f7 11/30/2008 06:24 pm aurel32

target-ppc: convert return from interrupt instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
bdb4b689 11/30/2008 06:24 pm aurel32

target-ppc: convert lscbx instruction to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
dfbc799d 11/30/2008 06:24 pm aurel32

target-ppc: convert load/store string instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
37d269df 11/30/2008 06:24 pm aurel32

target-ppc: convert icbi instruction to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
799a8c8d 11/30/2008 06:24 pm aurel32

target-ppc: convert dcbz instruction to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
ff4a62cd 11/30/2008 06:23 pm aurel32

target-ppc: convert load/store multiple instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162
cf02a65c 11/30/2008 06:23 pm aurel32

target-ppc: convert mfrom instruction to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5823 c046a42c-6fe2-441c-8c8c-71466251a162
0f3955e2 11/30/2008 06:22 pm aurel32

target-ppc: convert software TLB instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5819 c046a42c-6fe2-441c-8c8c-71466251a162
cab3bee2 11/24/2008 01:28 pm aurel32

target-ppc: convert trap instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
a0d7d5a7 11/23/2008 06:30 pm aurel32

target-ppc: convert FPU load/store to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5786 c046a42c-6fe2-441c-8c8c-71466251a162
1c97856d 11/23/2008 12:54 pm aurel32

target-ppc: convert SPE FP ops to TCG

Including a few bug fixes:
- Don't clear high part for instruction with 32-bit destination
- Fix efscmp* and etstcmp* return value

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5783 c046a42c-6fe2-441c-8c8c-71466251a162
64adab3f 11/22/2008 12:09 pm aurel32

target-ppc: convert exceptions generation to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
af12906f 11/19/2008 06:10 pm aurel32

target-ppc: convert fp ops to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
57951c27 11/10/2008 01:10 pm aurel32

target-ppc: convert most SPE integer instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
74637406 11/01/2008 02:54 am aurel32

target-ppc: convert arithmetic functions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
26d67362 10/21/2008 02:31 pm aurel32

target-ppc: convert logical instructions to TCG

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162