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# Date Author Comment
97836cee 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement relocatable vectors

See ISA, 4.4.3 for details.

Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ccfcaba6 09/10/2011 07:57 pm Max Filippov

target-xtensa: add gdb support

Specific xtensa processor overlay for GDB contains register map in
the gdb/xtensa-config.c. This description is used by the GDB to e.g.
parse 'g' response packets and it may be reused in the qemu's gdbstub
(only XTREG definitions for non-pseudoregisters are needed)....
b67ea0cd 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement memory protection options

- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).

Cache control attribute bits are not used by this implementation.

Signed-off-by: Max Filippov <>...
4dd85b6b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement boolean option

See ISA, 4.3.9

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
553e44f9 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement windowed registers

See ISA, 4.7.1 for details.

Physical registers and currently visible window are separate fields in
CPUEnv. Only current window is accessible to TCG. On operations that
change window base helpers copy current window to and from physical...
797d780b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement loop option

See ISA, 4.3.2 for details.

Operations that change LEND SR value invalidate TBs at the old and at
the new LEND. LEND value at TB compilation time is considered constant
and loop instruction is generated based on this value....
6ad6dbf7 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement extended L32R

See ISA, 4.3.3 for details.

TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
b994e91b 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement interrupt option

See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
f3df4c04 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement CPENABLE and PRID SRs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
3580ecad 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement shifts (ST1 and RST1 groups)

- ST1: SAR (shift amount special register) manipulation, NSA;
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
809377aa 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement LSAI group

- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
f0a548b9 09/10/2011 07:57 pm Max Filippov

target-xtensa: add PS register and access control

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
40643d7c 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement exceptions

- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
2af3da91 09/10/2011 07:57 pm Max Filippov

target-xtensa: add special and user registers

Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.

User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details....
2328826b 09/10/2011 07:57 pm Max Filippov

target-xtensa: add target stubs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
dedc5eae 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement disas_xtensa_insn

Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <>...