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target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement boolean option
See ISA, 4.3.9
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement loop option
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and atthe new LEND. LEND value at TB compilation time is considered constantand loop instruction is generated based on this value....
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generatedin case this option is not enabled.
target-xtensa: implement SIMCALL
Tensilica iss provides support for applications running in freestandingenvironment through SIMCALL command. It is used by Tensilica libc toaccess argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses....
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement accurate window check
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used registerwatermark" beyond its current level. Used register watermark is reset oninstructions that change WINDOW_BASE/WINDOW_START SRs....
target-xtensa: implement CPENABLE and PRID SRs
target-xtensa: implement RST3 group
- access to Special Registers (wsr, rsr);- access to User Registers (wur, rur);- misc. operations option (value clamp, sign extension, min, max);- conditional moves.
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;- cache operations (not implemented);- multiprocessor synchronization operations.
target-xtensa: mark reserved and TBD opcodes
Reserved opcodes must generate illegal instruction exception. Usuallythey signal emulation quality problems.Not implemented opcodes are good to see.
target-xtensa: implement SYNC group
All operations in this group are no-ops, because there are no delayedside effects.
target-xtensa: implement CACHE group
All operations in this group are no-ops, because cache ought to betransparent to applications. However cache may be abused, then we'llneed to actually implement these opcodes.
target-xtensa: add PS register and access control
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: implement RST2 group (32 bit mul/div/rem)
target-xtensa: implement conditional jumps
- BZ (comparison to zero);- BI0 (comparison to signed immediate);- BI1 (comparison to unsigned immediate);- B (two registers comparison, bit sets comparison);- BEQZ.N/BNEZ.N (narrow comparison to zero).
target-xtensa: implement JX/RET0/CALLX
Group SNM0 (indirect jumps and calls).
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processorby the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in somecases of options that Tensilica provides. See ISA, 5.4 for details....
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
target-xtensa: implement narrow instructions
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
target-xtensa: implement RT0 group
NEG and ABS are the only members of RT0 group.