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target-i386: QOM'ify CPU
Embed CPUX86State as first member of X86CPU.Distinguish between "x86_64-cpu" and "i386-cpu".Drop cpu_x86_close() in favor of calling object_delete() directly.
For now let CPUClass::reset() call cpu_state_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: QOM'ify CPU init
Move code from cpu_x86_init() to new QOM x86_cpu_initfn().Also move mce_init() to cpu.c since it's used nowhere else.
target-i386: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM x86_cpu_reset(),fixing style issues for FPU init.
target-i386: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUX86State/g" target-i386/*.[hc] sed -i "s/#define CPUX86State/#define CPUState/" target-i386/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-i386: Mask NX bit from cpu_get_phys_page_debug result
This was a long pending bug, now revealed by the assert inphys_page_find that stumbled over the large page index returned bycpu_get_phys_page_debug for NX-marked pages: We need to mask out NX and...
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
target-i386: Clean includes
Remove some include statements which are not needed.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-i386: Add infrastructure for reporting TPR MMIO accesses
This will allow the APIC core to file a TPR access report. Depending onthe accelerator and kernel irqchip mode, it will either be deliveredright away or queued for later reporting.
In TCG mode, we can restart the triggering instruction and can therefore...
Fix X86 CPU topology in KVM mode
apic id returned to guest kernel in ebx for cpuid(function=1) depends onCPUX86State->cpuid_apic_id which gets populated after the cpuid informationis cached in the host kernel. This results in broken CPU topology in guest....
i386: wire up MSR_IA32_MISC_ENABLE
It's needed for its default value - bit 0 specifies that "rep movs" isgood enough for memcpy, and Linux may use a slower memcpu if it is not set,depending on cpu family/model.
Signed-off-by: Avi Kivity <avi@redhat.com>...
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
Avoid allocating TCG resources in non-TCG mode
Do not allocate TCG-only resources like the translation buffer whenrunning over KVM or XEN. Saves a "few" bytes in the qemu address spaceand is also conceptually cleaner.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix compilation warning due to missing header for sigaction (followup)
This patch removes all references to signal.h when qemu-common.h is includedas they become redundant.
Signed-off-by: Alexandre Raymond <cerbere@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-i386: remove old code handling float64
Now that target-i386 uses softfloat, floatx80 is always available andthere is no need anymore to have code handling both float64 and floax80.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: use CPU_LDoubleU instead of a private union
Use CPU_LDoubleU in cpu_dump_state() instead of redefining a union fordoing the conversion.
Based on a patch from Laurent Vivier <laurent@vivier.eu>.
Cc: Laurent Vivier <laurent@vivier.eu>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
x86: Properly reset PAT MSR
Conforming to the Intel spec, set the power-on value of PAT also onreset, but save it across INIT.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: x86: Consolidate TCG and KVM MCE injection code
This switches KVM's MCE injection path to cpu_x86_inject_mce, both forSIGBUS and monitor initiated events. This means we prepare the MCA MSRsin the VCPUState also for KVM.
We have to drop the MSRs writeback restrictions for this purpose which...
x86: Perform implicit mcg_status reset
Reorder mcg_status in CPUState to achieve automatic clearing on reset.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>CC: Jin Dongming <jin.dongming@np.css.fujitsu.com>...
x86: Small cleanups of MCE helpers
Fix some code style issues, use proper headers, and align to cpu_x86naming scheme. No functional changes.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Huang Ying <ying.huang@intel.com>CC: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>...
x86: Refine error reporting of MCE injection services
As this service is used by the human monitor, make sure that errors getreported to the right channel, and also raise the verbosity.
This requires to move Monitor typedef in qemu-common.h to resolve the...
x86: Optionally avoid injecting AO MCEs while others are pending
Allow to tell cpu_x86_inject_mce that it should ignore Action OptionalMCE events when the target VCPU is still processing another one. Thiswill be used by KVM soon.
x86: Run qemu_inject_x86_mce on target VCPU
We will use the current TCG-only MCE injection path for KVM as well, andthen this read-modify-write of the target VCPU state has to be performedsynchronously in the corresponding thread.
x86: Fix MCA broadcast parameters for TCG case
When broadcasting MCEs, we need to set MCIP and RIPV in mcg_status likeit is done for KVM. Use the symbolic constants at this chance.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>...
x86: Optionally dump code bytes on cpu_dump_state
Introduce the cpu_dump_state flag CPU_DUMP_CODE and implement it forx86. This writes out the code bytes around the current instructionpointer. Make use of this feature in KVM to help debugging fatal vmexits....
Clean up cpu_inject_x86_mce()
Clean up cpu_inject_x86_mce() for later patch.
Signed-off-by: Jin Dongming <jin.dongming@np.css.fujitsu.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Add "broadcast" option for mce command
When the following test case is injected with mce command, maybe user could notget the expected result. DATA command cpu bank status mcg_status addr misc (qemu) mce 1 1 0xbd00000000000000 0x05 0x1234 0x8c...
Add function for checking mca broadcast of CPU
Add function for checking whether current CPU support mca broadcast.
x86: Filter out garbage from segment flags dump
Only bits 8..23 of the segment flags contain valid data, so only dumpthose when printing the CPU state.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
kvm: x86: add mce support
Port qemu-kvm's MCE support
commit c68b2374c9048812f488e00ffb95db66c0bc07a7Author: Huang Ying <ying.huang@intel.com>Date: Mon Jul 20 10:00:53 2009 +0800
Add MCE simulation support to qemu/kvm
KVM ioctls are used to initialize MCE simulation and inject MCE. The...
MCE: Relay UCR MCE to guest
Port qemu-kvm's
commit 4b62fff1101a7ad77553147717a8bd3bf79df7efAuthor: Huang Ying <ying.huang@intel.com>Date: Mon Sep 21 10:43:25 2009 +0800
UCR (uncorrected recovery) MCE is supported in recent Intel CPUs,...
x86: Fix INIT processing
This fixes a regression of 0e26b7b892: Reset halted also on INIT.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
apic: avoid passing CPUState from CPU code
Pass only APICState when accessing APIC from CPU code.
target-i386: print EFER in cpu_dump_state
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Avi Kivity <avi@redhat.com>
target-i386: Fix compiler warning
With argument checking for cpu_fprintf, gcc throws this warning:
CC i386-softmmu/helper.occ1: warnings being treated as errors/qemu/ar7/target-i386/helper.c: In function ‘cpu_x86_dump_seg_cache’:/qemu/ar7/target-i386/helper.c:220: error: format not a string literal and no format arguments...
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
x86/cpuid: move CPUID functions into separate file
about half of target-i386/helper.c consist of CPUID related functions.Only one of them is a real TCG helper function. So move the wholeCPUID stuff out of this into a separate file to get bettermaintainable parts....
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Signed-off-by: Paul Brook <paul@codesourcery.com>
target-i386: fix crash on x86 32bit linux host with hw breakpoint exceptions
If you make use of hw breakpoints on a 32bit x86 linux host, qemuwill segmentation fault when processing the exception.
The problem is that the value of env is stored in $ebp in the op_helper...
Fix OpenBSD linker warning
helper.o(.text+0x11e0): In function `listflags':/src/qemu/target-i386/helper.c:661: warning: sprintf() is often misused, please use snprintf()
Fix i386-bsd-user build
Add cpu model configuration support..
This is a reimplementation of prior versions which addsthe ability to define cpu models for contemporary processors.The added models are likewise selected via -cpu <name>,and are intended to displace the existing convention...
Add KVM paravirt cpuid leaf
Initialize KVM paravirt cpuid leaf and allow user to control guestvisible PV features through -cpu flag.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
MCE: Fix bug of IA32_MCG_STATUS after system reset
Now, if we inject a fatal MCE into guest OS, for example Linux, Linuxwill go panic and then reboot. But if we inject another MCE now,system will reset directly instead of go panic firstly, becauseMCG_STATUS.MCIP is set to 1 and not cleared after reboot. This is does...
Intel CPUs starting from pentium have apic
Intel CPUs starting from pentium have apic. Lets advertise it.
Signed-off-by: Gleb Natapov <gleb@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: Update CPUID feature set for TCG
The CPUID features QEMU presented to the guest were not up-to-datewith QEMU's emulated feature set.Add the missing bits of recent (and not so recent) additions toQEMU's emulation engine.For stability reasons only the user mode usable bits are exposed for...
cpuid: Fix multicore setup on Intel
The multicore CPUID code detects whether the guest is an Intel or anAMD CPU, because the Linux kernel is picky about the CmpLegacy bit.KVM by default passes through the host's vendor, which was notcatched by the code. So fork out the vendor determining bits into a...
user: move CPU reset call to main.c for x86/PPC/Sparc
v3: don't call reset functions on cpu initialization
There is absolutely no need to call reset functions when initializingdevices. Since we are already registering them, calling qemu_system_reset()should suffice. Actually, it is what happens when we reboot the machine,...
x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change
CC: Huang Ying <ying.huang@intel.com>Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactlywhat we need (namely, sign extend to 64 bits when used with 64bit addresess.
Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax....
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
i386: Drop redundant kvm_enabled test
cpu_synchronize_state already does this.
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
kvm_arch_get_registers() shouldn't be called directly
Direct call to kvm_arch_get_registers() bypass logic incpu_synchronize_state()
push CPUID level to 4 to allow Intel multicore decoding
Intel CPUs store the number of cores in CPUID leaf 4. So pushthe maxleaf value to 4 to allow the guests access to this leaf.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
set CPUID bits to present cores and threads topology
Controlled by the enhanced -smp option set the CPUID bits to present theguest the desired topology. This is vendor specific, but (with the exceptionof the CMP_LEGACY bit) not conflicting, so we set all bits everytime....
allow overriding of CPUID level on command line
The CPUID level determines how many CPUID leafs are exposed to the guest.Some features (like multi-core) cannot be propagated without the properlevel, but guests maybe confused by bogus entries in some leafs....
introduce kvm64 CPU
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type,which is the least common denominator of all KVM-capable x86-CPUs(based on Intel Pentium 4 Prescott). It can be used as a base typefor migration.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>...
Unbreak large mem support by removing kqemu
kqemu introduces a number of restrictions on the i386 target. The worst is thatit prevents large memory from working in the default build.
Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on...
Only allow -cpu host when KVM is enabled
-cpu host is not at all useful when using tcg.
Initialize cpuid variables
This causes a build break when !KVM.
omit 3DNOW! CPUID bits from qemu64 CPU model
Since we recently do not disable 3DNOW! support anymore, we shouldavoid setting the bits in the default qemu64 CPU model to easemigration. TCG does not support it anyway and even AMD deprecatesit's usage nowadays....
Update to a hopefully more future proof FSF address
gdbstub: x86: Support for setting segment registers
This allows to set segment registers via gdb also in system emulationmode. Basic sanity checks are applied and nothing is changed if theyfail. But screwing up the target via this interface will never be...
QEMU: MCE: Add MCE simulation to qemu/tcg
- MCE features are initialized when VCPU is intialized according to CPUID.- A monitor command "mce" is added to inject a MCE.- A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
aliguori: fix build for linux-user...
Suppress a GCC warning
allow hypervisor CPUID bit to be overriden
KVM defaults to the hypervisor CPUID bit to be set, whereas pureQEMU clears it. On some occasions one wants to set or clear it theother way round (for instance to get HyperV running inside a guest).
Move the bit-set to be done before the command line parsing and...
introduce -cpu host target
Although the guest's CPUID bits can be controlled in a fine grained wayin QEMU, a simple way to inject the host CPU is missing. This is handyfor KVM desktop virtualization, where one wants the guest to support thefull host feature set....
CPUID Fn8000_0001.EAX is family/model/stepping, not features
fix KVMs GET_SUPPORTED_CPUID feature usage
If we want to trim the user provided CPUID bits for KVM to be not greaterthan that of the host, we should not remove the bits after we sentthem to the kernel.This fixes the masking of features that are not present on the host by...
remove CPUID host hacks
KVM provides an in-kernel feature to disable CPUID bits that are notpresent in the current host. So there is no need here to duplicate thiswork. Additionally allows 3DNow! on capable processors, since therestriction seems to apply to QEMU/TCG only....
Handle init/sipi in a main cpu exec loop. (v2)
This should fix compilation problem in case of CONFIG_USER_ONLY.
Currently INIT/SIPI is handled in the context of CPU that sends IPI.This patch changes this to handle them like all other events in a maincpu exec loop. When KVM will gain thread per vcpu capability it will...
allow CPUID vendor override
KVM-enabled QEMU will always report the vendor ID of the physical CPU it isrunning on. Allow to override this if explicitly requested on thecommand line. It will not suffice to name a CPU type (like -cpu phenom),but you have to explicitly set the vendor: -cpu phenom,vendor=AuthenticAMD...
QEMU KVM: i386: Fix the cpu reset state
As per the IA32 processor manual, the accessed bit is set to 1 in theprocessor state after reset. qemu pc cpu_reset code was missing thisaccessed bit setting.
Signed-off-by: Nitin A Kamble <nitin.a.kamble@intel.com>...
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Remove noisy printf when KVM masks CPU features
Make x86 cpuid feature names available in file scope
To be used later.
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Fix x86 feature modifications for features that set multiple bits
QEMU allows adding or removing cpu features by using the syntax '-cpu +feature'or '-cpu -feature'. Some cpuid features cause more than one bit to be set orcleared; but QEMU stops after just one bit has been modified, causing the...
kvm: Trim cpu features not supported by kvm
Remove cpu features that are not supported by kvm from the cpuid featuresreported to the guest.
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
kqemu: merge CONFIG_KQEMU and USE_KQEMU
Basically a recursive ":%s/USE_KQEMU/CONFIG_KQEMU/g".
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7189 c046a42c-6fe2-441c-8c8c-71466251a162
x86: Enhanced dump of segment registers (Jan Kiszka)
Parse the descriptor flags that segment registers refer to and show theresult in a more human-friendly format. The output of info registers eg.then looks like this:
[...]ES =007b 00000000 ffffffff 00cff300 DPL=3 DS [-WA]...
Fix cpuid KVM crash on i386 (Lubomir Rintel)
Cpuid should return into vec, not overwrite past address in count.Changeset 6565 broke this.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6689 c046a42c-6fe2-441c-8c8c-71466251a162
Fix "info registers" under kvm.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6684 c046a42c-6fe2-441c-8c8c-71466251a162
KVM: CPUID takes ecx as input value for some functions (Amit Shah)
The CPUID instruction takes the value of ECX as an input parameterin addition to the value of EAX as the count for functions 4, 0xband 0xd. Make sure we pass the value to the instruction....
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Add phenom CPU descriptor (Alexander Graf)
As part of my ongoing effort to make nested SVM useful, I started working to getVMware ESX run inside KVM.
VMware couples itself pretty tightly to the CPUID, so it's a good idea to emulatea machine that officially supports SVM and should thus exploit the powers of...
Fix a typo in ext2_feature_name (Carl-Daniel Hailfinger)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6474 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
x86 cleanup
Remove some unnecessary includes, add needed includes, move prototypes tocpu.h to suppress missing prototype warnings.
Remove unused functions and prototypes (cpu_x86_flush_tlb, cpu_lock,cpu_unlock, restore_native_fp_state, save_native_fp_state)....
Fix register name typo in dumping debug registers (Jan Kiszka)
Signed-off-by: Jan Kiszka <jan.kiszka@web.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5855 c046a42c-6fe2-441c-8c8c-71466251a162
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.