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root / target-arm @ 9168b3a5

Name Size
cpu.h 14.5 kB
exec.h 1.5 kB
helper.c 72 kB
helpers.h 15.9 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.6 kB
neon_helper.c 34.4 kB
op_addsub.h 1.8 kB
op_helper.c 10.7 kB
translate.c 312.2 kB

Latest revisions

# Date Author Comment
e03c22a9 05/31/2010 08:40 pm Lars Munch

arm: fix arm kernel boot for non zero start addr

Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu...
9ba8c3f4 05/28/2010 10:25 pm Lars Munch

arm: prevent coprocessor IO reset

This prevent coprocessor IO structure from being reset on cpu reset. This was
a problem for PXA which uses coprocessor 6 and 14.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>
22ed1d34 04/25/2010 10:31 pm Blue Swirl

arm: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>
8e31209e 04/08/2010 10:12 pm Juha Riihimäki

target-arm: fix neon vmon/vmvn with modified immediate

Signed-Off-By: Riku Voipio <>
Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>
d9968827 04/08/2010 12:11 pm Lars Munch

target-arm: resource leak fixes for iwmmxt disassemble

This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>
4f78c9ad 04/05/2010 09:56 pm Paul Brook

Fix arm-linux-user

Only include hw/loader.h from target-arm/helper.c when building for
system emulation.

Signed-off-by: Paul Brook <>
983fe826 04/05/2010 09:43 pm Paul Brook

ARMv7-M reset fixes

Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board
reset routine to call this. Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <>
3ad493fc 03/27/2010 03:14 pm Rabin Vincent

target-arm: disable PAGE_EXEC for XN pages

Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection
checking if the page is already in the TLB.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Aurelien Jarno <>
bedd2912 03/23/2010 11:10 pm Johan Bengtsson

target-arm: Fix handling of AL condition in IT instruction

Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>
d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...

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