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root / target-xtensa @ 93148aa5

Name Size
  core-dc232b
  core-fsf
core-dc232b.c 565 Bytes
core-fsf.c 464 Bytes
cpu.h 12.7 kB
helper.c 19.3 kB
helpers.h 1.2 kB
machine.c 1.7 kB
op_helper.c 21.2 kB
overlay_tool.h 16.8 kB
translate.c 83.3 kB

Latest revisions

# Date Author Comment
5a30d3f1 03/03/2012 07:59 pm Blue Swirl

Merge branch 'upstream' of git://qemu.weilnetz.de/qemu

  • 'upstream' of git://qemu.weilnetz.de/qemu:
    Move definition of HOST_LONG_BITS to qemu-common.h
    target-xtensa: Clean includes
    target-unicore32: Clean includes
    target-sh4: Clean includes
    target-s390x: Clean includes...
2ad5201c 02/28/2012 11:33 pm Stefan Weil

target-xtensa: Clean includes

Remove some include statements which are not needed.

Acked-by: Max Filippov <>
Signed-off-by: Stefan Weil <>
f14c4b5f 02/20/2012 06:07 pm Max Filippov

target-xtensa: add DBREAK data breakpoints

Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debug
watchpoints.

This implementation is not fully compliant to ISA: when a breakpoint is
set to an unmapped/inaccessible memory address it generates TLB/memory...
18da9326 02/20/2012 06:07 pm Max Filippov

target-xtensa: add DEBUG_SECTION to overlay tool

Fill debug configuration from overlay definitions in the DEBUG_SECTION.
Add DEBUG_SECTION to DC232B and FSF cores.

Signed-off-by: Max Filippov <>
35b5c044 02/18/2012 12:55 pm Max Filippov

target-xtensa: add ICOUNT SR and debug exception

ICOUNT SR gets incremented on every instruction completion provided that
CINTLEVEL at the beginning of the instruction execution is lower than
ICOUNTLEVEL.

When ICOUNT would increment to 0 a debug exception is raised if...
ab58c5b4 02/18/2012 12:55 pm Max Filippov

target-xtensa: add DEBUGCAUSE SR and configuration

DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.

Signed-off-by: Max Filippov <>
e61dc8f7 02/18/2012 12:55 pm Max Filippov

target-xtensa: implement instruction breakpoints

Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and
BREAK.N instructions and IBREAK breakpoints.

IBREAK breakpoint address is considered constant for TB lifetime.
On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
692f737c 02/17/2012 11:25 pm Max Filippov

target-xtensa: implement info tlb monitor command

Command dumps valid ITLB and DTLB entries.

Signed-off-by: Max Filippov <>
a044ec2a 02/17/2012 11:25 pm Max Filippov

target-xtensa: fetch 3rd opcode byte only when needed

According to ISA, 3.5.4, third opcode byte should not be fetched for
2-byte instructions.

Signed-off-by: Max Filippov <>
b96ac3e4 02/17/2012 11:25 pm Max Filippov

target-xtensa: define TLB_TEMPLATE for MMU-less cores

TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.

Signed-off-by: Max Filippov <>

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