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root / target-mips @ 9a78eead

Name Size
TODO 1.9 kB
cpu.h 18.8 kB
exec.h 2.6 kB
helper.c 22.1 kB
helper.h 8.5 kB
machine.c 10.6 kB
mips-defs.h 2.1 kB
op_helper.c 95.9 kB
translate.c 360.9 kB
translate_init.c 22.3 kB

Latest revisions

# Date Author Comment
9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

2abf314d 10/13/2010 09:43 pm Blue Swirl

mips: avoid write only variables

Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
/src/qemu/target-mips/translate.c: In function 'gen_ld':
/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]...

1c7242da 09/18/2010 08:53 am Blue Swirl

MIPS: fix yield handling

The parameter for yield should be handled as a signed integer
for the comparisons to have any effect.

This also avoids a gcc warning with -Wtype-limits.

Signed-off-by: Blue Swirl <>

138afb02 08/06/2010 01:21 pm Edgar E. Iglesias

mips: Add support for VInt and VEIC irq modes

Signed-off-by: Edgar E. Iglesias <>

671b0f36 07/31/2010 06:14 pm Hervé Poussineau

Correctly identify multiple cpus in SMP systems

Signed-off-by: Hervé Poussineau <>
Signed-off-by: Aurelien Jarno <>

cf7c00d5 07/31/2010 06:14 pm Hervé Poussineau

Remove unused constant

Remove unused constant MIPS_FCR0

Signed-off-by: Hervé Poussineau <>
Signed-off-by: Aurelien Jarno <>

5dc5d9f0 07/25/2010 05:54 pm Aurelien Jarno

mips: more fixes to the MIPS interrupt glue logic

Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.

Signed-off-by: Aurelien Jarno <>...

36388314 07/24/2010 02:40 pm Edgar E. Iglesias

mips: Correct MIPS interrupt glue logic for icount

When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue...

3fc00a7b 07/17/2010 05:13 pm Aurelien Jarno

target-mips: fix xtlb exception for loongson

Loongson 2E and 2F use the same entry for xtlb and tlb exception, at
offset 0x000.

Signed-off-by: Aurelien Jarno <>

161f85e6 07/11/2010 11:24 am Aurelien Jarno

target-mips: add loongson 2E & 2F integer instructions

This patch adds support for loongson 2E & 2F instructions. They are the
same instructions, but differ by the opcode encoding.

Signed-off-by: Aurelien Jarno <>

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