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Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
arm_gic: Rename gic_state to GICState
Rename the gic_state struct to match QEMU's coding style conventionsfor structure names, since the impending KVM-for-ARM patches willcreate another subclass of it. This patch was created using: sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \...
hw/arm_gic.c: Fix improper DPRINTF output.
s->cpu_enabled is an array, so s->cpu_enabled ? "En" : "Dis" returns"En" always. We should use s->cpu_enabled[cpu] here.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic.c: Define .class_size in arm_gic_info TypeInfo
Add the missing .class_size definition to the arm_gic_info TypeInfo.This fixes the memory corruption and possible segfault that otherwiseresults when the class struct is allocated at too small a size and...
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
arm_gic: Send dbg msgs to stderr not stdout
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
hw/arm_gic: Remove NVIC ifdefs from gic_state struct
Remove some NVIC ifdefs from the gic_state struct and itsstate save/load functions. This means there are some fieldsin it which are present for the NVIC but not used, but meansit always has the same layout and can be pulled out into a...
hw/arm_gic: Remove the special casing of NCPU for the NVIC
Drop the special casing of NCPU=1 for the NVIC. This slightlyincreases the amount of memory used by its state structure,but removes some ifdeffery and means we can safely move theGIC state into a common subclass structure....
hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset
Move the NVIC specific bits of reset to the NVIC's ownreset function, rather than using ifdefs in the commonarm_gic reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers
Implement the NVIC specific register areas using a set ofoverlaid MemoryRegions in a container, rather than by havingthe arm_gic read/write functions use special purpose callbacks.
hw/arm_gic: Add qdev property for GIC revision
GIC behaviour can be different between revision 1 and2 of the architectural GIC specification; we also haveto handle the legacy 11MPCore GIC, which is differentagain in some places. Introduce a qdev property so we...
hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor
The GIC spec says that the CPU target registers should RAZ/WIfor uniprocessor implementations. Implement this, which alsoconveniently lets us drop an NVIC ifdef.
Annoyingly, the 11MPCore's GIC is the odd one out, since...
hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting
Make the minor tweaks to interrupt numbering used by the NVICa runtime setting rather than a compile time one, so we candrop more NVIC ifdefs.
hw/arm_gic: Move CPU interface memory region setup into arm_gic_init
Remove more NVIC ifdefs by moving the code to setup the CPU interfacememory regions into the GIC specific arm_gic_init() function ratherthan the gic_init() function. Rename the latter to more closely...
hw/armv7m_nvic: Make the NVIC a freestanding class
Rearrange the GIC and NVIC so both are straightforwardsubclasses of a common class, rather than having the NVICsource file textually include arm_gic.c.
hw/arm_gic: Make gic_reset a sysbus reset function
Make gic_reset a sysbus reset function, so we actuallyreset the GIC on system reset rather than only at init.For the NVIC this requires us also to implement resetof the SysTick.
hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define
Now all the A profile cores have been switched to use the standalonesysbus GIC, the only remaining code which #includes arm_gic.c isthe v7M NVIC. The coupling is much closer here so it's not so...
hw/arm_gic: gic_set_pending_private() is NVIC only
The function gic_set_pending_private() is now used by the NVIConly (for the GIC we now set PPI interrupts via gpio lines andgic_set_irq()). So make it #ifdef NVIC and remove the 'attributeunused' annotation....
hw/arm_gic: Remove stray hardcoded tab
Remove the single instance of a hardcoded tab from hw/arm_gic.c.
hw/arm_gic: Move NCPU definition to arm_gic.c
Move the NCPU definition to arm_gic.c: the maximum numberof CPU interfaces is defined by the GIC architecture specificationto be 8, so we don't need to have this #define in each of thesources files which currently includes arm_gic.c....
hw/arm_gic: Move gic_get_current_cpu into arm_gic.c
Move the gic_get_current_cpu() function into arm_gic.c.There are only two implementations: (1) "get the indexof the currently executing CPU", used by all multicoreGICs, and (2) "always 0", used by all GICs instantiated...
hw/arm_gic: Expose PPI inputs as gpio inputs
Expose the Private Peripheral Interrupt inputs as GPIO inputs.The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ...
Treating PPIs as being another kind of input line is in line with the...
hw/arm_gic: Make the GIC its own sysbus device
Compile arm_gic.c as a standalone C file to produce a self containedsysbus GIC device. Support the legacy usage by #include of the .c fileby making those users #define LEGACY_INCLUDED_GIC, so we can convert...
ARM: Remove unnecessary subpage workarounds
In the ARM per-CPU peripherals (GIC, private timers, SCU, etc),remove workarounds for subpage memory region read/write functionsbeing passed offsets from the start of the page rather than thestart of the region. Following commit 5312bd8b3 the masking off...
arm: clean up GIC constants
Interrupts numbers 0-31 are private to the processor interface, 32-1019 aregeneral interrupts. Add GIC_INTERNAL and substitute everywhere.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>[Peter Maydell: converted some tabs to spaces]...
arm: make sure that number of irqs can be represented in GICD_TYPER.
We currently assume that the number of interrupts (ITLinesNumber inthe architecture reference manual) is divisible by 32, since wepresent it to the guest when it reads GICD_TYPER (in gic_dist_readb())...
arm: make the number of GIC interrupts configurable
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020,and create a configurable property for each defaulting to 96 and 64(respectively) so that device modelers can set the value appropriately...
arm: add dummy gic security registers
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge remote-tracking branch 'stefanha/trivial-patches-next' into staging
hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regions
Expose the ARM GIC CPU interfaces as memory regions, rather thanjust providing read and write functions for them.
fix spelling in hw sub directory
Correct obvious spelling errors in qemu/hw directory.
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
hw/arm_gic.c: Ignore attempts to complete nonexistent IRQs
Ignore attempts to complete non-existent IRQs; this fixes a bufferoverrun if the guest writes a bad value to the GICC_EOIR register.(This case is UNPREDICTABLE so ignoring it is a valid choice.)...
arm_gic: handle banked enable bits for per-cpu interrupts
The first enable set/clear register (which controls the PPIs and SGIs)is supposed to be banked for each processor. Currently it is justhandled globally and this prevents recent SMP Linux kernels from...
hw/arm_gic.c: Fix save/load of irq_target array
irq_target array saving/loading is in the wrong loop.Version bump.
Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>Acked-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
arm_gic: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Correct spelling of licensed
Correct typos of "licenced" to "licensed".
Reviewed-by: Stefan Weil <weil@mail.berlios.de>Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-arm: Fix soft interrupt in GIC distributor
Fix selection of target list filter mode.
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. Thetarget endianness is not of their concern, so we need to push thingsdown a level.
This patch adds a parameter to cpu_register_io_memory that allows adevice to choose its endianness. For now, all devices simply choose...
savevm: Add DeviceState param
When available, we'd like to be able to access the DeviceStatewhen registering a savevm. For buses with a get_dev_path()function, this will allow us to create more unique savevmid strings.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>...
ARM PBX-A9 board support
Implement ARM RealView PBX-A9 board support.
Signed-off-by: Paul Brook <paul@codesourcery.com>
ARM MPCore tweaks
Allow the user to specify the number of cores present on theRealView EB + ARM11MPCore board. Also split into its own configrather than guessing from the CPU name.
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Make CPURead/WriteFunc structure 'const'
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove io_index argument from cpu_register_io_memory()
The parameter is always zero except when registering the three internalio regions (ROM, unassigned, notdirty). Remove the parameter to reducethe API's power, thus facilitating future change.
Signed-off-by: Avi Kivity <avi@redhat.com>...
Remove qdev irq sink handling
We have both IRQ sinks and GPIO inputs. These are in principle exactlythe same thing, so remove the former.
ARM GIC qdev conversion
Replace gcc variadic macro extension with C99 version
Replace cpu_abort with hw_error
arm: Fix gic_irq_state.level bitfield type
Found while cleaning up compiler warnings: GIC_*_LEVEL macros stronglysuggest that gic_irq_state.level is intended to be per-CPU and not justa single, global bit. I'm unable to test the effect, but it seems to be...
hw: remove error handling from qemu_malloc() callers (Avi Kivity)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6529 c046a42c-6fe2-441c-8c8c-71466251a162
Change MMIO callbacks to use offsets, not absolute addresses.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
Save/restore for stellaris boards.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4824 c046a42c-6fe2-441c-8c8c-71466251a162
Force correct evaluation order in a a == b != c condition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv7-M SysTick fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3727 c046a42c-6fe2-441c-8c8c-71466251a162
ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
arm_gic.c error message fix, by Adam Lackorzynski.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3153 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one memory region sizes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2931 c046a42c-6fe2-441c-8c8c-71466251a162
Unify IRQ handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
Arm GIC stuck interrupt fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2286 c046a42c-6fe2-441c-8c8c-71466251a162
ARM GIC bug.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2187 c046a42c-6fe2-441c-8c8c-71466251a162
Add ARM RealView Emulation Baseboard.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2164 c046a42c-6fe2-441c-8c8c-71466251a162